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Journal articles on the topic 'CMOS technology scaling'

Author: Grafiati

Published: 4 June 2021

Last updated: 7 February 2022

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1

Kocanda, Piotr, and Andrzej Kos. "Energy losses and DVFS effectiveness vs technology scaling." Microelectronics International 32, no. 3 (August 3, 2015): 158–63. http://dx.doi.org/10.1108/mi-01-2015-0008.

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Purpose – This article aims to present complete analysis of energy losses in complementary metal-oxide semiconductor (CMOS) circuits and the effectiveness of dynamic voltage and frequency scaling (DVFS) as a method of energy conservation in CMOS circuits in variety of technologies. Energy efficiency in CMOS devices is an issue of highest importance with still continuing technology scaling. There are powerful tools for energy conservation in form of dynamic voltage scaling (DVS) and dynamic frequency scaling (DFS). Design/methodology/approach – Using analytical equations and Spice models of various technologies, energy losses are calculated and effectiveness of DVS and DFS is evaluated for every technology. Findings – Test showed that new dedicated technology for low static energy consumption can be as economical as older technologies. The dynamic voltage and frequency scaling are most effective when there is a dominance of dynamic energy losses in circuit. In case when static energy losses are comparable to dynamic energy losses, use of dynamic voltage frequency scaling can even lead to increased energy consumption. Originality/value – This paper presents complete analysis of energy losses in CMOS circuits and effectiveness of mentioned methods of energy conservation in CMOS circuits in six different technologies.

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2

Nowak, E. J. "(Invited) Advanced CMOS Scaling and FinFET Technology." ECS Transactions 50, no. 9 (March 15, 2013): 3–16. http://dx.doi.org/10.1149/05009.0003ecst.

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3

Jacob, Ajey P., Ruilong Xie, Min Gyu Sung, Lars Liebmann, Rinus T. P. Lee, and Bill Taylor. "Scaling Challenges for Advanced CMOS Devices." International Journal of High Speed Electronics and Systems 26, no. 01n02 (February 17, 2017): 1740001. http://dx.doi.org/10.1142/s0129156417400018.

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The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore’s law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors.

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4

Shahidi, Ghavam G. "Chip Power Scaling in Recent CMOS Technology Nodes." IEEE Access 7 (2019): 851–56. http://dx.doi.org/10.1109/access.2018.2885895.

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Ioannou, D. E. "Scaling limits and reliability of SOI CMOS technology." Journal of Physics: Conference Series 10 (January 1, 2005): 1–6. http://dx.doi.org/10.1088/1742-6596/10/1/001.

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6

Dettmer, R. "Softly, softly [CMOS scaling advances by subthreshold technology]." IEE Review 51, no. 9 (September 1, 2005): 26–30. http://dx.doi.org/10.1049/ir:20050902.

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7

Anis, M., M. Allam, and M. Elmasry. "Impact of technology scaling on CMOS logic styles." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 49, no. 8 (August 2002): 577–88. http://dx.doi.org/10.1109/tcsii.2002.805631.

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8

Hon-Sum Wong. "Technology and device scaling considerations for CMOS imagers." IEEE Transactions on Electron Devices 43, no. 12 (1996): 2131–42. http://dx.doi.org/10.1109/16.544384.

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9

Nowak, Matt, and Brian Henderson. "Can High Density 3D Through Silicon Stacking Replace Lithography-Driven CMOS Scaling as the Engine for the Semiconductor Industry?" Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, DPC (January 1, 2011): 000458–75. http://dx.doi.org/10.4071/2011dpc-ta12.

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High density 3D Through Silicon Stacking (TSS) offers opportunities for form factor miniaturization, cost reduction, and performance and energy improvement for advanced semiconductor systems. We will explore the value propositions for TSS compared to CMOS scaling to consider if TSS could replace lithography-driven CMOS scaling as the engine for the semiconductor industry. TSS can provide major reduction in volume form factor compared to 2D CMOS scaling. As the industry moves to advanced lithography and complex device structures at 16nm and below, the cost improvement resulting from CMOS scaling is expected to diminish. The cost reduction opportunities of TSS compared to traditional System on Chip (SOC) solutions enabled by lithography-driven CMOS scaling will be explored. The realized technology value propositions are strongly dependent on the specific system architecture and application. Architectural and software innovation enabled by HD 3D TSS and Architectural Pathfinding could provide an additional vector for continuing the improvements from semiconductor miniaturization.

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10

Maimon, J., and N. Haddad. "Overcoming scaling concerns in a radiation-hardened CMOS technology." IEEE Transactions on Nuclear Science 46, no. 6 (1999): 1686–89. http://dx.doi.org/10.1109/23.819139.

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11

Awang Salleh, Dayang Nur Salmi Dharmiza, and Rohana Sapawi. "A Study on Scalability and Variation of CMOS Low Noise Amplifier in Advance CMOS Technology Processes." Applied Mechanics and Materials 833 (April 2016): 135–39. http://dx.doi.org/10.4028/www.scientific.net/amm.833.135.

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Recent technology requires multistandard Radio Frequency (RF) chips for multipurpose wireless applications. In RF circuits, a low-noise amplifier (LNA) plays the key role in determining the receiver’s performance. With CMOS technology scaling, various designs has been adopted to study circuit’s characteristic and variation. In this paper, we present the results of scalable wideband LNA design based on complementary metal oxide semiconductor (CMOS), with its variance study. The design was fabricated in 180nm, 90nm, 65nm and 40nm CMOS technology.

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12

Birla, Shilpi, Sudip Mahanti, and Neha Singh. "Leakage reduction technique for nano-scaled devices." Circuit World 47, no. 1 (May 29, 2020): 97–104. http://dx.doi.org/10.1108/cw-12-2019-0195.

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Purpose The purpose of this paper is to propose a leakage reduction technique which will works for complementary metal oxide semiconductor (CMOS) and fin field effect transistor (FinFET). Power consumption will always remain one of the major concerns for the integrated circuit (IC) designers. Presently, leakage power dominates the total power consumption, which is a severe issue. It is undoubtedly clear that the scaling of CMOS revolutionizes the IC industry. Still, on the contrary, scaling of the size of the transistor has raised leakage power as one of the significant threats to the IC industry. Scaling of the devices leads to the scaling of other device parameters, which includes threshold voltage also. The scaling of threshold voltage leads to an exponential increase in the sub-threshold current. So, many leakage reduction techniques have been proposed by researchers for CMOS from time to time. Even the other nano-scaled devices such as FinFET, carbon nanotube field effect transistor and tunneling field effect transistor, have been introduced, and FinFET is the one which has evolved as the most favorable candidate for replacing CMOS technology. Design/methodology/approach Because of its minimum leakage and without having limitation of the short channel effects, it gradually started replacing the CMOS. In this paper, the authors have proposed a technique for leakage reduction for circuits using nano-scaled devices such as CMOS and FinFET. They have compared the proposed PMOS FOOTER SLEEP with the existing leakage reduction techniques such as LECTOR technique, LECTOR FOOTER SLEEP technique. The proposed technique has been implemented using CMOS and FinFET devices. This study found that the proposed method reduces the average power, as well as leakage power reduction, for both CMOS and FinFET devices. Findings This study found that the proposed method reduces the average power as well as leakage power reduction for both CMOS and FinFET devices. The delay has been calculated for the proposed technique and the existing techniques, which verifies that the proposed technique is suitable for high-speed circuit applications. The authors have implemented higher order gates to verify the performance of the proposed circuit. The proposed method is suitable for deep-submicron CMOS technology and FinFET technology. Originality/value All the existing techniques were proposed for either CMOS device or FinFET device, but the authors have implemented all the techniques with both the devices and verified with the proposed technique for CMOS as well as FinFET devices.

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13

SHAHIDI, GHAVAM G. "ARE WE AT THE END OF CMOS SCALING?" International Journal of High Speed Electronics and Systems 16, no. 01 (March 2006): 3–8. http://dx.doi.org/10.1142/s0129156406003503.

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CMOS scaling enabled by advances in lithography has been behind the information revolution. Over the last 15 years, there has been a new CMOS technology node approximately every two years. The key feature of every node has been 2X density shrink and ~35% performance gain per technology node. At 90 nm node a number usual knobs that have enabled the scaling have approached their limits. Furthermore chip power (both active and stand-by) has been increasing rapidly, approaching air cool limit. Chip stand-by power, which was negligible a few years ago, is now about the same order of magnitude as the active power in high end microprocessors. In this talk it will be argued that because of power density limitation of 90 nm, 65 nm, and beyond nodes, performance and ability to shrink are more than ever linked, and in fact if the performance gain would significantly slow down (for the designs that operate at the existing cooling limit). It is more than ever critical to come up with technology features that will enhance the performance, at a given device leakage.

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14

Zheng, Peng, Daniel Connelly, Fei Ding, and Tsu-Jae King Liu. "FinFET Evolution Toward Stacked-Nanowire FET for CMOS Technology Scaling." IEEE Transactions on Electron Devices 62, no. 12 (December 2015): 3945–50. http://dx.doi.org/10.1109/ted.2015.2487367.

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15

Badaroglu, M., P. Wambacq, G. Van der Plas, S. Donnay, G. G. E. Gielen, and H. J. De Man. "Evolution of substrate noise generation mechanisms with CMOS technology scaling." IEEE Transactions on Circuits and Systems I: Regular Papers 53, no. 2 (February 2006): 296–305. http://dx.doi.org/10.1109/tcsi.2005.856049.

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16

Vassighi, A., O. Semenov, M. Sachdev, A. Keshavarzi, and C. Hawkins. "CMOS IC Technology Scaling and Its Impact on Burn-In." IEEE Transactions on Device and Materials Reliability 4, no. 2 (June 2004): 208–21. http://dx.doi.org/10.1109/tdmr.2004.826591.

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17

Kenkare, P. U., C. Mazure, J. D. Hayden, J. R. Pfiester, J. Ko, H. C. Kirsch, S. A. Ajuria, P. Crabtree, and T. Vuong. "Scaling of poly-encapsulated LOCOS for 0.35 μm CMOS technology." IEEE Transactions on Electron Devices 41, no. 1 (1994): 56–62. http://dx.doi.org/10.1109/16.259620.

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18

Meyer, Joseph, Reza Moghimi, and Noah Sturcken. "Package Voltage Regulators: The Answer for Power Management Challenges." International Symposium on Microelectronics 2019, no. 1 (October 1, 2019): 000438–43. http://dx.doi.org/10.4071/2380-4505-2019.1.000438.

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Abstract The generational scaling of CMOS device geometries, as predicted by Moore's law, has significantly outpaced advances in CMOS package and power electronics technology. The conduction of power to a high-performance integrated circuit (IC) die typically requires close to 50% of package and IC I/O and is increasing with trends towards lower supply voltages and higher power density that occur in advanced CMOS nodes. The disparity in scaling of logic, package, and I/O technology has created a significant bottleneck that has become a dominant constraint on computational performance. By performing power conversion and voltage regulation in-package, this limitation can be mitigated. Integration of thin-film ferromagnetic inductors with CMOS technology enables single-chip power converters to be co-packaged with processors, high bandwidth memory (HBM), and/or other modules. This paper highlights the advantages of fully integrated package voltage regulators (PVRs), which include: reducing package I/O allocated for power, eliminating the need for upstream power-conversion stages, and improving transient response. These benefits substantially reduce the size, weight, and power of modern electronic systems.

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19

Khater, Marwan H., Thomas N. Adam, Rajendran Krishnasamy, Mattias E. Dahlstrom, Jae-Sung Rieh, Kathryn T. Schonenberg, Bradly A. Orner, Francois Pagette, Kenneth Stein, and David C. Ahlgren. "PRESENT STATUS AND FUTURE DIRECTIONS OF SiGe HBT TECHNOLOGY." International Journal of High Speed Electronics and Systems 17, no. 01 (March 2007): 61–80. http://dx.doi.org/10.1142/s0129156407004254.

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The implementation of challenging novel materials and process techniques has led to remarkable device improvements in state-of-the-art high-performance SiGe HBTs, rivaling their III-V compound semiconductor counterparts. Vertical scaling, lateral scaling, and device structure innovations required to improve SiGe HBTs performance have benefited from advanced materials and process techniques developed for next generation CMOS technology. In this work, we present a review of recent process and materials development enabling operational speeds of SiGe HBTs approaching 400 GHz. In addition, we present device simulation results that show the extendibility of SiGe HBT technology performance towards half-terahertz and beyond with further scaling and device structure improvements.

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20

Reid, Dave, Campbell Millar, Scott Roy, Gareth Roy, Richard Sinnott, Gordon Stewart, Graeme Stewart, and Asen Asenov. "Enabling cutting-edge semiconductor simulation through grid technology." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 367, no. 1897 (June 28, 2009): 2573–84. http://dx.doi.org/10.1098/rsta.2009.0031.

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The progressive scaling of complementary metal oxide semiconductor (CMOS) transistors drives the success of the global semiconductor industry. Detailed knowledge of transistor behaviour is necessary to overcome the many fundamental challenges faced by chip and systems designers. Grid technology has enabled the unavoidable statistical variations introduced by scaling to be examined in unprecedented detail. Over 200 000 transistors have been simulated, the results of which provide detailed insight into underlying physical processes. This paper outlines recent scientific results of the nanoCMOS project and describes the way in which the scientific goals have been reflected in the grid-based e-Infrastructure.

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21

Heyns, M., and W. Tsai. "Ultimate Scaling of CMOS Logic Devices with Ge and III–V Materials." MRS Bulletin 34, no. 7 (July 2009): 485–92. http://dx.doi.org/10.1557/mrs2009.136.

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AbstractOver the years, many new materials have been introduced in advanced complementary metal oxide semiconductor (CMOS) processes in order to continue the trend of reducing the gate length and increasing the performance of CMOS devices. This is clearly evidenced in the International Technology Roadmap for Semiconductors (ITRS), which indicates the requirements and technological challenges in the microelectronics industry in various technology nodes. Every new technology node, characterized by the minimal device dimensions that are used, has required innovations in new materials and transistor design. The introduction of deposited high-κ gate dielectrics and metal gates as replacements for the thermally grown SiO2 and poly-Si electrode was a major challenge that has been met in the transition toward the 32 nm technology node since it replaced the heart of the metal oxide semiconductor structure. For the next generation of technology nodes, even bigger hurdles will need to be overcome, since new device structures and high-mobility channel materials such as Ge and III–V compounds might be needed, according to the ITRS roadmap, to meet the power and performance specifications of the 16 nm CMOS node and beyond. The basic properties of these high-mobility channel materials and their impact on the device performance have to be fully understood to allow process integration and full-scale manufacturing. In addition to thermal stability, compatibility with other materials, electronic transport properties, and especially the passivation of electronically active defects at the interface with a high-κ dielectric, are enormous challenges. Many encouraging results have been obtained, but the stringent demands in terms of electrical performance and oxide thickness scaling needed for highly scaled CMOS devices are not yet fully met. Other areas where breakthroughs will be needed are the formation of low-resistivity contacts, especially on III–V materials, and III–V materials suited for pMOS channels. An overview of the major successes and remaining critical issues in the materials research on high-mobility channel materials for advanced CMOS devices is given in this issue of MRS Bulletin.

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22

Kerber, Andreas. "Reliability of Metal Gate / High-k devices and its impact on CMOS technology scaling." MRS Advances 2, no. 52 (2017): 2973–82. http://dx.doi.org/10.1557/adv.2017.504.

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ABSTRACTMG/HK was introduced into CMOS technology and enabled scaling beyond the 45/32nm technology node. The change in gate stack from poly-Si/SiON to MG/HK introduced new reliability challenges like the positive bias temperature instability (PBTI) and stress induced leakage currents (SILC) in nFET devices which prompted thorough investigation to provide fundamental understanding of these degradation mechanisms and are nowadays well understood. The shift to a dual-layer gate stack also had a profound impact on the time dependent dielectric breakdown (TDDB) introducing a strong polarity dependence in the model parameter. As device scaling continues, stochastic modeling of variability, both at time zero and post stress due to BTI, becomes critical especially for SRAM circuit aging. As we migrate towards novel device architectures like bulk FinFET, SOI FinFETs, FDSOI and gate-all-around devices, impact of self-heating needs to be accounted for in reliability testing.In this paper we summarize the fundamentals of MG/HK reliability and discuss the reliability and characterization challenges related to the scaling of future CMOS technologies.

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23

Garrou, Philip. "3D IC Technology: the Perfect Storm." International Symposium on Microelectronics 2010, no. 1 (January 1, 2010): 000001–6. http://dx.doi.org/10.4071/isom-2010-ta1-paper1.

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IC technology, which has traditionally been dominated by dimensional scaling, is facing several technical and economic hurdles as it moves forward. Low K insulation has not been able to meet performance projections, copper traces are becoming more and more resistive, clock rates have been constrained due to thermal issues and multicore processors are demanding major increases in bandwidth and decreases in latency. Economic constraints will also begin limiting the number of IC companies able to develop leading-edge IC designs. Moving past 45 nm digital CMOS scaling will no longer guarantee lower cost and higher performance. All of these issues have crated a “perfect storm scenario” for the widespread adoption of 3D IC technology.

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Dhar, Subhra, Manisha Pattanaik, and Poolla Rajaram. "Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications." VLSI Design 2011 (May 26, 2011): 1–19. http://dx.doi.org/10.1155/2011/178516.

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In recent years, the demand for power sensitive designs has grown significantly due to the fast growth of battery-operated portable applications. As the technology scaling continues unabated, subthreshold device design has gained a lot of attention due to the low-power and ultra-low-power consumption in various applications. Design of low-power high-performance submicron and deep submicron CMOS devices and circuits is a big challenge. Short-channel effect is a major challenge for scaling the gate length down and below 0.1 μm. Detailed review and potential solutions for prolonging CMOS as the leading information technology proposed by various researchers in the past two decades are presented in this paper. This paper attempts to categorize the challenges and solutions for low-power and low-voltage application and thus provides a roadmap for device designers working in the submicron and deep submicron region of CMOS devices separately.

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Hu, Jian Ping, and Jia Guo Zhu. "Voltage Scaling for SRAM in 45nm CMOS Process." Applied Mechanics and Materials 39 (November 2010): 253–59. http://dx.doi.org/10.4028/www.scientific.net/amm.39.253.

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Scaling supply voltage is an efficient approach to achieve low energy. Scaling supply voltage to sub-threshold region can reach minimum energy consumption but only suits for ultra-low operation frequencies. In order to attain more extensive application, scaling supply voltage to medium-voltage region is an attractive approach especially suiting for mid performances. This paper investigates performances of conventional SRAMs in near-threshold and super-threshold regions in terms of energy dissipation and max operating frequency. All circuits are simulated with HSPICE at PTM 45nm CMOS technology by varying supply voltages from 0.4V to 1.1V with 0.1V steps. The simulation results demonstrate that the conventional SRAMs operate on medium-voltage region can not only keep reasonable speed but also reduce greatly energy consumptions.

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26

Walko, J. "Scaling is dead, long live innovation! [90 nm CMOS process technology]." IEE Review 50, no. 6 (June 1, 2004): 23. http://dx.doi.org/10.1049/ir:20040601.

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27

Hassan, Hassan, Mohab Anis, and Mohamed Elmasry. "Impact of technology scaling and process variations on RF CMOS devices." Microelectronics Journal 37, no. 4 (April 2006): 275–82. http://dx.doi.org/10.1016/j.mejo.2005.07.013.

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28

Semenov, O., A. Vassighi, M. Sachdev, A. Keshavarzi, and C. F. Hawkins. "Effect of cmos technology scaling on thermal management during burn-in." IEEE Transactions on Semiconductor Manufacturing 16, no. 4 (November 2003): 686–95. http://dx.doi.org/10.1109/tsm.2003.818985.

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29

Hokazono, A., S. Balasubramanian, K. Ishimaru, H. Ishiuchi, C. Hu, and T. J. K. Liu. "Forward Body Biasing as a Bulk-Si CMOS Technology Scaling Strategy." IEEE Transactions on Electron Devices 55, no. 10 (October 2008): 2657–64. http://dx.doi.org/10.1109/ted.2008.2003029.

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30

Song, Yi, Huajie Zhou, Qiuxia Xu, Jun Luo, Haizhou Yin, Jiang Yan, and Huicai Zhong. "Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status." Journal of Electronic Materials 40, no. 7 (May 15, 2011): 1584–612. http://dx.doi.org/10.1007/s11664-011-1623-z.

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31

FLYNN, MICHAEL P., SUNGHYUN PARK, and CHUN C. LEE. "ACHIEVING ANALOG ACCURACY IN NANOMETER CMOS." International Journal of High Speed Electronics and Systems 15, no. 02 (June 2005): 255–75. http://dx.doi.org/10.1142/s0129156405003193.

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This paper reviews causes of and trends in MOS transistor mismatch, and assesses the implications for analog circuit design in the nanometer régime. The current understanding of MOS transistor mismatch is reviewed. In most cases, transistor mismatch is dominated by threshold voltage mismatch. Although, there is strong evidence that VT matching is improving as CMOS technology evolves, these improvements are countered by reductions in power supply that also accompany process scaling. In fact, the power consumption of analog circuits based on current design styles will increase with scaling to finer processes. It has long been known that thermal noise causes the power consumption of analog circuits to increase with scaling. However, unlike the case with thermal noise, new circuit techniques can break the accuracy-power constraints related to mismatch. These techniques are based on analog circuit redundancy, and take advantage of the tremendous transistor density offered by nanometer CMOS. This paper is primarily concerned with comparators, and in particular, with the use of comparators in flash ADCs; however, the analysis is also applicable to other circuits and applications.

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Viswadha, Singathala Guru. "Next Generation Computing Using Quantum Dot Cellular Automata Nano Technology, New Promising Alternative to CMOS." Asian Journal of Computer Science and Technology 8, S3 (June 5, 2019): 19–24. http://dx.doi.org/10.51983/ajcst-2019.8.s3.2111.

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CMOS technology is one of the most popular technology in the computer chip design industry and broadly used today to form integrated circuits in numerous and varied applications and it has transformed the field of electronics. Over the time the design methodologies and processing technologies of CMOS devices have greatest activity with the Moore’s law. Now CMOS technology has to face challenges to survive through the submicron ranges. The scaling in CMOS has reached higher limit, not only from technological and Physical point of view but also from economical and material aspects. This concept inspires the researches to look for new alternatives to CMOS which gives better performance and power consumption. One of the alternative technologies to digital designing in CMOS is the Quantum dot Cellular Automata (QCA). QCA is a technology it works on Electronic interaction between the cells. The QCA cell basically consists of Quantum dots separated by certain distance. The transmission of information done via the interaction between the Electrons present in these quantum dots. In this paper the limitations to CMOS in submicron range and concepts for designing in QCA have been discussed and also the building blocks are explained using QCA designer implementations with focus on cell interaction and clocking mechanism.

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Pankiewicz, B. "Multiple output CMOS current amplifier." Bulletin of the Polish Academy of Sciences Technical Sciences 64, no. 2 (June 1, 2016): 301–6. http://dx.doi.org/10.1515/bpasts-2016-0034.

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Abstract In this paper the multiple output current amplifier basic cell is proposed. The triple output current mirror and current follower circuit are described in detail. The cell consists of a split nMOS differential pair and accompanying biasing current sources. It is suitable for low voltage operation and exhibits highly linear DC response. Through cell devices scaling, not only unity, but also any current gains are achievable. As examples, a current amplifier and bandpass biquad section designed in CMOS TSMC 90nm technology are presented. The current amplifier is powered from a 1.2V supply. MOS transistors scaling was chosen to obtain output gains equal to -2, 1 and 2. Simulated real gains are -1.941, 0.966 and 1.932 respectively. The 3dB passband obtained is above 20MHz, while current consumption is independent of input and output currents and is only 7.77μA. The bandpass biquad section utilises the previously presented amplifier, two capacitors and one resistor, and has a Q factor equal to 4 and pole frequency equal to 100 kHz.

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Wang, Lei, CiHui Yang, Jing Wen, and Shan Gai. "Emerging Nonvolatile Memories to Go Beyond Scaling Limits of Conventional CMOS Nanodevices." Journal of Nanomaterials 2014 (2014): 1–10. http://dx.doi.org/10.1155/2014/927696.

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Continuous dimensional scaling of the CMOS technology, along with its cost reduction, has rendered Flash memory as one of the most promising nonvolatile memory candidates during the last decade. With the Flash memory technology inevitably approaching its fundamental limits, more advanced storage nanodevices, which can probably overcome the scaling limits of Flash memory, are being explored, bringing about a series of new paradigms such as FeRAM, MRAM, PCRAM, and ReRAM. These devices have indeed exhibited better scaling capability than Flash memory while also facing their respective physical drawbacks. The consequent tradeoffs therefore drive the information storage device technology towards further advancement; as a result, new types of nonvolatile memories, including carbon memory, Mott memory, macromolecular memory, and molecular memory have been proposed. In this paper, the nanomaterials used for these four emerging types of memories and the physical principles behind the writing and reading methods in each case are discussed, along with their respective merits and drawbacks when compared with conventional nonvolatile memories. The potential applications of each technology are also briefly assessed.

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35

Mohamed, Khaled Salah. "Work around Moore’s Law: Current and next Generation Technologies." Applied Mechanics and Materials 110-116 (October 2011): 3278–83. http://dx.doi.org/10.4028/www.scientific.net/amm.110-116.3278.

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Interconnect dimensions and CMOS transistor feature size approach their physical limits, therefore scaling will no longer play an important role in performance improvement. So, instead of trying to improve the performance of traditional CMOS circuits, integration of multiple technologies and different components in a heterogeneous system that is high performance will be introduced “moore than more” and CMOS replacement”beyond CMOS” will be explored. This paper focuses on Technology level trends where it presents “More Moore”:New Architectures (SOI, FinFET, Twin-Well),”More Moore” :New Materials (High-K, Metal Gate, Strained-Si) ,”More than Moore”:New Interconnects Schemes (3D, NoC, Optical, Wireless), and ”Beyond CMOS” :New Devices (Molecular Computer, Biological computer, Quantum Computer) .

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Lu, Bin Bin, and Jian Ping Hu. "Complementary Pass-Transistor Adiabatic Logic Using Dual Threshold CMOS Techniques." Applied Mechanics and Materials 39 (November 2010): 55–60. http://dx.doi.org/10.4028/www.scientific.net/amm.39.55.

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With rapid technology scaling down, the energy dissipation of nanometer CMOS circuits is becoming a major concern, because of the increasing sub-threshold leakage in nanometer CMOS processes. This paper introduces a dual threshold CMOS (DTCMOS) technique for CPAL (complementary pass-transistor adiabatic logic) circuits to reduce sub-threshold leakage dissipations. The method to size the transistors of the dual-threshold CPAL gates is also discussed. A full adder using dual-threshold CPAL circuits is realized using 45nm BSIM4 CMOS model. HSPICE simulation results show that leakage dissipations of the CPAL full adder with DTCMOS techniques are reduced compared with the basic CPAL one.

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Boselli, G., V. Reddy, and C. Duvvury. "Impact of Scaling on the High Current Behavior of RF CMOS Technology." IEEE Transactions on Device and Materials Reliability 4, no. 3 (September 2004): 542–48. http://dx.doi.org/10.1109/tdmr.2004.836163.

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Jan, Chia-Hong. "CMOS Technology Scaling for System-On-Chip Integration - Past, Present and Future." ECS Transactions 44, no. 1 (December 15, 2019): 451–70. http://dx.doi.org/10.1149/1.3694354.

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Hazucha, P., and C. Svensson. "Impact of CMOS technology scaling on the atmospheric neutron soft error rate." IEEE Transactions on Nuclear Science 47, no. 6 (2000): 2586–94. http://dx.doi.org/10.1109/23.903813.

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Deng, Jie, Keunwoo Kim, Ching-Te Chuang, and H. S. Philip Wong. "The Impact of Device Footprint Scaling on High-Performance CMOS Logic Technology." IEEE Transactions on Electron Devices 54, no. 5 (May 2007): 1148–55. http://dx.doi.org/10.1109/ted.2007.894596.

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Carusone, Anthony Chan, Hemesh Yasotharan, and Tony Kao. "CMOS Technology Scaling Considerations for Multi-Gbps Optical Receivers With Integrated Photodetectors." IEEE Journal of Solid-State Circuits 46, no. 8 (August 2011): 1832–42. http://dx.doi.org/10.1109/jssc.2011.2157254.

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Dhaou, Imed Ben, Keshab K. Parhi, and Hannu Tenhunen. "Energy Efficient Signaling in Deep-submicron Technology." VLSI Design 15, no. 3 (January 1, 2002): 563–86. http://dx.doi.org/10.1080/1065514021000012192.

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In deep-submicron technology, global interconnect capacitances have started reaching several orders of magnitude greater than the intrinsic capacitances of the CMOS gates. The dynamic power consumption of a CMOS gate driving a global wire is the sum of the power dissipated due to (dis)charging (i) the intrinsic capacitance of the gate, and (ii) the wire capacitance. The latter is referred to as on-chip signaling power consumption. In this paper, a scheme has been proposed for combating crosstalk noise and reducing power consumption while driving the global wire at an optimal delay. This scheme is based on reduced voltage-swing signaling combined with buffer-insertion and resizing. The buffers are inserted and resized to compensate for the speed degradation caused by scaling the supply voltage and eradicating the crosstalk noise. A new buffer insertion algorithm called VIJIM has been described here, along with accurate delay and crosstalk-noise estimation algorithms for distributed RLC wires. The experimental results show that the VIJIM algorithm inserts fewer buffers into non-critical nets than does the existing buffer-insertion algorithms. In a 0.25 mm CMOS process, the experimental results show that energy savings of over 60% can be achived if the supply voltage is reduced from 2.5 to 1.5 V.

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Angelov, George V., Dimitar N. Nikolov, and Marin H. Hristov. "Technology and Modeling of Nonclassical Transistor Devices." Journal of Electrical and Computer Engineering 2019 (November 3, 2019): 1–18. http://dx.doi.org/10.1155/2019/4792461.

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This paper presents a comprehensive outlook for the current technology status and the prospective upcoming advancements. VLSI scaling trends and technology advancements in the context of sub-10-nm technologies are reviewed as well as the associated device modeling approaches and compact models of transistor structures are considered. As technology goes into the nanometer regime, semiconductor devices are confronting numerous short-channel effects. Bulk CMOS technology is developing and innovating to overcome these constraints by introduction of (i) new technologies and new materials and (ii) new transistor architectures. Technology boosters such as high-k/metal-gate technologies, ultra-thin-body SOI, Ge-on-insulator (GOI), AIII–BV semiconductors, and band-engineered transistor (SiGe or Strained Si-channel) with high-carrier-mobility channels are examined. Nonclassical device structures such as novel multiple-gate transistor structures including multiple-gate field-effect transistors, FD-SOI MOSFETs, CNTFETs, and SETs are examined as possible successors of conventional CMOS devices and FinFETs. Special attention is devoted to gate-all-around FETs and, respectively, nanowire and nanosheet FETs as forthcoming mainstream replacements of FinFET. In view of that, compact modeling of bulk CMOS transistors and multiple-gate transistors are considered as well as BSIM and PSP multiple-gate models, FD-SOI MOSFETs, CNTFET, and SET modeling are reviewed.

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Li, Hong, Jia Guo Zhu, and Jian Ping Hu. "A Single-Phase Energy-Recovery Register Using Drowsy Cache and MTCMOS Techniques for Leakage Reductions." Applied Mechanics and Materials 29-32 (August 2010): 1937–42. http://dx.doi.org/10.4028/www.scientific.net/amm.29-32.1937.

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With rapid technology scaling, the leakage dissipation is becoming a major source in CMOS circuits because of the increasing sub-threshold and gate leakage current in nanometer CMOS processes. This paper presents an adiabatic register file based on improved CAL (Clocked Adiabatic Logic) using MTCMOS power-gating and drowsy cache techniques to reduce both sub-threshold leakage and gate oxide leakage current dissipations. A 32 X 32 single-phase adiabatic register file are verified using HSPICE. BSIM4 model is adopted to reflect leakage currents in nanometer CMOS processes with gate oxide materials. Simulation results show that leakage losses are greatly reduced.

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Hussain, Inamul, and Saurabh Chaudhury. "CNFET Based Low Power Full Adder Circuit for VLSI Applications." Nanoscience & Nanotechnology-Asia 10, no. 3 (June 17, 2020): 286–91. http://dx.doi.org/10.2174/2210681209666190220122553.

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Background: The Adder is one of the most prominent building blocks in VLSI circuits and systems. Performance of such systems depends mostly on the performance of the adder cell. The scaling down of devices has been the driving force in technological advances. However, in CMOS technology performance of adder cell decreases as technology node scaled down to deep micron regime. Objective: With the growth of research, new device model has been proposed based on carbon nano tube field effect transistor (CNFET). Therefore, there is a need of full adder cell, which performs sufficiently well in CNFET as well as different CMOS technology nodes. Method: A new low power full adder cell has been proposed with a hybrid XOR/XNOR module by using CNFET, which is also compatible for the CMOS technology nodes. The performance of the adder cell is validated with HSPICE simulation in terms of power, delay and power delay product. It is observed that the proposed adder cell performs better than the CMOS, CPL, TGA, 10 T, 14 T, 24 T, HSPC and Hybrid_FA adder cells. The CNFET full adder is designed in 32 nm CNFET model and to appraise its compatibility with Bulk-Si CMOS technology, 90 nm and 32 nm CMOS technology node is used. Conclusion: The proposed adder is very much suitable for both CMOS and CNFET technology based circuits and systems. To validate the result, simulation has been carried out with Synopsis tool. This full adder will definitely dominate other full adder cells at various technology nodes for VLSI applications.

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Bae, Woorham. "CMOS Inverter as Analog Circuit: An Overview." Journal of Low Power Electronics and Applications 9, no. 3 (August 20, 2019): 26. http://dx.doi.org/10.3390/jlpea9030026.

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Since the CMOS technology scaling has focused on improving digital circuit, the design of conventional analog circuits has become more and more difficult. To overcome this challenge, there have been a lot of efforts to replace conventional analog circuits with digital implementations. Among those approaches, this paper gives an overview of the latest achievement on utilizing a CMOS inverter as an analog circuit. Analog designers have found that a simple resistive feedback pulls a CMOS inverter into an optimum biasing for analog operation. Recently developed applications of the resistive-feedback inverter, including CMOS inverter as amplifier, high-speed buffer, and output driver for high-speed link, are introduced and discussed in this paper.

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SPEDO, SERGIO, and CLAUDIO FIEGNA. "SIMULATION OF THERMAL NOISE IN SCALED MOSFETS." Fluctuation and Noise Letters 02, no. 02 (June 2002): L109—L116. http://dx.doi.org/10.1142/s0219477502000683.

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In this work, hydrodynamic device simulations and a post-processor for the simulation of noise in MOSFETs are applied in order to evaluate the impact of scaling on the thermal noise of transistors representative of technologies with minimum gate length scaled from 0.25 μm down to 0.1 μm. The dependences on bias and technology scaling of the spectral densities of the equivalent drain- and induced gate-noise currents are anayzed in details. The effect of technology scaling on the two-port noise parameters of the intrinsic MOSFET is studied as well. The results of this work confirm that the transistor's noise performance tend to improve as the technology is scaled down, making CMOS a suitable technological option for the implementation of advanced low-power RF systems.

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Sharma, Suruchi, Santosh Kumar, Alok Kumar Mishra, D. Vaithiyanathan, and Baljit Kaur. "Process, Voltage, and Temperature Aware Analysis of ISCAS C17 Benchmark Circuit." Advanced Science, Engineering and Medicine 12, no. 10 (October 1, 2020): 1289–95. http://dx.doi.org/10.1166/asem.2020.2707.

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High leakage currents such as sub-threshold leakage, junction leakage, and gate leakage currents have become prominent sources of power consumption in CMOS VLSI circuits due to rapid technology scaling in the nanometer regimen accompanied by supply voltage reduction. Consequently, in the nanometer regime, it is imperative to estimate and reduce leakage capacity. However, this continuous aggressive scaling makes the CMOS circuits more prone to Process, Voltage, and Temperature (PVT) variations at nanometer technologies. This paper explores a systematic analysis of various leakage power reduction techniques at the circuit level, such as Power Gating (PG), Drain Gating (DG), LECTOR and GALEOR, and analyzes the effect of PVT variations on the dissipation and delay of leakage power using the ISCAS C17 benchmark circuit.

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Wong, Hei, and Hiroshi Iwai. "On the scaling of subnanometer EOT gate dielectrics for ultimate nano CMOS technology." Microelectronic Engineering 138 (April 2015): 57–76. http://dx.doi.org/10.1016/j.mee.2015.02.023.

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Liu, Qing, Atsushi Yagishita, Arvind Kumar, Nicolas Loubet, Toyoji Yamamoto, Pranita Kulkarni, Frederic Monsieur, et al. "Ultra-Thin Body and BOX (UTBB) Device for Aggressive Scaling of CMOS Technology." ECS Transactions 34, no. 1 (December 16, 2019): 37–42. http://dx.doi.org/10.1149/1.3567556.

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