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1

Lauer, Isaac 1976. "Double-sided CMOS fabrication technology." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/86778.

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2

Tsang, Yuk Lun. "Modelling for Strained Silicon CMOS Technology." Thesis, University of Newcastle upon Tyne, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.485865.

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The metal-oxide-semiconductor field effect transistor (MOSFET) has been scaling down aggressively over many technology nodes in order to follow Moore's Law predictions. Strain engineering to the device channel can modify the band structure and so enhance carrier mobility. It has widely been incorporated to improve device performance. Novel modelling techniques, including strain effects, are necessarily required. The electrical characteristics of semiconductor hav9r.their origin in energy band structure. In this thesis, a new semi-analytical model is developed lor describing the energy band structure under strain conditions. Furthermore, the band parameters of the SiGe heterojunction are generalised for different combinations of Ge fractions. Those results can be used to understand and to model the transport properties of carriers and the variation of threshold voltage measured from strained Si MOSFETs. The calculated band parameters are then entered into a newly developed model to calculate the threshold voltage variation in strained Si MOSFETs having a dual channel architecture. Finally, understanding the strain effects on the band structure is extended to the modelling of strained-induced variation of carrier mobility using the piezoresistance concept. The overviews of each main-result chapter in this thesis are given below: In Chapter 3, model using the original k'p method for the energy dispersion of holes in the inversion layer of p-MOSFETs is complicated and demands extensive computational resource. Those are the reasons why the development of simulations for p-MOSFETs lagged behind their n-MOSFET counterpart. In this work, the band structure for holes in an inversion layer is dramatically simplified using a new semi-analytical model. It is described by novel non-parabolic and anisotropic expressions such that the overall computational complexity is significantly reduced compared to a fully numerical treatment. Here, the band parameters are also generalised for different Ge fractions in a SiJ-xGexfilm grown on a relaxed SiJ.yGeyvirtual substrate. In Chapter 4, an analytical model of threshold voltage for globally strained SiiSiGe CMOS devices using a dual channel architecture is developed. A model to calculate threshold voltage is developed which includes effects of device geometry, material properties, such as band parameters and permittivity, and channel and substrate doping concentrations. The threshold voltage roll-off due to short channel effects is included using the voltage-doping transformation. The proposed model is validated in agreement with simulations and experiments. It provides a physical insight for the variation of threshold voltage for both n- and p-MOSFETs having a dual channel architecture and it can be generalised to apply to single channel devices also. In Chapter 5, the conventional piezoresistance model has commonly been used to describe mobility enhancement for low levels of process induced strain in CMOS technology. However, many reports show it failing at the high levels of stress needed for future technology generations. This is because approximations made are only valid for very low stress levels. The piezomobility formulation removes an approximation assumed in the commonly-used piezoresistance model and improves its accuracy to much higher stress regimes while retaining its simplicity. The validity of the new formulation is demonstrated for Monte Carlo simulations of mobility, nMOSFETs, pMOSFETs, and nanowires in stress regimes where the commonly-used piezoresistance model has previously been reported to fail.
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3

Afshar-Hanaii, Nasser. "Some aspects of submicron CMOS technology." Thesis, University of Southampton, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.358782.

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4

Michelon, Dino. "UHF energy harvester in CMOS technology." Thesis, Aix-Marseille, 2016. http://www.theses.fr/2016AIXM4322.

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Un des défis majeurs de l’Internet des Objets et, plus généralement, des tous les réseaux de capteurs sans fils, c’est l’alimentation de chaque nœud connecté. La solution la plus commune est d’équiper chaque dispositif d’une batterie mais cela introduit plusieurs contraintes, qui mettent en question la faisabilité de cette approche sur le long terme (durée de vie limité, couts de gestion élevé, empreinte écologique).Cette thèse développe une possible solution basée sur la transmission sans-fils de l’énergie. Un récupérateur d’énergie RF, composé d’une antenne, un redresseur haute-fréquence et un convertisseur élévateur, est présenté. Ce système permet de récupérer les ondes électromagnétiques et de produire une tension continue en sortie, qui peut être utilisé pour alimenter des microcontrôleurs ou des capteurs. L’absence d’une batterie interne augmente la flexibilité globale, surtout pour les situations où le remplacement n’est pas possible (ex. dispositifs implantés, nombre élevé de nœuds, milieux dangereux). Une étude approfondie sur les redresseur intégrés ultra-haute-fréquence de type Schottky et MOS a été mené ; plusieurs topologies ont été analysées et optimisées. De plus, l’utilisation d’un convertisseur élévateur a été envisagée, dans le but d’accroitre la tension en sortie ; une première version discrète et puis une plus compacte version intégrée, ont été abordées et testées. Ces développements ont permis d’aboutir à un récupérateur complet, potentiellement capable d’alimenter un microcontrôleur du commerce<br>One of the challenges of the Internet of Things and, more in general, of every wireless sensor network is to provide electrical power to every single one of its smart nodes. A typical solution uses batteries but various major concerns reduce the long-term feasibility of this approach (limited lifetime, maintenance and replacement costs, and environmental footprint).This thesis develops a possible solution based on the wireless transmission of power. A complete RF harvester composed of an antenna, a UHF rectifier and a step-up voltage converter is presented. This system captures electromagnetic waves and converts them to a stable DC voltage to supply power to common logic circuits like microcontrollers and sensors. The lack of an internal battery provides an extended flexibility, especially when its replacement is not a viable option (ex. implanted devices, large number of nodes, dangerous environments, etc.). An in-depth study of integrated Schottky and CMOS UHF rectifiers is carried out; various topologies and optimizations are analyzed. Moreover, the use of an additional step-up converter is proposed in order to increase the system output voltage; an early discrete implementation and a final, more compact, integrated version are discussed and tested. These developments lead to a complete system capable of potentially powering an application with an off-the-shelf microcontroller
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5

Colombo, Dalton Martini. "Bandgap voltage references in submicrometer CMOS technology." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2009. http://hdl.handle.net/10183/16136.

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Referências de tensão são blocos fundamentais em uma série de aplicações de sinais mistos e de rádio frequência, como por exemplo, conversores de dados, PLL's e conversores de potência. A implementação CMOS mais usada para referências de tensão é o circuito Bandgap devido sua alta previbilidade, e baixa dependência em relação à temperatura e tensão de alimentação. Este trabalho estuda aplicação de Referência de Tensão Bandgap. O princípio, as topologias tradicionalmente usadas para implementar este método e as limitações que essas arquiteturas sofrem são investigadas. Será também apresentada uma pesquisa das questões recentes envolvendo alta precisão, operação com baixa tensão de alimentação e baixa potência, e ruído de saída para as referências Bandgap fabricadas em tecnologias submicrométricas. Além disso, uma investigação abrangente do impacto causado pelo o processo da fabricação e do ruído no desempenho da referência é apresentada. Será mostrado que o ruído de saída pode limitar a precisão dos circuitos Bandgap e seus circuitos de ajuste. Para desenvolver nosso trabalho, três Referências Bandgap foram projetadas utilizando o processo IBM 7RF 0.18 micra com uma tensão de alimentação de 1.8V. Também foram projetados os leiautes desses circuitos para prover informações pósleiaute extraídos e resultados de simulação elétrica. Este trabalho provê uma discussão de algumas topologias e das práticas de projeto para referências Bandgap.<br>A Voltage Reference is a pivotal block in several mixed-signal and radio-frequency applications, for instance, data converters, PLL's and power converters. The most used CMOS implementation for voltage references is the Bandgap circuit due to its highpredictability, and low dependence of the supply voltage and temperature of operation. This work studies the Bandgap Voltage References (BGR). The most relevant and the traditional topologies usually employed to implement Bandgap Voltage References are investigated, and the limitations of these architectures are discussed. A survey is also presented, discussing the most relevant issues and performance metrics for BGR, including, high-accuracy, low-voltage and low-power operation, as well as the output noise of Bandgap References fabricated in submicrometer technologies. Moreover, a comprehensive investigation on the impact of fabrication process effects and noise on the reference voltage is presented. It is shown that output noise can limit the accuracy of the BGR and trim circuits. To support and develop our work, three BGR´s were designed using the IBM 0.18 Micron 7RF process with a supply voltage of 1.8 V. The layouts of these circuits were also designed to provide post-extracted layout information and electrical simulation results. This work provides a comprehensive discussion on the structure and design practices for Bandgap References.
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6

Rochas, Alexis. "Single photon avalanche diodes in CMOS technology /." [S.l.] : [s.n.], 2003. http://library.epfl.ch/theses/?nr=2814.

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7

Wang, Peng-Fei. "Complementary tunneling-FETs (CTFET) in CMOS technology." [S.l.] : [s.n.], 2003. http://deposit.ddb.de/cgi-bin/dokserv?idn=970218257.

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8

Sjöblom, Gustaf. "Metal Gate Technology for Advanced CMOS Devices." Doctoral thesis, Uppsala University, Solid State Electronics, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-7120.

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<p>The development and implementation of a metal gate technology (alloy, compound, or silicide) into metal-oxide-semiconductor field effect transistors (MOSFETs) is necessary to extend the life of planar CMOS devices and enable further downscaling. This thesis examines possible metal gate materials for improving the performance of the gate stack and discusses process integration as well as improved electrical and physical measurement methodologies, tested on capacitor structures and transistors. </p><p>By using reactive PVD and gradually increasing the N<sub>2</sub>/Ar flow ratio, it was found that the work function (on SiO<sub>2</sub>) of the TiN<sub>x</sub> and ZrN<sub>x</sub> metal systems could be modulated ~0.7 eV from low near nMOS work functions to high pMOS work functions. After high-temperature anneals corresponding to junction activation, both metals systems reached mid-gap work function values. The mechanisms behind the work function changes are explained with XPS data and discussed in terms of metal gradients and Fermi level pinning due to extrinsic interface states.</p><p>A modified scheme for improved Fowler-Nordheim tunnelling is also shown, using degenerately doped silicon substrates. In that case, the work functions of ALD/PVD TaN were accurately determined on both SiO<sub>2</sub> and HfO<sub>2</sub> and benchmarked against IPE (Internal Photoemission) results. KFM (Kelvin Force Microscopy) was also used to physically measure the work functions of PVD TiN and Mo deposited on SiO<sub>2</sub>; the results agreed well with <i>C-V</i> and <i>I-V</i> data.</p><p>Finally, an appealing combination of novel materials is demonstrated with ALD TiN/Al<sub>2</sub>O<sub>3</sub>/HfAlO<sub>x</sub>/Al<sub>2</sub>O<sub>3</sub>/strained-SiGe surface channel pMOS devices. The drive current and transconductance were measured to be 30% higher than the Si reference, clearly demonstrating increased mobility and the absence of polydepletion. Finally, using similarly processed transistors with Al<sub>2</sub>O<sub>3</sub> dielectric instead, low-temperature water vapour annealing was shown to improve the device characteristics by reducing the negative charge within the ALD Al<sub>2</sub>O<sub>3</sub>.</p>
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9

Sjöblom, Gustaf. "Metal gate technology for advanced CMOS devices /." Uppsala : Acta Universitatis Upsaliensis, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-7120.

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10

Armstrong, Mark Albert. "Technology for SiGe heterostructure-based CMOS devices." Thesis, Massachusetts Institute of Technology, 1999. http://hdl.handle.net/1721.1/9339.

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Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.<br>Includes bibliographical references (p. 133-140).<br>by Mark Albert Armstrong.<br>Ph.D.
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11

Khatib, Moustafa. "THz Radiation Detection Based on CMOS Technology." Doctoral thesis, Università degli studi di Trento, 2019. https://hdl.handle.net/11572/368305.

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The Terahertz (THz) band of the electromagnetic spectrum, also defined as sub-millimeter waves, covers the frequency range from 300 GHz to 10 THz. There are several unique characteristics of the radiation in this frequency range such as the non-ionizing nature, since the associated power is low and therefore it is considered as safe technology in many applications. THz waves have the capability of penetrating through several materials such as plastics, paper, and wood. Moreover, it provides a higher resolution compared to conventional mmWave technologies thanks to its shorter wavelengths. The most promising applications of the THz technology are medical imaging, security/surveillance imaging, quality control, non-destructive materials testing and spectroscopy. The potential advantages in these fields provide the motivation to develop room-temperature THz detectors. In terms of low cost, high volume, and high integration capabilities, standard CMOS technology has been considered as an excellent platform to achieve fully integrated THz imaging systems. In this Ph.D. thesis, we report on the design and development of field effect transistor (FET) THz direct detectors operating at low THz frequency (e.g. 300 GHz), as well as at higher THz frequencies (e.g. 800 GHz – 1 THz). In addition, we investigated the implementation issues that limit the power coupling efficiency with the integrated antenna, as well as the antenna-detector impedance-matching condition. The implemented antenna-coupled FET detector structures aim to improve the detection behavior in terms of responsivity and noise equivalent power (NEP) for CMOS based imaging applications. Since the detected THz signals by using this approach are extremely weak with limited bandwidth, the next section of this work presents a pixel-level readout chain containing a cascade of a pre-amplification and noise reduction stage based on a parametric chopper amplifier and a direct analog-to-digital conversion by means of an incremental Sigma-Delta converter. The readout circuit aims to perform a lock-in operation with modulated sources. The in-pixel readout chain provides simultaneous signal integration and noise filtering for the multi-pixel FET detector arrays and hence achieving similar sensitivity by the external lock-in amplifier. Next, based on the experimental THz characterization and measurement results of a single pixel (antenna-coupled FET detector + readout circuit), the design and implementation of a multispectral imager containing 10 x 10 THz focal plane array (FPA) as well as 50 x 50 (3T-APS) visible pixels is presented. Moreover, the readout circuit for the visible pixel is realized as a column-level correlated double sampler. All of the designed chips have been implemented and fabricated in 0.15-µm standard CMOS technology. The physical implementation, fabrication and electrical testing preparation are discussed.
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12

Khatib, Moustafa. "THz Radiation Detection Based on CMOS Technology." Doctoral thesis, University of Trento, 2019. http://eprints-phd.biblio.unitn.it/3644/1/PhD_Thesis_MK_final.pdf.

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The Terahertz (THz) band of the electromagnetic spectrum, also defined as sub-millimeter waves, covers the frequency range from 300 GHz to 10 THz. There are several unique characteristics of the radiation in this frequency range such as the non-ionizing nature, since the associated power is low and therefore it is considered as safe technology in many applications. THz waves have the capability of penetrating through several materials such as plastics, paper, and wood. Moreover, it provides a higher resolution compared to conventional mmWave technologies thanks to its shorter wavelengths. The most promising applications of the THz technology are medical imaging, security/surveillance imaging, quality control, non-destructive materials testing and spectroscopy. The potential advantages in these fields provide the motivation to develop room-temperature THz detectors. In terms of low cost, high volume, and high integration capabilities, standard CMOS technology has been considered as an excellent platform to achieve fully integrated THz imaging systems. In this Ph.D. thesis, we report on the design and development of field effect transistor (FET) THz direct detectors operating at low THz frequency (e.g. 300 GHz), as well as at higher THz frequencies (e.g. 800 GHz – 1 THz). In addition, we investigated the implementation issues that limit the power coupling efficiency with the integrated antenna, as well as the antenna-detector impedance-matching condition. The implemented antenna-coupled FET detector structures aim to improve the detection behavior in terms of responsivity and noise equivalent power (NEP) for CMOS based imaging applications. Since the detected THz signals by using this approach are extremely weak with limited bandwidth, the next section of this work presents a pixel-level readout chain containing a cascade of a pre-amplification and noise reduction stage based on a parametric chopper amplifier and a direct analog-to-digital conversion by means of an incremental Sigma-Delta converter. The readout circuit aims to perform a lock-in operation with modulated sources. The in-pixel readout chain provides simultaneous signal integration and noise filtering for the multi-pixel FET detector arrays and hence achieving similar sensitivity by the external lock-in amplifier. Next, based on the experimental THz characterization and measurement results of a single pixel (antenna-coupled FET detector + readout circuit), the design and implementation of a multispectral imager containing 10 x 10 THz focal plane array (FPA) as well as 50 x 50 (3T-APS) visible pixels is presented. Moreover, the readout circuit for the visible pixel is realized as a column-level correlated double sampler. All of the designed chips have been implemented and fabricated in 0.15-µm standard CMOS technology. The physical implementation, fabrication and electrical testing preparation are discussed.
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13

Atrash, Amer Hani. "Data Bus Deskewing Systems in Digital CMOS Technology." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4969.

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This dissertation presents a study of signal deskewing systems in standard CMOS technologies. The objective of this work is to understand the limitations of deskewing systems as they are applied to modern systems and present new architectures to overcome past limitations. Traditional methods for signal deskewing are explored and the general limitations of these methods are identified. Several new architectures are proposed to address the limitations of previous techniques. The systems will be investigated with regard to minimum resolution, programming time, delay, maximum data rate, full scale range, and duty cycle distortion. Several other effects that are critical to the operation of deskewing systems will also be investigated. These effects include overshoot caused by parasitic package inductance, the impact of capacitive terminations, and the effect of mutual inductance between traces. To fulfill the requirements of this study, two deskewing systems are implemented in a 0.25um process. An open-loop system for deskewing wide data busses and a closed-loop system for deskewing a differential pair of lines are both fabricated. Both systems are found to meet the expected performance metrics, providing validation of the proposed techniques. Use of the proposed architectures allows the limitations of previous methods to be overcome. The remaining work is validated through either analytical techniques, simulations, or both where appropriate.
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Eilertsen, Bård Egil. "Current-Mode SAR-ADC In 180nm CMOS Technology." Thesis, Norges teknisk-naturvitenskapelige universitet, Institutt for elektronikk og telekommunikasjon, 2012. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-18820.

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This thesis presents a fully differential 9-bit current-mode successive approximation (SAR) ADC. The circuit is designed in 0.18 um technology with 1.8 V supply voltage and has a current draw on 472 uA. The ADC has a sampling frequency on 50 MHz and has a maximum ENOB on 8.42 bit. Because of non-linearity will ENOB be input frequency dependent and degrade to 6.87 bit.The design is based on conventional current-mode SAR ADC operation, but with a new comparator design and time interleaving. Time interleaving is used to increase the sampling frequency 10 times.The circuit needs a high degree of matching to work properly. Sub-threshold operation in several current sources gives a high degree of uncertainty in the current value. Thus several calibration circuits are presented, but are not implemented.
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Bespalko, Ryan Douglas. "Transimpedance amplifier design using 0.18 um CMOS technology." Thesis, Kingston, Ont. : [s.n.], 2007. http://hdl.handle.net/1974/452.

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Ramirez, Ortiz Rolando Carleton University Dissertation Engineering Electrical. "Technology mapping algorithms for CMOS dynamic logic circuits." Ottawa, 1992.

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17

Basset, Christophe Jean-Michel Perona Pietro Perona Pietro. "CMOS imaging technology with embedded early image processing /." Diss., Pasadena, Calif. : California Institute of Technology, 2007. http://resolver.caltech.edu/CaltechETD:etd-04262007-131214.

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18

Csutak, Sebastian Marius. "Optical receivers and photodetectors in 130nm CMOS technology." Access restricted to users with UT Austin EID Full text (PDF) from UMI/Dissertation Abstracts International, 2001. http://wwwlib.umi.com/cr/utexas/fullcit?p3036588.

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19

Fritzin, Jonas. "CMOS RF Power Amplifiers for Wireless Communications." Doctoral thesis, Linköpings universitet, Elektroniska komponenter, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-71852.

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The wireless market has experienced a remarkable development and growth since the introduction of the first modern mobile phone systems, with a steady increase in the number of subscribers, new application areas, and higher data rates. As mobile phones and wireless connectivity have become consumer mass markets, the prime goal of the IC manufacturers is to provide low-cost solutions. The power amplifier (PA) is a key building block in all RF transmitters. To lower the costs and allow full integration of a complete radio System-on-Chip (SoC), it is desirable to integrate the entire transceiver and the PA in a single CMOS chip. While digital circuits benefit from the technology scaling, it is becoming harder to meet the stringent requirements on linearity, output power, bandwidth, and efficiency at lower supply voltages in traditional PA architectures. This has recently triggered extensive studies to investigate the impact of different efficiency enhancement and linearization techniques, like polar modulation and outphasing, in nanometer CMOS technologies. This thesis addresses the potential of integrating linear and power-efficient PAs in nanometer CMOS technologies at GHz frequencies. In total eight amplifiers have been designed - two linear Class-A PAs, two switched Class-E PAs, and four Class-D PAs linearized in outphasing configurations. Based on the outphasing PAs, amplifier models and predistorters have been developed and evaluated for uplink (terminal) and downlink (base station) signals. The two linear Class-A PAs with LC-based and transformer-based input and interstage matching networks were designed in a 65nm CMOS technology for 2.4GHz 802.11n WLAN. For a 72.2Mbit/s 64-QAM 802.11n OFDM signal with PAPR of 9.1dB, both PAs fulfilled the toughest EVM requirement in the standard at average output power levels of +9.4dBm and +11.6dBm, respectively. The two PAs were among the first PAs implemented in a 65nm CMOS technology. The two Class-E PAs, intended for DECT and Bluetooth, were designed in 130nm CMOS and operated at low ‘digital’ supply voltages. The PAs delivered +26.4 and +22.7dBm at 1.5V and 1.0V supply voltages with PAE of 30% and 36%, respectively. The Bluetooth PA was based on thin oxide devices and the performance degradation over time for a high level of oxide stress was evaluated. The four Class-D outphasing PAs were designed in 65nm, 90nm, and 130nm CMOS technologies. The first outphasing design was based on a Class-D stage utilizing a cascode configuration, driven by an AC-coupled low-voltage driver, to allow a 5.5V supply voltage in a 65nm CMOS technology without excessive device voltage stress. Two on-chip transformers combined the outputs of four Class-D stages. At 1.95GHz the PA delivered +29.7dBm with a PAE of 26.6%. The 3dB bandwidth was  1.6GHz, representing state-of-the-art bandwidth for CMOS Class-D RF PAs. After one week of continuous operation, no performance degradation was noticed. The second design was based on the same Class-D stage, but combined eight amplifier stages by four on-chip transformers in 130nm CMOS to achieve a state-of-the-art output power of +32dBm for CMOS Class-D RF PAs. Both designs met the ACLR and modulation requirements without predistortion when amplifying uplink WCDMA and 20MHz LTE signals. The third outphasing design was based on two low-power Class-D stages in 90nm CMOS featuring a harmonic suppression technique, cancelling the third harmonic in the output spectrum which also improves drain efficiency. The proposed Class-D stage creates a voltage level of VDD/2 from a single supply voltage to shape the drain voltage, uses only digital circuits and eliminates the short-circuit current present in inverter-based Class-D stages. A single Class-D stage delivered +5.1dBm at 1.2V supply voltage with a drain efficiency and PAE of 73% and 59%, respectively. Two Class-D stages were connected to a PCB transformer to create an outphasing amplifier, which was linear enough to amplify EDGE and WCDMA signals without the need for predistortion. The fourth outphasing design was based on two Class-D stages  connected to an on-chip transformer with peak power of +10dBm. It was used in the development of a behavioral model structure and model-based phase-only predistortion method suitable for outphasing amplifiers to compensate for both amplitude and phase mismatches. In measurements for EDGE and WCDMA signals, the predistorter improved the margin to the limits of the spectral mask and the ACLR by more than 12dB. Based on a similar approach, an amplifier model and predistortion method were developed and evaluated for the +32dBm Class-D PA design using a downlink WCDMA signal, where the ACLR was improved by 13.5dB. A least-squares phase predistortion method was developed and evaluated for the +30dBm Class-D PA design using WCDMA and LTE uplink signals, where the ACLR was improved by approximately 10dB.
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Hafizović, Sadik. "Neural interface and atomic-force microscope in CMOS technology /." Zürich : Physical Electronics Laboratory, ETH Zürich, 2006. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=16806.

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Tang, Yi. "Digitally-assisted sigma-delta ADCs for scaled CMOS technology /." Thesis, Connect to this title online; UW restricted, 2007. http://hdl.handle.net/1773/5958.

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Chen, Tingsu. "CMOS High Frequency Circuits for Spin Torque Oscillator Technology." Licentiate thesis, KTH, Integrerade komponenter och kretsar, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-139588.

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Spin torque oscillator (STO) technology has a unique blend of features, including but not limited to octave tunability, GHz operating frequency, and nanoscaled size, which makes it highly suitable for microwave and radar applications. This thesis studies the fundamentals of STOs, utilizes the state-of-art STO's advantages, and proposes two STO-based microwave systems targeting its microwave applications and measurement setup, respectively. First, based on an investigation of possible STO applications, the magnetic tunnel junction (MTJ) STO shows a great suitability for microwave oscillator in multi-standard multi-band radios. Yet, it also imposes a large challenge due to its low output power, which limits it from being used as a microwave oscillator. In this regard, different power enhancement approaches are investigated to achieve an MTJ STO-based microwave oscillator. The only possible approach is to use a dedicated CMOS wideband amplifier to boost the output power of the MTJ STO. The dedicated wideband amplifier, containing a novel Balun-LNA, an amplification stage and an output buffer, is proposed, analyzed, implemented, measured and used to achieve the MTJ STO-based microwave oscillator. The proposed amplifier core consumes 25.44 mW from a 1.2 V power supply and occupies an area of 0.16 mm2 in a 65 nm CMOS process. The measurement results show a S21 of 35 dB, maximum NF of 5 dB, bandwidth of 2 GHz - 7 GHz. This performance, as well as the measurement results of the proposed MTJ STO-based microwave oscillator, show that this microwave oscillator has a highly-tunable range and is able to drive a PLL. The second aspect of this thesis, firstly identifies the major difficulties in measuring the giant magnetoresistance (GMR) STO, and hence studying its dynamic properties. Thereafter, the system architecture of a reliable GMR STO measurement setup, which integrates the GMR STO with a dedicated CMOS high frequency IC to overcome these difficulties in precise characterization of GMR STOs, is proposed. An analysis of integration methods is given and the integration method based on wire bonding is evaluated and employed, as a first integration attempt of STO and CMOS technologies. Moreover, a dedicated high frequency CMOS IC, which is composed of a dedicated on-chip bias-tee, ESD diodes, input and output networks, and an amplification stage for amplifying the weak signal generated by the GMR STO, is proposed, analyzed, developed, implemented and measured. The proposed dedicated high frequency circuits for GMR STO consumes 14.3 mW from a 1.2 V power supply and takes a total area of 0.329 mm2 in a 65 nm CMOS process. The proposed on-chip bias-tee presents a maximum measured S12 of -20 dB and a current handling of about 25 mA. Additionally, the proposed dedicated IC gives a measured gain of 13 dB with a bandwidth of 12.5 GHz - 14.5 GHz. The first attempt to measure the (GMR STO+IC) pair presents no RF signal at the output. The possible cause and other identified issues are given.<br><p>QC 20140114</p>
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Huang, Qin. "Devices and technology for CMOS compatible power integrated circuits." Thesis, University of Cambridge, 1992. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.240973.

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Pathapati, Srinivasa Rao. "All-Digital ADC Design in 65 nm CMOS Technology." Thesis, Linköpings universitet, Elektroniksystem, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-108578.

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The design of analog and complex mixed-signal circuits in a deep submicron CMOS process technology is a big challenge. This makes it desirable to shift data converter design towards the digital domain. The advantage of using a fully digital ADC design rather than a traditional analog ADC design is that the circuit is defined by an HDL description and automatically synthesized by tools. It offers low power consumption, low silicon area and a fully optimized gate-level circuit that reduces the design costs, etc. The functioning of an all-digital ADC is based on the time domain signal processing approach, which brings a high time resolution obtained by the use of a nanometer CMOS process. An all-digital ADC design is implemented by using a combination of the digital Voltage-Controlled Oscillator (VCO) and a Time-to-Digital Converter (TDC). The VCO converts the amplitude-domain analog signal to a phase-domain time-based signal. In addition, the VCO works as a time based quantizer. The time-based signal from the VCO output is then processed by the TDC quantizer in order to generate the digital code sequences. The fully digital VCO-based ADC has the advantage of superior time resolution. Moreover, the VCO-based ADC offers a first order noise shaping property of its quantization noise. This thesis presents the implementation of a VCO-based ADC in STM 65 nm CMOS process technology using digital tools such as ModelSim simulator, Synopsys Design Compiler and Cadence SOC Encounter. The circuit level simulations have been done in Cadence Virtuoso ADE. A multi-phase VCO and multi-bit quantization architecture has been chosen for this 8-bit ADC. The power consumption of the ADC is approximately 630 μW at 1.0 V power supply and the figure of merit is around 410 fJ per conversion step.
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Moral, Cejudo Alberto Jose del. "Integration of vertical Single Electron Transistor into CMOS technology." Doctoral thesis, Universitat Autònoma de Barcelona, 2021. http://hdl.handle.net/10803/673762.

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Aquesta tesi presenta les investigacions realitzades cap a la integració de transistors verticals d’un sol electró (SET) en tecnologia metall-òxid-semiconductor complementari (CMOS). Dues de les principals motivacions de la indústria de semiconductors són la miniaturització de dispositius i la reducció del consum d’energia. En els nodes més avançats, les arquitectures tridimensionals han guanyat una importància significativa per tal d’augmentar la densitat d’integració, sent els dispositius disposats verticalment els candidats més adequats per a les generacions més recents. D’altra banda, els dispositius d’un sol electró són exemples de circuits de baix consum energètic. En aquest treball, s’aborda la fabricació d’un SET basat en un nanofil vertical i la seva co-integració amb tecnologia CMOS. El punt de partida és un nanopilar de Si/SiO2/Si amb nanopunts de Si a la capa intermèdia de SiO2, que actuen com a punt quàntic del sistema. Els elèctrodes de porta i drenador es situen al voltant de l’òxid intermedi i en contacte amb el cap del pilar, respectivament. La integritat del pilar i el contacte dels seus elèctrodes es validen mitjançant caracterització estructural. Tot i que la integració SET en producció a gran escala és encara un repte, la seva combinació amb tecnologia CMOS es beneficia de la maduresa tecnològica del processament de circuits integrats, superant els inconvenients intrínsecs del SET com el soroll de fons o la inestabilitat del dispositiu. Aquest treball també presenta la fabricació monolítica i compatible amb CMOS d’un transistor planar convencional co-integrat amb un SET vertical. La fabricació del procés s’adapta per complir les restriccions imposades pel SET prefabricat, com ara un pressupost tèrmic reduït, capes de protecció i dopatge modificat. Es demostra la fabricació monolítica de SET vertical i transistors planars convencionals; es preserva la integritat del pilar i els transistors fabricats funcionen en condicions òptimes per a la compatibilitat SET.<br>Esta tesis presenta las investigaciones realizadas hacia la integración de transistores verticales de un solo electrón (SET) en tecnología metal-óxido-semiconductor complementario (CMOS). Dos de las principales motivaciones de la industria de semiconductores son la miniaturización de dispositivos y la reducción de consumo de energía. En los nodos más avanzados, las arquitecturas tridimensionales han ganado una importancia significativa para aumentar la densidad de integración, siendo los dispositivos dispuestos verticalmente los candidatos más adecuados para las generaciones más recientes. Por otro lado, los dispositivos de un solo electrón son ejemplos de circuitos de bajo consumo energético. En este trabajo, se aborda la fabricación de un SET basado en un nanohilo vertical y su co-integración con tecnología CMOS. El punto de partida es un nanopilar de Si/SiO/Si con nanopuntos de Si en la capa intermedia de SiO2, que actúan como puntos cuánticos del sistema. Los electrodos de puerta y drenador se sitúan alrededor del óxido intermedio y en contacto con la parte superior del pilar, respectivamente. La integridad del pilar y el contacto de sus electrodos se validan mediante caracterización estructural. Aunque la integración SET en producción a gran escala es todavía un reto, su combinación con tecnología CMOS se beneficia de la madurez tecnológica del procesamiento de circuitos integrados, superando al mismo tiempo los inconvenientes intrínsecos del SET como ruido de fondo o la inestabilidad del dispositivo. Este trabajo también presenta la fabricación monolítica y compatible con CMOS de un transistor planar convencional co-integrado con un SET vertical. La fabricación del proceso se adapta para cumplir las restricciones impuestas por el SET prefabricado, como presupuesto térmico reducido, capas de protección o dopaje modificado. Se demuestra la fabricación monolítica de SET vertical y transistores planares convencionales; se preserva la integridad del pilar y los transistores fabricados funcionan en condiciones óptimas para la compatibilidad SET.<br>This thesis presents the investigations performed towards the integration of Single Electron Transistor (SET) into Complementary Metal-Oxide-Semiconductor (CMOS) technologies. Two of the main drives in semiconductor industry are device miniaturization and power consumption reduction. In the most advanced nodes, three-dimensional architectures have gained significant importance to increase the integration density, being vertically arranged devices the most suitable candidates for the ultimate generations. On the other hand, single electron devices are examples of ultra-low power consumption circuits. In this work, the fabrication of a SET based on a vertical nanowire and its co-integration with CMOS technology is addressed. The starting point is a Si/SiO2/Si nanopillar with Si nanodots in the intermediate SiO2 layer, acting as quantum dot of the system. The subsequent gate and drain electrodes are placed all-around the embedded oxide and on contact with the pillar cap, respectively. Pillar integrity and its electrodes contacting are validated by structural characterization. While SET integration in large-scale production is still challenging, its combination with CMOS technology benefits from the technological maturity of integrated circuits processing, overtaking SET intrinsic drawbacks as background noise or device instability. This work also reports the CMOS compatible and monolithic fabrication of a conventional planar transistor co-integrated with a vertical SET. The process fabrication is adapted to fulfil the restrictions imposed by the pre-fabricated SET, such as reduced thermal budget, protective layers and modified doping. The monolithic fabrication of vertical SET and planar transistors is demonstrated; the pillar integrity is preserved, and the fabricated transistors operate at optimum conditions for SET compatibility.<br>Universitat Autònoma de Barcelona. Programa de Doctorat en Enginyeria Electrònica i de Telecomunicació
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Zarabadi, Seyed Ramezan. "Design of analog VLSI circuits in BICMOS/CMOS technology /." The Ohio State University, 1992. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487777170407338.

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Kommareddy, Jeevani. "10-bit C2C DAC Design in 65nm CMOS Technology." Wright State University / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=wright1565538915029852.

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Al-Attar, Talal. "A 77GHz monolithic IMPATT transmitter in standard CMOS technology /." May be available electronically:, 2008. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.

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29

Sengupta, Susanta. "Technology-independent CMOS op amp in minimum channel length." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-07092004-101204/unrestricted/sengupta%5Fsusanta%5F200407%5Fphd.pdf.

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Thesis (Ph. D.)--School of Electrical and Computer Engineering, Georgia Institute of Technology, 2005. Directed by Phillip Allen.<br>Morley, Thomas, Committee Member ; Leach, Marshall, Committee Member ; Ayazi, Farrokh, Committee Member ; Rincon-Mora, Gabriel, Committee Member ; Allen, Phillip, Committee Chair. Includes bibliographical references.
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Tenten, Wilfried. "Improved analog to digital converter circuits using CMOS technology." Thesis, University of Bath, 1990. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.329619.

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EL, RACHINI ALI. "Redundant analog to digital conversion architectures in CMOS technology." Doctoral thesis, Università degli Studi di Cagliari, 2015. http://hdl.handle.net/11584/266860.

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The operation of modern electronic devices in different fields as communications, signal processing, and sensor interface is critically affected with robust, high performance and scalable Analog-to-Digital Converter (ADCs), that can be considered as one of the main blocks in many systems, since they are mandatory to make the link between the analog outside world and the evermore-ubiquitous digital computer world. The design of these ADCs come distinct tradeoffs between speed, power, resolution, and die area embodied within many data conversion architectural variations. The flash ADC structure are often the base structure for high-speed operation and simple architecture analog-to-digital converters (ADCs). As the input signal is applied to (2
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Dhillon, Gurbhej Singh. "TUNABLE TIME DELAY ELEMENTS IN CMOS 90nm TECHNOLOGY FOR NOVEL VCO IMPLEMENTATION." The Ohio State University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=osu1269608522.

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33

Chen, Tingsu. "Wideband Amplifier Design for STO Technology." Thesis, KTH, Integrerade komponenter och kretsar, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-78198.

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Spin Torque Oscillator (STO) is a promising technology for microwave and radar applications due to its large tunability, miniature size, high operation frequency, high integration level, etc. However, the technology comes also with issues and challenges,such as low output power and spectrum impurity. For instance, in order to apply the STO technology into communication systems, an amplifier is required to compensate the STO’s low output power.     This thesis presents an amplifier for promising Magnetic Tunnel Junction (MTJ) STO devices. The motional resistance of different MTJ STO devices varies from several Ohms to hundreds Ohms, which makes the design challenging. This thesis focuses first on extracting the amplifier requirements using the state-of-the-art MTJ STO devices. The operation frequency of MTJ STO is in the range of 4-8GHzwith a -40~-60 dBm output power. Therefore, a wideband amplifier with 45-65 dB gain is required. Then based on the amplifier requirements, an amplifier topology is proposed, which is composed of two types of input balun-LNA stages depending onthe motional resistance of the STO, a broadband limiting amplifier and an outputbuffer. CG-CS architecture is suitable for the input balun-LNA in the small motional resistance case and cascoded-CS architecture is suitable for the large motional resistance case. The limiting amplifier and the output buffer are the common circuits shared by two cases via switches.     The wideband amplifier for STO is implemented using a 65nm CMOS process with 1.2 V supply and it exhibits 52.36 dB gain with 1.34-11.8 GHz bandwidth insmall motional resistance case and 59.29 dB gain with 1.171-8.178 GHz bandwidth in large motional resistance case. The simulation results show that the amplifier has very low power consumption and meets the linearity and noise performance requirements.
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Fritzin, Jonas. "Power Amplifier Circuits in CMOS Technologies." Licentiate thesis, Linköping : Department of Electrical Engineering, Linköpings universitet, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-21030.

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Arreguit, Xavier. "Compatible lateral bipolar transistors in CMOS technology : model and applications /." [S.l.] : [s.n.], 1989. http://library.epfl.ch/theses/?nr=817.

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36

Ross, Kyle Gene. "Distributed amplifier circuit design using a commercial CMOS process technology." Thesis, Montana State University, 2006. http://etd.lib.montana.edu/etd/2006/ross/RossK0806.pdf.

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Jakonis, Darius. "Direct RF sampling receivers for wireless systems in CMOS technology /." Linköping : Univ, 2004. http://www.bibl.liu.se/liupubl/disp/disp2004/tek881s.pdf.

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Haider, Daniyal. "On-Chip Phase Measurement Design Study in 65nm CMOS Technology." Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-120912.

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Jitter is generally defined as a time deviation of the clock waveform from its desired position. The deviation which occurs can be on the leading or lagging side and it can be bounded (deterministic) or unbounded (random). Jitter is a critical specification in the digital system design. There are various techniques to measure the jitter. The straightforward approach is based on spectrum analyzer or oscilloscope measurements. In this thesis an on-chip jitter measurement technique is investigated and the respective circuit is designed using 65 nm CMOS technology. The work presents the high level model and transistor level model, both implemented using Cadence software. Based on the Vernier concept the circuit is composed of an edge detector, two oscillators, and a phase detector followed by a binary counter, which provides the measurement result. The designed circuit attains resolution of 10ps and can operate in the range of 100 - 500 MHz Compared to other measurement techniques this design features low power consumption and low chip area overhead that is essential for built-in self-test (BIST) applications.
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Park, Min Ph D. Massachusetts Institute of Technology. "Time-based circuits for communication systems in advanced CMOS technology." Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/54229.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Cataloged from student submitted PDF version of thesis.<br>Includes bibliographical references (p. 145-151).<br>As device size scales down, there have been challenges to design conventional analog circuits, such as low voltage headroom and the low intrinsic gain of a device. Although ever-decreasing device channel length in CMOS technology has mainly negative effects on analog circuits, it increases device speed and reduces the power consumption of digital circuits. As a result, time-based signal processing has been attracting attention because time-based circuits take advantage of high speed and low power devices to deal with analog information in the time domain. In this thesis, we focus on a ring oscillator as a core time-based circuit for communication systems. Ring oscillators are employed in analog-to-time conversion or time-to-digital conversion. In this work, we present A/D converters and an RF modulator based on ring oscillators in deep sub-micron CMOS processes. We introduce a VCO-based [sigma][delta] A/D converter utilizing a voltage-controlled ring oscillator (ring VCO) as a continuous-time integrator. We propose to replace conventional integrators designed with analog circuits in a [sigma][delta] modulator with a ring VCO and a phase detector, thereby implementing an A/D converter without traditional analog circuits. We also propose a single-slope A/D converter using time-to-digital conversion. By combining a few analog circuits and a ring oscillator based Time-to-Digital Converter (TDC), we achieve highly digital A/D conversion. Finally, we demonstrate a VCO-based RF modulator. The proposed RF modulator generates an RF signal by simply switching transistors. As opposed to an RFDAC approach, the proposed RF modulator is not limited by quantization noise because it employs multiphase PWM signals. A VCO-based OP amp is also introduced as an alternative method of designing an OP amp in deep sub-micron CMOS. The proposed VCO-based OP amp is utilized to generate the multiphase PWM signals in the RF modulator. This thesis also presents the fundamental limitations of a ring oscillator as a timebased circuit. Although the idea of time-based signal processing employing a ring oscillator has its own limitations such as non-linear tuning characteristics and phase noise, the basic idea is worth investigating to solve the serious problems of analog circuits for future CMOS technology.<br>by Min Park.<br>Ph.D.
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Li, Yifan. "Developing CMOS compatible electro wetting-on-dielectric (EWOD) microfluidic technology." Thesis, University of Edinburgh, 2007. http://hdl.handle.net/1842/11052.

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Richardson, Justin Andrew. "Time resolved single photon imaging in nanometer scale CMOS technology." Thesis, University of Edinburgh, 2010. http://hdl.handle.net/1842/7588.

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Time resolved imaging is concerned with the measurement of photon arrival time. It has a wealth of emerging applications including biomedical uses such as fluorescence lifetime microscopy and positron emission tomography, as well as laser ranging and imaging in three dimensions. The impact of time resolved imaging on human life is significant: it can be used to identify cancerous cells in-vivo, how well new drugs may perform, or to guide a robot around a factory or hospital. Two essential building blocks of a time resolved imaging system are a photon detector capable of sensing single photons, and fast time resolvers that can measure the time of flight of light to picosecond resolution. In order to address these emerging applications, miniaturised, single-chip, integrated arrays of photon detectors and time resolvers must be developed with state of the art performance and low cost. The goal of this research is therefore the design, layout and verification of arrays of low noise Single Photon Avalanche Diodes (SPADs) together with high resolution Time-Digital Converters (TDCs) using an advanced silicon fabrication process. The research reported in this Thesis was carried out as part of the E.U. funded Megaframe FP6 Project. A 32x32 pixel, one million frames per second, time correlated imaging device has been designed, simulated and fabricated using a 130nm CMOS Imaging process from ST Microelectronics. The imager array has been implemented together with required support cells in order to transmit data off chip at high speed as well as providing a means of device control, test and calibration. The fabricated imaging device successfully demonstrates the research objectives. The Thesis presents details of design, simulation and characterisation results of the elements of the Megaframe device which were the author’s own work. Highlights of the results include the smallest and lowest noise SPAD devices yet published for this class of fabrication process and an imaging array capable of recording single photon arrivals every microsecond, with a minimum time resolution of fifty picoseconds and single bit linearity.
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Zaveri, Jainish K. "Asic Design of RF Energy Harvester Using 0.13UM CMOS Technology." DigitalCommons@CalPoly, 2018. https://digitalcommons.calpoly.edu/theses/1940.

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Recent advances in wireless sensor nodes, data acquisition devices, wearable and implantable medical devices have paved way for low power (sub 50uW) devices. These devices generally use small solid state or thin film batteries for power supply which need replacement or need to be removed for charging. RF energy harvesting technology can be used to charge these batteries without the need to remove the battery from the device, thus providing a sustainable power supply. In other cases, a battery can become unnecessary altogether. This enables us to deploy wireless network nodes in places where regular physical access to the nodes is difficult or cumbersome. This thesis proposes a design of an RF energy harvesting device able to charge commercially available thin film or solid-state batteries. The energy harvesting amplifier circuit is designed in Global Foundry 0.13um CMOS technology using Cadence integrated circuit design tools. This Application Specific Integrated Circuit (ASIC) is intended to have as small a footprint as possible so that it can be easily integrated with the above-mentioned devices. While a dedicated RF power source is a direct solution to provide sustainable power to the harvesting circuit, harvesting ambient RF power from TV and UHF cellular frequencies increases the possibilities of where the harvesting device can be placed. The biggest challenge for RF energy harvesting technology is the availability of adequate amount of RF power. This thesis also presents a survey of available RF power at various ultra-high frequencies in San Luis Obispo, CA.The idea is to determine the frequency band which can provide maximum RF power for harvesting and design a harvester for that frequency band.
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Farazian, Mohammad. "Fast hopping high-frequency carrier generation in digital CMOS technology." Diss., [La Jolla] : University of California, San Diego, 2009. http://wwwlib.umi.com/cr/ucsd/fullcit?p3356429.

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Thesis (Ph. D.)--University of California, San Diego, 2009.<br>Title from first page of PDF file (viewed June 16, 2009). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 127-131).
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Wang, Ron-wen, and 王榮文. "Microsensors By CMOS Technology." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/40890740454120796200.

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碩士<br>國立臺灣大學<br>電機工程學系<br>85<br>In this thesis, two integrated microsensors are designed and implemented. Thesis two sensors are CMOS infrared (IR) thermopile sensor and CMOS 2D vertical Hall sensor, both are integrated with on-chip readout circuits.The IR sensor is characterized by its ease of operation, requirement of no bias, wide spectral response and being fabricated by standard IC process.Though itis always not the optimal process for sensor, considerable sensor proformancestill can be obtained by using this industrial IC process and minimal post-process micromachining steps. On the other hand, the 2D vertical Hall sensor is outstanding for its ability to measure two-dimensional magnetic fieldsimultaneously, its ability to adjust sensitivity by maskless post-processmicromachining and active carrier confinement arrangement. The maximal absolutesensitivity value of the 2D Hall sensor is approximately 34 mV/T, which is higher than that reported by other researchers in 1996. Through empirical study of teh design, fabrication and measurement of these sensors, some experiences are gained. Therefore, in this thesis, some observations are also offered to hopefully help the interested researchers successfully implement their desired sensors.
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Laio, Chi-Hung, and 廖啟宏. "CMOS Image Sensor Technology (I)." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/45000030569043876291.

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碩士<br>國立交通大學<br>電子工程系<br>89<br>Recently, there has been a growing interest in CMOS image sensors. The major reason for this interest is the customer demand for miniaturized, low-power, and low-coast digital cameras. CMOS image sensors offer a great potential to integrate a significant amount of VLSI electronics on a single chip and reduce discrete components and packaging costs. It is now straightforward to envision a single-chip camera that has integrated timing and control electronics, sensor array, signal processing electronics, analog-to-digital converter (ADC) and full digital interface. Such a camera-on-a-chip will operate with standard logic supply voltages and consume power measured in the tens of milli-watts. The CMOS image sensor under studies includes three important parts: the first is pixel array, the second is on-chip signal processing and the third is programmable-gain amplifier. The pixel size is the key point for CMOS image sensors in high-resolution applications. In this thesis, the structure of three transistors is proposed. On-chip analog signal processing can be used to improve the performance and functionality of a CMOS image sensor. The general method is to use correlated-double-sampling (CDS) to suppress kTC noise from pixel reset, 1/f noise from the in-pixel source follower amplifier, and fixed-pattern-noise (FPN) originating from pixel-to-pixel variation in source-follower threshold voltage. The programmable gain settings are used to create color-filter-patterns. The CMOS image sensor uses the standard logic process offered by TSMC (0.35um) with applied voltage of 3.3v and operates at 25MHz, and the pixel array is 640*480.
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Liao, Yi-Hui, та 廖怡卉. "CMOS Image Sensor Technology(二)". Thesis, 2001. http://ndltd.ncl.edu.tw/handle/57469001736875199438.

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碩士<br>國立交通大學<br>電子工程系<br>89<br>The pixels of an image sensor are based on CCD (Charge-Coupled device) in current market for high-resolution applications. However, the disadvantages of CCD are large power consumption and incompatible in process with CMOS (Complementary metal-oxide semiconductor) elements for system on a chip to reduce cost. This thesis gives the architecture of a CMOS image sensor chip, including serial interface and its control, the image sensor operation and its control, and the image sensor registers. The serial interface includes synchronous interface and universal asynchronous transmitter and receiver. The main control blocks of the image sensor include the pixel and readout block control, the programmable gain amplifier block control, and the analog to digital converter control. The data of register sets is used to control the capture image operation of the image sensor and the image data processing of the image chip.
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Hung, Kei-Kang, and 洪根剛. "ESD ROBUSTNESS OF CMOS DEVICES IN SOI SALICIDE CMOS TECHNOLOGY." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/22766714966573020828.

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碩士<br>國立交通大學<br>電子工程系<br>89<br>There are two parts included in this thesis, which are related to the MOSFET devices and diode devices in the silicon-on-insulator (SOI) CMOS technology. In the first part, electrostatic discharge (ESD) robustness of CMOS MOSFETs with four different layout structures of H-gate, T-gate, floating-body, and sided-body, fabricated in a 0.15-µm partially-depleted SOI salicide CMOS process are studied and compared. Both of the positive polarity and the negative polarity ESD robustness of these fabricated MOSFETs are verified by ESD tester, and the second breakdown current (It2) of these MOSFETs are also measured by the transmission line pulse generator (TLPG). The dependences of ESD robustness on the layout parameters of these CMOS devices in this SOI CMOS process have been investigated to find the optimum layout rules for on-chip ESD protection design. The effectiveness of ESD clamp circuits designed with the gate-driven and substrate-triggered techniques are also compared in this SOI CMOS process. The ESD robustness raised by gate-driven technique performs more efficient than by substrate-triggered technique. In the second part, novel gated and non-gated diode structures for ESD protection are disclosed. The I-V characteristics of these new diodes under forward-biased and reverse-biased conditions are measured and compared to that of the lateral unidirectional bipolar type insulated gate transistor (Lubistor) diode. The experimental results show that the proposed new diode structures have an improved ESD robustness. A novel design on the power-rail ESD clamp circuit with the gate-triggered diodes in stacked configuration has shown a higher ESD robustness.
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48

Kao, Yu-Hsien, and 高侑賢. "Broadband Radar System in CMOS Technology." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/pkky8g.

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49

周美芬. "CMOS Technology Applied to Microwave Integrated Circuits." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/65059134547132856089.

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博士<br>國立交通大學<br>電子工程系所<br>94<br>The dissertation presents the radio frequency integrated circuit designs of direct conversion CMOS radio transceiver for wireless LAN and ultra wide-band applications based on integration considerations. The design considerations cover from standard specifications, circuit behaviors, schematic designs to package models as well as multi-process integration. Direct conversion architecture is proposed and analyzed for various wireless LAN and ultra wide-band applications, and some of the key building blocks are designed and implemented. First a 3-10-GHz low noise amplifier designed in 0.18-um CMOS technology for the receive path of ultra wide-band systems is presented. The proposed LNA employing stagger tuning technique consists of two stacked common-source stages with different resonance frequencies to achieve low power consumption and wide operating bandwidth. A wideband amplifier for the transmit path of ultra wide-band systems is also designed, implemented and measured, which employs current reuse distributed amplifier with PMOS and NMOS transistors reusing the same bias current to achieve the design goals of low power consumption and wide operating bandwidth. In addition, a highly integratable dual-band mixer equipped with a current combine dual-band load is designed and implemented in a 0.18-um CMOS technology for dual-band mixing and differential to single operation at both 2.45 and 5-GHz IEEE 802.11a/b/g wireless LAN frequency bands. The experimental results demonstrate the ability of functional integration for two frequency bands with a switchable dual-band load design. A plasma post treatment technique is developed to enhance the thermal stability of the low dielectrics in interconnects for process integration while the signal delay and cross coupling are improved at the same time. The integration example of CMOS voltage control oscillator with multi-level substrate is also presented to demonstrate the feasibility of system-on-a-package integration solution.
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50

Benson, Niels. "Organic CMOS technology by dielectric interface engineering." Phd thesis, 2009. https://tuprints.ulb.tu-darmstadt.de/1302/1/Dissertation.pdf.

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This work investigates the importance of electronic states at the dielectric / semiconductor interface for organic field effect transistor (OFET) charge carrier transport. It was determined, that balanced p- and n-type charge carrier transport in pentacene is possible, if an adequate gate dielectric is selected. It was further demonstrated, that the OFET charge carrier transport can be selectively influenced by either the introduction of charge carrier traps to the dielectric interface or the removal of such traps. By covering an electron trap afflicted silicon dioxide dielectric with a thin layer of oxidized Ca, which passivates and isolates available electron traps from the transistor channel, n-type transport in pentacene OFETs is achieved. In addition, it was demonstrated, that the introduction of electron traps into a Polymethylmethacrylat dielectric, using ultra violet radiation in ambient atmosphere, allows for the inversion of an otherwise unipolar n-type OFET to unipolar p-type. The possibility to realize OFETs of complementary polarity with an identical device cross section has allowed for the realization of an organic complementary metal oxide semiconductor inverter.
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