Relevant bibliographies by topics / CMOS Transistors

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'CMOS Transistors'

Author: Grafiati
Published: 4 June 2021
Last updated: 2 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'CMOS Transistors.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "CMOS Transistors"

1

Pan, James N. "Chromatic and Panchromatic Nonlinear Optoelectronic CMOSFETs for CMOS Image Sensors, Laser Multiplexing, Computing, and Communication." MRS Advances 5, no. 37-38 (2020): 1965–74. http://dx.doi.org/10.1557/adv.2020.273.

Full text
Abstract:
AbstractTraditionally, CMOS transistors are for low power, high speed, and high packing density applications. CMOS is also commonly used as power regulating devices, and light sensors (CCD or CMOS image sensors). In this paper, we would like to introduce Photonic CMOS as a light emitting device for optical computing, ASIC, power transistors, and ultra large scale integration (ULSI). A Photonic CMOS Field Effect Transistor is fabricated with a low-resistance laser or LED in the drain region, and multiple photon sensors in the channel / well regions. The MOSFET, laser, and photon sensors are fabricated as one integral transistor. With embedded nonlinear optical films, the Photonic CMOSFETs have the capability of detecting and generating focused laser beams of various frequencies to perform optical computing, signal modulation, polarization, and multiplexing for digital / analog processing and communication.
APA, Harvard, Vancouver, ISO, and other styles
2

Stegemann, S., J. Xiong, and W. Mathis. "Modellierung von Quanteneffekten in einem ladungsbasierten MOS-Transistor-Modell zur Simulation von nanoskalierten CMOS-Analogschaltungen." Advances in Radio Science 7 (May 19, 2009): 185–90. http://dx.doi.org/10.5194/ars-7-185-2009.

Full text
Abstract:
Abstract. Aufgrund der fortschreitenden Miniaturisierung der Bauelemente in CMOS-Schaltungen und den dadurch erreichten Strukturgrößen nehmen quantenmechanische Effekte zunehmenden Einfluss auf die Funktion von Transistoren und damit auf die gesamte Schaltung. Unter Einbeziehung der Energiequantisierung an der Si/SiO2-Grenzfläche wird untersucht, wie sich durch eine Modifikation der Beschreibung des Oberflächenpotenzials die Inversionsladung quantenmechanisch formulieren lässt. Im Hinblick auf den Entwurf und die Simulation von CMOS-Analogschaltungen wird dazu ein ladungsbasiertes MOS-Transistor-Modell zugrunde gelegt. Die sich daraus ergebenden Veränderungen für die Kapazitäten und die Inversionsladung werden dabei für die Modellierung des quasiballistischen Drain-Source-Stromes verwendet. Dazu wird innerhalb dieses Modells ein Streufaktor berechnet, mit dem nanoskalierte MOS-Transistoren mit einer Kanallänge von unter 20 nm simuliert werden können. Ausgehend von Parametern eines CMOS-Prozesses werden mit MATLAB die Einflüsse der quantenmechanischen Effekte bei der Skalierung des Transistors analysiert.
APA, Harvard, Vancouver, ISO, and other styles
3

Radamson, Henry H., Xiaobin He, Qingzhu Zhang, Jinbiao Liu, Hushan Cui, Jinjuan Xiang, Zhenzhen Kong, et al. "Miniaturization of CMOS." Micromachines 10, no. 5 (April 30, 2019): 293. http://dx.doi.org/10.3390/mi10050293.

Full text
Abstract:
When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.
APA, Harvard, Vancouver, ISO, and other styles
4

Angelov, George V., Dimitar N. Nikolov, and Marin H. Hristov. "Technology and Modeling of Nonclassical Transistor Devices." Journal of Electrical and Computer Engineering 2019 (November 3, 2019): 1–18. http://dx.doi.org/10.1155/2019/4792461.

Full text
Abstract:
This paper presents a comprehensive outlook for the current technology status and the prospective upcoming advancements. VLSI scaling trends and technology advancements in the context of sub-10-nm technologies are reviewed as well as the associated device modeling approaches and compact models of transistor structures are considered. As technology goes into the nanometer regime, semiconductor devices are confronting numerous short-channel effects. Bulk CMOS technology is developing and innovating to overcome these constraints by introduction of (i) new technologies and new materials and (ii) new transistor architectures. Technology boosters such as high-k/metal-gate technologies, ultra-thin-body SOI, Ge-on-insulator (GOI), AIII–BV semiconductors, and band-engineered transistor (SiGe or Strained Si-channel) with high-carrier-mobility channels are examined. Nonclassical device structures such as novel multiple-gate transistor structures including multiple-gate field-effect transistors, FD-SOI MOSFETs, CNTFETs, and SETs are examined as possible successors of conventional CMOS devices and FinFETs. Special attention is devoted to gate-all-around FETs and, respectively, nanowire and nanosheet FETs as forthcoming mainstream replacements of FinFET. In view of that, compact modeling of bulk CMOS transistors and multiple-gate transistors are considered as well as BSIM and PSP multiple-gate models, FD-SOI MOSFETs, CNTFET, and SET modeling are reviewed.
APA, Harvard, Vancouver, ISO, and other styles
5

SELLAMI, L., S. K. SINGH, R. W. NEWCOMB, A. RASMUSSEN, and M. E. ZAGHLOUL. "VLSI FLOATING RESISTORS FOR NEURAL TYPE CELL ARRAYS." Journal of Circuits, Systems and Computers 08, no. 05n06 (October 1998): 559–69. http://dx.doi.org/10.1142/s0218126698000353.

Full text
Abstract:
Two novel CMOS circuit designs implementing floating resistors are introduced, using the structure of a two-transistor CMOS bilateral linear resistor in the first configuration and two two-transistor CMOS bilateral linear resistors and cascode current mirrors in the second configuration. Linearity is achieved through nonlinearity cancellation via current mirrors over an applied range of ±5V. PSpice simulation results using parameters of MOSIS transistors are presented to verify the theory. These floating resistors can be used for coupling weights in VLSI neural-type cell arrays.
APA, Harvard, Vancouver, ISO, and other styles
6

Weng, Wu-Te, Yao-Jen Lee, Horng-Chih Lin, and Tiao-Yuan Huang. "Plasma-Induced Damage on the Reliability of Hf-Based High-k/Dual Metal-Gates Complementary Metal Oxide Semiconductor Technology." International Journal of Plasma Science and Engineering 2009 (December 14, 2009): 1–10. http://dx.doi.org/10.1155/2009/308949.

Full text
Abstract:
This study examines the effects of plasma-induced damage (PID) on Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates that thinning the gate dielectric reduces the impact of damage on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO2/poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for high-k/metal-gate CMOS technology.
APA, Harvard, Vancouver, ISO, and other styles
7

Jiang, Jin Tao, Li Fang Ye, and Jian Ping Hu. "Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration." Applied Mechanics and Materials 39 (November 2010): 73–78. http://dx.doi.org/10.4028/www.scientific.net/amm.39.73.

Full text
Abstract:
Leakage power reduction is extremely important in the design of nano-circuits. Gate leakage has become a significant component in currently used nanometer CMOS processes with gate oxide structure. The structure and operation of the PAL-2P (pass-transistor adiabatic logic with PMOS pull-up configuration) circuits that consist mostly of PMOS transistors are complementary to PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) ones that consist mostly of NMOS transistors. This paper investigates gate leakage reduction of the PAL-2P circuits in nanometer CMOS processes with gate oxide materials. An s27 benchmark circuit from the ISCAS89 sequential benchmark set is verified using the PAL-2P scheme. All circuits are simulated with HSPICE using the 65nm CMOS process with gate oxide materials. Based on the power dissipation models of PAL-2P adiabatic circuits, active leakage dissipations are estimated by testing total leakage dissipations using SPICE simulations. The PAL-2P circuits consume low static power compared with traditional PAL-2N ones.
APA, Harvard, Vancouver, ISO, and other styles
8

Lee, Sang-Hoon, Min-Jae Seo, Amos Amoako Boampong, Jae-Hyeok Cho, Kyeong Min Yu, and Min-Hoi Kim. "Solution-Processed Organic and Oxide Hybrid CMOS Inverter for Low Cost Electronic Circuits." Journal of Nanoscience and Nanotechnology 20, no. 7 (July 1, 2020): 4381–84. http://dx.doi.org/10.1166/jnn.2020.17600.

Full text
Abstract:
We demonstrated an organic and oxide hybrid CMOS inverter with the solution-processed semiconductor and source/drain electrodes. For the solution-processed n- and p-type semiconductor, InGaZnO solution and TIPS-pentacene/PαMS blend were spin-coated respectively while Silver ink and PEDOT:PSS solution were drop-casted with the help of the bank to serve as source/drain electrodes. The InGaZnO and the TIPS-pentacene transistors show typical n- and p-type transistor operations with low off-current. Based on the combination of the solution-processed n- and p-type transistors, full-swing characteristic curve with low static current of the hybrid CMOS were obtained.
APA, Harvard, Vancouver, ISO, and other styles
9

Ahmad, Nabihah, and Rezaul Hasan. "A 0.8 V 0.23 nW 1.5 ns Full-Swing Pass-Transistor XOR Gate in 130 nm CMOS." Active and Passive Electronic Components 2013 (2013): 1–6. http://dx.doi.org/10.1155/2013/148518.

Full text
Abstract:
A power efficient circuit topology is proposed to implement a low-voltage CMOS 2-input pass-transistor XOR gate. This design aims to minimize power dissipation and reduce transistor count while at the same time reducing the propagation delay. The XOR gate utilizes six transistors to achieve a compact circuit design and was fabricated using the 130 nm IBM CMOS process. The performance of the XOR circuit was validated against other XOR gate designs through simulations using the same 130 nm CMOS process. The area of the core circuit is only about 56 sq · µm with 1.5659 ns propagation delay and 0.2312 nW power dissipation at 0.8 V supply voltage. The proposed six-transistor implementation thus compares favorably with other existing XOR gate designs.
APA, Harvard, Vancouver, ISO, and other styles
10

Vidhyadharan, Abhay Sanjay, and Sanjay Vidhyadharan. "Improved hetero-junction TFET-based Schmitt trigger designs for ultra-low-voltage VLSI applications." World Journal of Engineering 18, no. 5 (March 26, 2021): 750–59. http://dx.doi.org/10.1108/wje-08-2020-0367.

Full text
Abstract:
Purpose Tunnel field effect transistors (TFETs) have significantly steeper sub-threshold slope (24–30 mv/decade), as compared with the conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), which have a sub-threshold slope of 60 mv/decade at room temperature. The steep sub-threshold slope of TFETs enables a much faster switching, making TFETs a better option than MOSFETs for low-voltage VLSI applications. The purpose of this paper is to present a novel hetero-junction TFET-based Schmitt triggers, which outperform the conventional complementary metal oxide semiconductor (CMOS) Schmitt triggers at low power supply voltage levels. Design/methodology/approach The conventional Schmitt trigger has been implemented with both MOSFETs and HTFETs for operation at a low-voltage level of 0.4 V and a target hysteresis width of 100 mV. Simulation results have indicated that the HTFET-based Schmitt trigger not only has significantly lower delays but also consumes lesser power as compared to the CMOS-based Schmitt trigger. The limitations of the conventional Schmitt trigger design have been analysed, and improved CMOS and CMOS–HTFET hybrid Schmitt trigger designs have been presented. Findings The conventional Schmitt trigger implemented with HTFETs has 99.9% lower propagation delay (29ps) and 41.2% lesser power requirement (4.7 nW) than the analogous CMOS Schmitt trigger, which has a delay of 36 ns and consumes 8 nW of power. An improved Schmitt trigger design has been proposed which has a transistor count of only six as compared to the eight transistors required in the conventional design. The proposed improved Schmitt trigger design, when implemented with only CMOS devices enable a reduction of power delay product (PDP) by 98.4% with respect to the CMOS conventional Schmitt trigger design. The proposed CMOS–HTFET hybrid Schmitt trigger further helps in decreasing the delay of the improved CMOS-only Schmitt trigger by 70% and PDP by 21%. Originality/value The unique advantage of very steep sub-threshold slope of HTFETs has been used to improve the performance of the conventional Schmitt trigger circuit. Novel CMOS-only and CMOS–HTFET hybrid improved Schmitt trigger designs have been proposed which requires lesser number of transistors (saving 70% chip area) for implementation and has significantly lower delays and power requirement than the conventional designs.
APA, Harvard, Vancouver, ISO, and other styles
More sources

Dissertations / Theses on the topic "CMOS Transistors"

1

Duncan, Martin Russell. "CMOS-compatible high-voltage transistors." Thesis, University of Edinburgh, 1994. http://hdl.handle.net/1842/12182.

Full text
Abstract:
Bipolar transistors are known to be the most suitable for high-voltage and power applications, due to their inherently greater current handling capability. In contrast, MOS technology is preferable for logic applications, due to its superior packing density. Therefore the 'ideal' solution to the smart power problem of integrating control elements on the same die as power switches is a marriage of the two different technologies. This results in a complex process that can only be cost effective in high volume applications. For ASIC applications and low volume product runs a less expensive compromise solution is needed. By analyzing both bipolar and MOS, low and high voltage devices, it was found that if more than one power transistor is needed on the circuit, and a single technology is to be used, then MOS power transistors are inherently easier to integrate into a low voltage process. In particular the lateral double-diffused transistor (LDMOS) with all terminal contacts on the surface is to be preferred. Analyzing a CMOS process, common processing steps were found for both the low and high-voltage devices, leading to a smart power solution that doesn't need many masking levels. By making small changes to an established n-well CMOS process, and developing a novel power transistor structure with a field oxidation separating the channel and drain, a 120 Volt n-channel power transistor could be realised within a conventional process with no additional processing steps. By adding one further masking layer, a complementary p-channel power transistor that supported -55 Volts could be fabricated. If these transistors were fabricated on a p- epitaxial layer on an n- substrate then by changing the p-channel power device structure, a breakdown voltage of -95 Volt could be achieved using only nine masking layers.
APA, Harvard, Vancouver, ISO, and other styles
2

Tachi, Kiichi. "Etude physique et technologique d'architectures de transistors MOS à nanofils." Phd thesis, Université de Grenoble, 2011. http://tel.archives-ouvertes.fr/tel-00721968.

Full text
Abstract:
Il a été démontré que la structure gate-all-around en nanofils de silicium peut radicalement supprimer les effets de canaux courts. De plus, l'introduction d'espaceurs internes entre ces nanofils peut permettre de contrôler la tension de seuil, à l'aide d'une deuxième grille de contrôle. Ces technologies permettent d'obtenir une consommation électrique extrêmement faible. Dans cette thèse, pour obtenir des opérations à haute vitesse (pour augmenter le courant de drain), la technique de réduction de la résistance source/drain sera débattue. Les propriétés de transport électronique des NWs empilées verticalement seront analysées en détail. De plus, des simulations numériques sont effectuées pour examiner les facultés de contrôle de leur tension de seuil utilisant des grilles sépares.
APA, Harvard, Vancouver, ISO, and other styles
3

Acosta, Sandra Massulini. "Projeto de amplificadores operacionais CMOS utilizando transistores compostos em "sea-of-transistors"." reponame:Repositório Institucional da UFSC, 1997. https://repositorio.ufsc.br/handle/123456789/111588.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Markov, Stanislav Nikolaev. "Gate leakage variability in nano-CMOS transistors." Thesis, University of Glasgow, 2009. http://theses.gla.ac.uk/771/.

Full text
Abstract:
Gate leakage variability in nano-scale CMOS devices is investigated through advanced modelling and simulations of planar, bulk-type MOSFETs. The motivation for the work stems from the two of the most challenging issues in front of the semiconductor industry - excessive leakage power, and device variability - both being brought about with the aggressive downscaling of device dimensions to the nanometer scale. The aim is to deliver a comprehensive tool for the assessment of gate leakage variability in realistic nano-scale CMOS transistors. We adopt a 3D drift-diffusion device simulation approach with density-gradient quantum corrections, as the most established framework for the study of device variability. The simulator is first extended to model the direct tunnelling of electrons through the gate dielectric, by means of an improved WKB approximation. A study of a 25 nm square gate n-type MOSFET demonstrates that combined effect of discrete random dopants and oxide thickness variation lead to starndard deviation of up to 50% (10%) of the mean gate leakage current in OFF(ON)-state of the transistor. There is also a 5 to 6 times increase of the magnitude of the gate current, compared to that simulated of a uniform device. A significant part of the research is dedicated to the analysis of the non-abrupt bandgap and permittivity transition at the Si/SiO2 interface. One dimensional simulation of a MOS inversion layer with a 1nm SiO2 insulator and realistic band-gap transition reveals a strong impact on subband quantisation (over 50mV reduction in the delta-valley splitting and over 20% redistribution of carriers from the delta-2 to the delta-4 valleys), and enhancement of capacitance (over 10%) and leakage (about 10 times), relative to simulations with an abrupt band-edge transition at the interface.
APA, Harvard, Vancouver, ISO, and other styles
5

Vega, Reinaldo A. "Schottky field effect transistors and Schottky CMOS circuitry /." Online version of thesis, 2006. http://hdl.handle.net/1850/5179.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Lund, Håvard. "IV and CV characterization of 90nm CMOS transistors." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2006. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-10079.

Full text
Abstract:

A 90nm CMOS technology has been characterized on the basis of IV and CV measurements. This was feasible by means of a state of the art probe station and measurement instrumentation, capable of measuring current and capacitance in the low fA and fF area respectively. From IV results it was found that the static power consumption is an increasing challenge as the technology is scaled down. The IV measurements also showed the impact from small-channel effects, which was not as prominent as expected. Investigation of literature has resulted in a methodology for accomplishing accurate CV measurements on thin-oxide transistors. By using extraction methods on the capacitance measured, key parameters have been obtained for the CMOS technology. Some of the extracted results suffer however from the choice of test setup.

APA, Harvard, Vancouver, ISO, and other styles
7

Santos, Filipe de Andrade Tabarani. "Projeto de amplificadores com realimentação em corrente utilizando tecnologia 0,35 µm CMOS." [s.n.], 2011. http://repositorio.unicamp.br/jspui/handle/REPOSIP/262023.

Full text
Abstract:
Orientador: Carlos Alberto dos Reis Filho
Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação
Made available in DSpace on 2018-08-19T10:35:49Z (GMT). No. of bitstreams: 1 Santos_FilipedeAndradeTabarani_M.pdf: 11362655 bytes, checksum: 2e42c97ddd2bc2cb397c41f31568dc37 (MD5) Previous issue date: 2011
Resumo: Este trabalho apresenta o estudo aprofundado e a confecção de amplificadores realimentados por corrente (CFA). São analisadas as principais características de um CFA e comparado com o amplificador realimentado por tensão (VOA). Buscou-se esclarecer as aplicações nas quais a primeira célula apresenta-se como melhor alternativa e como importante ferramenta a ser disponibiliza aos projetistas. Ao longo desta analise são frisadas as principais dificuldades na implementação da célula em tecnologia CMOS mencionando as soluções encontradas pela na literatura. Estas dificuldades impedem a confecção de CFAs CMOS comerciais. Um dos principais problemas da implementação de amplificadores realimentados por corrente em tecnologia CMOS e a baixa transcondutância dos transistores. A literatura propõe contornar esta deficiência da tecnologia utilizando células que obtêm alta transcondutância através do uso de realimentação interna [1]. Entretanto, a topologia proposta possui um severo compromisso entre transcondutância e banda de freqüência. O trabalho apresentado nesta dissertação deixa sua contribuição a literatura propondo dois métodos para amenizar este compromisso, que resultam no deslocamento da freqüência de -3dB, tornando-a significantemente maior que a original. No exemplo de projeto, aqui ilustrado, foi obtida banda 3,25 vezes a original,mantendo as características DC.O projeto de duas topologias, sendo uma baseada no primeiro CFA monolítico comercializado e a outra que utiliza transistores compostos, foi realizado visando a implementação monolítica em tecnologia 0,35 ?m CMOS da fabrica Austriamicrosystems. Os protótipos fabricados foram medidos e os resultados comparados com o esperado por simulação
Abstract: This work presents the study and design of current-feedback amplifiers (CFA).It is analyzed the main characteristics of a CFA as it compares to a typical voltage feedback amplifier (VOA). It was attempted to clarify in which applications the first mentioned cell excels at and why it can serve as an important tool for the designers. Throughout the analysis, the main difficulties regarding the implementation of the cell using CMOS technology are highlighted and the solutions proposed by the literature exposed. Those characteristics restrain the conception of CMOS commercials CFAs. One of the primary obstacles for the implementation of current-feedback amplifiers using CMOS technology is the low transconductance of the transistors. The literature proposes the use of cells with internal feedback in order to solve this issue [1].However, the proposed cell has a severe trade-off between transconductance and frequency bandwidth. This work provides its contribution to the literature by proposing two methods to loosen this trade-off. Using the proposed modification, it was obtained 3.25 times the original bandwidth while maintaining all of its native DC characteristics. The design of two topologies was carried out using monolithic Austriamicrosystems0.35?m CMOS technology; one based on the topology of the first commercialized monolithic CFA and the other using compound transistors. The produced prototypes were measured and the results compared with expected by simulation
Mestrado
Eletrônica, Microeletrônica e Optoeletrônica
Mestre em Engenharia Elétrica
APA, Harvard, Vancouver, ISO, and other styles
8

Wilson, David. "Characterisation of bipolar parasitic transistors for CMOS process control." Thesis, University of Edinburgh, 1992. http://hdl.handle.net/1842/11585.

Full text
Abstract:
In integrated circuit manufacture, in particular, quality assurance, QA, is increasing rapidly in importance and in this research methods are developed and assessed which will assist with this. A review of current IC manufacturing is presented and CMOS technology shown to be dominant with BiCMOS seen to be a growth area. The role of Statistical Process Control, SPC, and the end for QA is also reviewed. This thesis addresses the problem and has defined some new techniques for the process control of a standard CMOS process. The approach is a novel one employing the concept of parasitic bipolar transistor test structures as a process control tool for present day CMOS circuits and, even more importantly, for BiCMOS devices. Test chip design and manufacture for the project are presented and the techniques proposed include: a) characterisation of parasitic JFETs to provide well depth information electrically b) the use of parasitic lateral bipolar transistors to estimate the sideways diffusion component associated with MOS transistors fabricated in a CMOS process c) the use of parasitic bipolar test structures to evaluate CMOS process uniformity. They provide useful parameters for processcontrol and, in some cases, have even been demonstrated to be more sensitive to CMOS process non-uniformities than those extracted from MOS devices themselves. Also process control information for today'sCMOS processes and an insight into the control of future BiCMOS processes.
APA, Harvard, Vancouver, ISO, and other styles
9

Voisin, Benoit. "Contrôle d'électrons et de dopants uniques dans des transistors silicium." Thesis, Grenoble, 2013. http://www.theses.fr/2013GRENY067/document.

Full text
Abstract:
Les récents progrès de fabrication des transistors en silicium-sur-isolant concernent la réduction de leurs dimensions, qui atteignent désormais quelques dizaines de nanomètres, et l'amélioration des contacts. Cela permet l'étude des premiers électrons du canal à basse température. Ceux-ci sont confinés dans les coins du nanofil, où le champ électrique est le plus intense. La dégénérescence de vallée du silicium est alors levée, donnant lieu à un singulet comme état à deux électrons de plus basse énergie en champ magnétique nul. La proximité de contacts quasi-métalliques permet l'étude des interactions entre ces électrons confinés et les électrons de la bande de conduction des contacts à travers l'effet Kondo et le Fermi-edge singularity.D'autre part les dopants, ingrédients essentiels de la fabrication de ces transistors, offrent naturellement une levée de dégénérescence de vallée de par leur fort potentiel de confinement. En variant le champ électrique transverse, nous étudions l'influence de l'environnement complexe sur l'ionisation d'un dopant selon sa position dans le canal. Nous avons ensuite réalisé le premier transistor à atomes couplés, où le transport est contrôlé par l'alignement des niveaux de deux atomes en série, facilitant la spectroscopie: nous mesurons une séparation entre les deux premiers états d'un dopant de l'ordre de 10 meV, un ordre de grandeur plus grand que celle des premiers électrons de la bande de conduction. Cette séparation permet de manipuler les états électroniques dans le régime de la dizaine de gigahertz. Une expérience d'interférométrie à un électron entre deux dopants est réalisée, ouvrant la voie vers des manipulations cohérentes dans des systèmes à dopants uniques
Recent progress in Silicon-On-Insulator transistors fabrication have concerned a dimensions reduction, up to a few tens of nanometers, and an improvement of the leads. This allows to study the few electrons regime at low temperature. These latter are confined in the corners of the nanowire, where the electric field is maximized. This leads for the silicon valley degeneracy to be lifted, with a singlet for the two-electron ground state at zero magnetic field. We also investigate the interactions between these confined electrons and the electrons of the contacts conduction bands, with the Kondo effect and the Fermi-edge singularity.The dopants, essential ingredients of the transistors fabrication, naturally lift the valley degeneracy thanks to their deep confinement potential. First, by tuning the transverse electric field, we investigate the influence of the complex environment on a donor's ionization according to its position in the nanowire. We then realized the first Coupled-Atom Transistor, where the transport is controlled by the alignment of the ground states of two dopants placed in series. We could measure an energy splitting between the two first states of the order of 10 meV, one order of magnitude larger than that of the first electrons of the conduction band. This large separation allows to manipulate the electronic states in the ten's gigahertz regime. We induce one-electron interferences between the ground states of the two dopants, opening the way towards coherent electron manipulations in dopant-based devices
APA, Harvard, Vancouver, ISO, and other styles
10

Di, Gilio Thierry. "Etude de la fiabilité porteurs chauds et des performances des technologies CMOS 0. 13 µm-2nm." Aix-Marseille 1, 2006. http://theses.univ-amu.fr.lama.univ-amu.fr/2006AIX11024.pdf.

Full text
Abstract:
Ces travaux sont consacrés à l'étude de la dégradation des transistors MOSFETs de la génération 130nm-2nm, soumis aux injections de porteurs énergétiques générés par les champs électriques élevés. Les méthodes de vieillissement et de caractérisation sont adaptées pour cette technologie. Une étude comparative des mécanismes de dégradations mis en jeu est ensuite réalisée sur des technologies antérieures afin de mettre en évidence l'évolution de ces mécanismes. Ces résultats sont utilisés pour l'évaluation de la durée de vie des dispositifs dans leur fonctionnement normal. Nous adaptons ces techniques d'extrapolation aux modes de défaillances relevés
APA, Harvard, Vancouver, ISO, and other styles
More sources

Books on the topic "CMOS Transistors"

1

1960-, Li Harry W., Boyce David E. 1940-, and Institute of Electrical and Electronics Engineers, eds. CMOS circuit design, layout, and simulation. New Delhi: Prentice-Hall of India, 2004.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
2

CMOS: Circuit design, layout, and simulation. 3rd ed. Piscataway, NJ: IEEE Press, 2010.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
3

Institute of Electrical and Electronics Engineers., ed. CMOS circuit design, layout, and simulation. 2nd ed. New York: IEEE Press, 2005.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
4

1960-, Li Harry W., and Boyce David E. 1940-, eds. CMOS circuit design, layout, and simulation. New York: IEEE Press, 1997.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
5

Baker, R. Jacob. CMOS circuit design, layout, and simulation. New York: IEEE Press, 1998.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
6

Institute of Electrical and Electronics Engineers., ed. CMOS circuit design, layout, and simulation. 2nd ed. Piscataway, NJ: IEEE Press, 2008.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
7

Saijets, Jan. MOSFET RF characterization using bulk and SOI CMOS technologies. [Espoo, Finland]: VTT Technical Research Centre of Finland, 2007.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
8

Youssef, Ahmed A. Nanometer CMOS RFICs for mobile TV applications. Dordrecht: Springer, 2010.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
9

Ma, Vivian Wing Yan. Integration of complementary EDMOS transistors in a standard 0.35[mu]m CMOS technology for 40V applications. Ottawa: National Library of Canada, 2003.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
10

El-Khatib, Ziad. Distributed CMOS bidirectional amplifiers: Broadbanding and linearization techniques. New York: Springer, 2012.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
More sources

Book chapters on the topic "CMOS Transistors"

1

Bindal, Ahmet. "MOS Transistors and CMOS Circuits." In Electronics for Embedded Systems, 57–87. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-39439-8_3.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Mouis, M., and G. Ghibaudo. "Accurate Determination of Transport Parameters in Sub-65 nm MOS Transistors." In Nanoscale CMOS, 475–544. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2013. http://dx.doi.org/10.1002/9781118621523.ch14.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Ma, Yanjun, and Edwin Kan. "Bipolar Transistors in Logic CMOS Processes." In Non-logic Devices in Logic Processes, 125–32. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-48339-9_6.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Manku, Tajinder. "Microwave Noise Modeling of CMOS Transistors." In Analog Circuit Design, 247–65. Boston, MA: Springer US, 1999. http://dx.doi.org/10.1007/978-1-4757-3047-0_11.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Anis, Mohab, and Mohamed Elmasry. "MTCMOS Combinational Circuits Using Sleep Transistors." In Multi-Threshold CMOS Digital Circuits, 73–133. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-0391-0_4.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Melzer, Christian, and Heinz von Seggern. "Organic Field-Effect Transistors for CMOS Devices." In Organic Electronics, 189–212. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/12_2009_9.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Tigelaar, Howard. "Parasitic MOS and Bipolar Transistors in CMOS ICs." In How Transistor Area Shrank by 1 Million Fold, 67–72. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-40021-7_5.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Resta, Giovanni V., Pierre-Emmanuel Gaillardon, and Giovanni De Micheli. "Functionality-Enhanced Devices: From Transistors to Circuit-Level Opportunities." In Beyond-CMOS Technologies for Next Generation Computer Design, 21–42. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-90385-9_2.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Tigelaar, Howard. "CMOS Inverter Manufacturing Flow: Part 1 Wafer Start Through Transistors." In How Transistor Area Shrank by 1 Million Fold, 73–102. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-40021-7_6.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Lu, Xubing. "High-k Dielectrics in Ferroelectric Gate Field Effect Transistors for Nonvolatile Memory Applications." In High-k Gate Dielectrics for CMOS Technology, 471–99. Weinheim, Germany: Wiley-VCH Verlag GmbH & Co. KGaA, 2012. http://dx.doi.org/10.1002/9783527646340.ch15.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "CMOS Transistors"

1

(Jane) Li, Yuanjing, John Aguada, Jiafang Lu, Jessica Yang, Roy Ng, and Howard Lee Marks. "Capturing Defects in Flip-Chip CMOS Devices Using Backside EBAC Technique and SEM Microscopy." In ISTFA 2016. ASM International, 2016. http://dx.doi.org/10.31399/asm.cp.istfa2016p0118.

Full text
Abstract:
Abstract This paper presents backside physical failure analysis methods for capturing anomalies and defects in advanced flip-chip packaged, bulk silicon CMOS devices. Sample preparation involves chemically removing all the silicon, including the diffusions, to expose the source/drain contact silicide and the gate of the transistors from the backside. Scanning Electron Microscopy (SEM) is used to form high resolution secondary and/or backscattered electron images of the transistor structures on and beneath the exposed surface. If no visual defects/anomalies are found at the transistor level, the Electron Beam Absorbed Current (EBAC) technique is used to isolate short/open defects in the interconnect metallization layers by landing nano-probe(s) on a transistor’s source/drain silicide or on the gate. Using the combination of secondary and backscattered electron imaging and backside EBAC thus allows defects residing in either the transistors or the metal nets to be found. Case studies from 20 nm technology node graphics processing units (GPU) are presented to demonstrate the effectiveness of this approach.
APA, Harvard, Vancouver, ISO, and other styles
2

Kenji Natori and Takashi Kurusu. "Novel aspects of nanoscale transistors." In 2006 International Workshop on Nano CMOS (IWNC). IEEE, 2006. http://dx.doi.org/10.1109/iwnc.2006.4570997.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Cristoloveanu, Sorin. "Length, width and thickness effects in SOI transistors." In 2006 International Workshop on Nano CMOS (IWNC). IEEE, 2006. http://dx.doi.org/10.1109/iwnc.2006.4570998.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Mulder, Randal, Sam Subramanian, and Tony Chrastecky. "Atomic Force Probe Analysis of Nonvisible Defects in Sub-100nm CMOS Technologies." In ISTFA 2006. ASM International, 2006. http://dx.doi.org/10.31399/asm.cp.istfa2006p0503.

Full text
Abstract:
Abstract Traditional micro-probing and electrical characterization at the transistor level for sub-100nm technologies has become very difficult if not virtually impossible. Scanning probe microscopy technology specifically atomic force probing was developed in response to these issues with traditional micro-probing. The case studies presented in this paper demonstrate how atomic force probing was used to characterize failing sub-100nm transistors, identify possible failure mechanisms, and allow device/process engineers to make adjustments to the wafer fabrication process to correct the problem even though physical analysis with scanning election microscope/transmission electron microscope was not able to image and identify a failure mechanism. The probable causes for the transistor level failures are being identified through test methods, computer simulations, and electrical analysis by means of the atomic force probe after the failure has been sufficiently localized to a minimum number of transistors.
APA, Harvard, Vancouver, ISO, and other styles
5

Kim, Jong Eun, Jong Hak Lee, Jong Kyu Cho, Sang Hyun Ban, Chang Su Park, Nam Il Kim, Dae Woo Kim, et al. "Analysis of SRAM Function Failure Due to Unformed CoSi2 Using Nanoprober and Transmission Electron Microscopy." In ISTFA 2016. ASM International, 2016. http://dx.doi.org/10.31399/asm.cp.istfa2016p0137.

Full text
Abstract:
Abstract In this article, an analysis of a failure in the embedded SRAM in a CMOS Image Sensor is investigated. The failure was due to unformed CoSi2. Because unformed CoSi2 causes a varying degree of response, a nano-prober was used to find the abnormally operating transistors among a 1-bit SRAM cell consisting of six transistors(6T). After measuring and analyzing the current-voltage relationships between each transistor, the current magnitude of one pull-down transistor was found to be less than the expected range and particularly lower than that of a connected access transistor. To visualize the failure phenomenon and find the root cause of this, TEM analysis was conducted. Using the EELS (Electron Energy Loss Spectroscopy) elemental mapping, unformed CoSi2 was detected between the contact and substrate, where the contact corresponds to the VSS of the pull-down transistor. This caused an increase in the contact resistance, thus lowering the current magnitude of the abnormal transistor to a greater degree than expected.
APA, Harvard, Vancouver, ISO, and other styles
6

Hériveaux, Laurent, Jessy Clédière, and Stèphanie Anceau. "Electrical Modeling of the Effect of Photoelectric Laser Fault Injection on Bulk CMOS Design." In ISTFA 2013. ASM International, 2013. http://dx.doi.org/10.31399/asm.cp.istfa2013p0361.

Full text
Abstract:
Abstract Fault injection from infrared laser is a common practice among Information Technology Security Evaluation Facility (ITSEF) labs for testing CMOS circuits, and obtained effects are very versatile. However, from our point of view, the details of the phenomenona that occur in the integrated circuit have yet to be investigated. The common hypothesis is that the photoelectric current created during the light stimulation flows through the P-N junctions, and corrupts voltage outputs of the cells. In this paper, we consider the vertical parasitic bipolar junction transistors inherent to CMOS bulk devices. We show that these parasitic transistors contribute to the injected fault at a higher rate than just the P-N junctions of the OFF MOS side. There are two features of such results. First, the space charge region of the N-well / P-substrate junction is wide and will induce a stronger photocurrent. Second, this current will be amplified by the parasitic bipolar transistor and thus lead to more effects. These results are obtained by electrical simulations on a CMOS inverter. The size of the laser spot is taken into account via neighboring cells that are also illuminated. To induce an effect, small spot size needs a very high-power density, which is not always achievable. Increasing the illuminated area to inject more power is then a solution; simulations illustrate this point.
APA, Harvard, Vancouver, ISO, and other styles
7

Abuayob, Eli, Evgeny Nisenboim, Amir Raveh, Baohua Niu, and Tom Tong. "Complex Waveform Analysis for Advanced CMOS ICs." In ISTFA 2016. ASM International, 2016. http://dx.doi.org/10.31399/asm.cp.istfa2016p0068.

Full text
Abstract:
Abstract Laser scanning microscope (LSM) based waveform acquisition is widely used in advanced CMOS IC design validation and debug application. Complex waveforms obtained from LSM probing on CMOS ICs are often difficult to fully comprehend without deep understanding of the complex physics involved even in planar CMOS. The introduction of 3-D Tri-Gate transistors since 2010 made this even more challenging. In this paper, we present both model based simulation and probing validations on the most advanced 3D Tri-Gate based CMOS ICs that give us a clear understanding of the nature of these complex waveforms.
APA, Harvard, Vancouver, ISO, and other styles
8

Muller, M., M. Bidaud, F. Boeuf, A. Halimaoui, M. Lamy, D. Lenoble, R. Palla, T. Skotnicki, and C. Laviron. "Advanced Junction Engineering for 60nm-CMOS Transistors." In 32nd European Solid-State Device Research Conference. IEEE, 2002. http://dx.doi.org/10.1109/essderc.2002.194932.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Salim, Z. S. M., M. Muhamad, H. Hussin, and N. Ahmad. "CMOS LNA Linearization Employing Multiple Gated Transistors." In 2019 IEEE 13th International Conference on Telecommunication Systems, Services, and Applications (TSSA). IEEE, 2019. http://dx.doi.org/10.1109/tssa48701.2019.8985504.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Marathe, R., W. Wang, Z. Mahmood, L. Daniel, and D. Weinstein. "Resonant body transistors in standard CMOS technology." In 2012 IEEE International Ultrasonics Symposium. IEEE, 2012. http://dx.doi.org/10.1109/ultsym.2012.0071.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Reports on the topic "CMOS Transistors"

1

Mahooti, Rabe'eh. A CMOS circuit generator using differential pass transistors for implementing Boolean functions. Portland State University Library, January 2000. http://dx.doi.org/10.15760/etd.5689.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Palmour, John W. Development of 6H-SiC CMOS Transistors for Insertion into a 350 deg C Operational Amplifier. Fort Belvoir, VA: Defense Technical Information Center, May 1992. http://dx.doi.org/10.21236/ada251339.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Palmour, John W. Development of 6H-SiC CMOS Transistors for Insertion into a 350 deg C Operational Amplifier. Fort Belvoir, VA: Defense Technical Information Center, July 1992. http://dx.doi.org/10.21236/ada253760.

Full text
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the extended bibliographies on the topic 'CMOS Transistors' for particular source types:
Journal articles Dissertations / Theses Books
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography