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Books on the topic 'CMOS Transistors'

Author: Grafiati

Published: 4 June 2021

Last updated: 2 February 2022

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1

1960-, Li Harry W., Boyce David E. 1940-, and Institute of Electrical and Electronics Engineers, eds. CMOS circuit design, layout, and simulation. New Delhi: Prentice-Hall of India, 2004.

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2

CMOS: Circuit design, layout, and simulation. 3rd ed. Piscataway, NJ: IEEE Press, 2010.

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3

Institute of Electrical and Electronics Engineers., ed. CMOS circuit design, layout, and simulation. 2nd ed. New York: IEEE Press, 2005.

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4

1960-, Li Harry W., and Boyce David E. 1940-, eds. CMOS circuit design, layout, and simulation. New York: IEEE Press, 1997.

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5

Baker, R. Jacob. CMOS circuit design, layout, and simulation. New York: IEEE Press, 1998.

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6

Institute of Electrical and Electronics Engineers., ed. CMOS circuit design, layout, and simulation. 2nd ed. Piscataway, NJ: IEEE Press, 2008.

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7

Saijets, Jan. MOSFET RF characterization using bulk and SOI CMOS technologies. [Espoo, Finland]: VTT Technical Research Centre of Finland, 2007.

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8

Youssef, Ahmed A. Nanometer CMOS RFICs for mobile TV applications. Dordrecht: Springer, 2010.

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9

Ma, Vivian Wing Yan. Integration of complementary EDMOS transistors in a standard 0.35[mu]m CMOS technology for 40V applications. Ottawa: National Library of Canada, 2003.

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10

El-Khatib, Ziad. Distributed CMOS bidirectional amplifiers: Broadbanding and linearization techniques. New York: Springer, 2012.

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11

Chang, Zhong Yuan. Low-noise wide-band amplifiers in bipolar and CMOS technologies. Boston: Kluwer Academic Publishers, 1991.

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12

Hossein, Sarbishaei, and Sachdev Manoj, eds. ESD protection device and circuit design for advanced CMOS technologies. [Dordrecht]: Springer, 2008.

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13

Madrid, Philip E. Device design and process window analysis of a deep submicron CMOS VLSI technology. Reading, Mass: Addison-Wesley, 1992.

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14

D, Buchanan Bert, ed. CMOS/TTL digital systems design. New York: McGraw-Hill, 1990.

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15

BiCMOS/CMOS systems design. New York: McGraw-Hill, 1991.

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16

Heusler, Lucas Sebastian. Transistor sizing for timing optimization of combinational digital CMOS circuits. [Konstanz, Switzerland: Hartung-Gorre Verlag, 1990.

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17

Heusler, Lucas S. Transistor sizing for timing optimization of combinational digital CMOS circuits. Konstanz: Hartung-Gorre, 1990.

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18

Magierowski, Sebastian Claudiusz. A PMOS transistor for a low-power 1 V CMOS process. Ottawa: National Library of Canada = Bibliothèque nationale du Canada, 1999.

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19

E, Buchanan James. Signal and power integrity in digital systems: TTL, CMOS, and BiCMOS. New York: McGraw-Hill, 1996.

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20

Analysis of Bipolar and CMOS Amplifiers. CRC, 2007.

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21

Huang, Feng-Jung. Schottky clamped MOS transistors for wireless CMOS radio frequency switch applications. 2001.

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22

Baker, R. Jacob. CMOS Circuit Design, Layout, and Simulation. Wiley-IEEE Press, 2004.

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23

Lee, Jonghwan. Comprehensive compact noise modeling of nanoscale CMOS devices. 2003.

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24

Hwang, Nam. Physical mechanisms, device models, and lifetime projections of hot-carrier effects in CMOS transistors. 1993.

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25

Zhou, Jianjun J. CMOS low noise amplifier design utilizing monolithic transformers. 1998.

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26

Youssef, Ahmed A., and James Haslett. Nanometer CMOS RFICs for Mobile TV Applications. Springer, 2010.

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27

Rezaei, Farshid. Realizing vertical bipolar transistors in a standard CMOS technology for the design of low-cost BiCMOS integrated circuits. 2004.

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28

Paul, Douglas J. Si/SiGe heterostructures in nanoelectronics. Edited by A. V. Narlikar and Y. Y. Fu. Oxford University Press, 2017. http://dx.doi.org/10.1093/oxfordhb/9780199533060.013.5.

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Abstract:

This article describes the applications of Si/SiGe heterostructures in nanoelectronics. Silicon-germanium is now a mature field with heterojunction bipolar transistors (HBTs) and complementary metal oxide semiconductors (CMOS) products in the market place. In the research field there are many areas where Si/SiGe heterostructures are being used to bandgap engineer nanoelectronic devices resulting in significant improvements in device performance. A number of these areas have good potential for eventually reaching production, while thereare also many that allow fundamental research on the physics of materials anddevices. This article begins with an overview of the growth of silicon-germanium alloys, followed by a discussion of the effect of strain on the band structure and properties of Si/SiGe devices. It then considers two mainstream nanoelectronic applications of Si/SiGe heterostructures, namely HBTs and CMOS. It also looks at resonant tunnelling diodes and SiGe quantum cascade emitters.

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29

Sansen, Willy M. C., and Zhong Yuan Chong. Low-Noise Wide-Band Amplifiers in Bipolar and CMOS Technologies (The International Series in Engineering and Computer Science). Springer, 1990.

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30

Pasternak, John Henry. CMOS pass-transistor logic design for VLSI. 1987.

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31

Mahapatra, Santanu, and Adrian Mihai Ionescu. Hybrid CMOS Single-Electron-Transistor Device And Circuit Design. Artech House Publishers, 2006.

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32

Feletou. Liste équivalences transistors: Bipolaires, FET, Puissance, CMS. Dunod, 1993.

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33

Félétou, G. Equivalences transistors, volume 2 : Bipolaire - FET - Puissance - CMS. Dunod, 1992.

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34

Steele, Gordon R. Transistor sizing in the design of high-speed CMOS super buffers. 1988.

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35

Buchanan, James E. Signal and Power Integrity in Digital Systems: TTL, CMOS, and BiCMOS. McGraw-Hill Companies, 1995.

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36

(Illustrator), Bert D. Buchanan, ed. Signal and Power Integrity in Digital Systems: TTL, CMOS, and BiCMOS. McGraw-Hill Companies, 1995.

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37

Saint, Judy, and Christopher Saint. IC Layout Basics : A Practical Guide. McGraw-Hill Professional, 2001.

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38

Saint, Judy, and Christopher Saint. IC Layout Basics : A Practical Guide. McGraw-Hill Professional, 2001.

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