Journal articles: 'CMOS Transistors'

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Pan, James N. "Chromatic and Panchromatic Nonlinear Optoelectronic CMOSFETs for CMOS Image Sensors, Laser Multiplexing, Computing, and Communication." MRS Advances 5, no. 37-38 (2020): 1965–74. http://dx.doi.org/10.1557/adv.2020.273.

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AbstractTraditionally, CMOS transistors are for low power, high speed, and high packing density applications. CMOS is also commonly used as power regulating devices, and light sensors (CCD or CMOS image sensors). In this paper, we would like to introduce Photonic CMOS as a light emitting device for optical computing, ASIC, power transistors, and ultra large scale integration (ULSI). A Photonic CMOS Field Effect Transistor is fabricated with a low-resistance laser or LED in the drain region, and multiple photon sensors in the channel / well regions. The MOSFET, laser, and photon sensors are fabricated as one integral transistor. With embedded nonlinear optical films, the Photonic CMOSFETs have the capability of detecting and generating focused laser beams of various frequencies to perform optical computing, signal modulation, polarization, and multiplexing for digital / analog processing and communication.

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Stegemann, S., J. Xiong, and W. Mathis. "Modellierung von Quanteneffekten in einem ladungsbasierten MOS-Transistor-Modell zur Simulation von nanoskalierten CMOS-Analogschaltungen." Advances in Radio Science 7 (May 19, 2009): 185–90. http://dx.doi.org/10.5194/ars-7-185-2009.

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Abstract. Aufgrund der fortschreitenden Miniaturisierung der Bauelemente in CMOS-Schaltungen und den dadurch erreichten Strukturgrößen nehmen quantenmechanische Effekte zunehmenden Einfluss auf die Funktion von Transistoren und damit auf die gesamte Schaltung. Unter Einbeziehung der Energiequantisierung an der Si/SiO2-Grenzfläche wird untersucht, wie sich durch eine Modifikation der Beschreibung des Oberflächenpotenzials die Inversionsladung quantenmechanisch formulieren lässt. Im Hinblick auf den Entwurf und die Simulation von CMOS-Analogschaltungen wird dazu ein ladungsbasiertes MOS-Transistor-Modell zugrunde gelegt. Die sich daraus ergebenden Veränderungen für die Kapazitäten und die Inversionsladung werden dabei für die Modellierung des quasiballistischen Drain-Source-Stromes verwendet. Dazu wird innerhalb dieses Modells ein Streufaktor berechnet, mit dem nanoskalierte MOS-Transistoren mit einer Kanallänge von unter 20 nm simuliert werden können. Ausgehend von Parametern eines CMOS-Prozesses werden mit MATLAB die Einflüsse der quantenmechanischen Effekte bei der Skalierung des Transistors analysiert.

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Radamson, Henry H., Xiaobin He, Qingzhu Zhang, Jinbiao Liu, Hushan Cui, Jinjuan Xiang, Zhenzhen Kong, et al. "Miniaturization of CMOS." Micromachines 10, no. 5 (April 30, 2019): 293. http://dx.doi.org/10.3390/mi10050293.

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When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.

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Angelov, George V., Dimitar N. Nikolov, and Marin H. Hristov. "Technology and Modeling of Nonclassical Transistor Devices." Journal of Electrical and Computer Engineering 2019 (November 3, 2019): 1–18. http://dx.doi.org/10.1155/2019/4792461.

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This paper presents a comprehensive outlook for the current technology status and the prospective upcoming advancements. VLSI scaling trends and technology advancements in the context of sub-10-nm technologies are reviewed as well as the associated device modeling approaches and compact models of transistor structures are considered. As technology goes into the nanometer regime, semiconductor devices are confronting numerous short-channel effects. Bulk CMOS technology is developing and innovating to overcome these constraints by introduction of (i) new technologies and new materials and (ii) new transistor architectures. Technology boosters such as high-k/metal-gate technologies, ultra-thin-body SOI, Ge-on-insulator (GOI), AIII–BV semiconductors, and band-engineered transistor (SiGe or Strained Si-channel) with high-carrier-mobility channels are examined. Nonclassical device structures such as novel multiple-gate transistor structures including multiple-gate field-effect transistors, FD-SOI MOSFETs, CNTFETs, and SETs are examined as possible successors of conventional CMOS devices and FinFETs. Special attention is devoted to gate-all-around FETs and, respectively, nanowire and nanosheet FETs as forthcoming mainstream replacements of FinFET. In view of that, compact modeling of bulk CMOS transistors and multiple-gate transistors are considered as well as BSIM and PSP multiple-gate models, FD-SOI MOSFETs, CNTFET, and SET modeling are reviewed.

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SELLAMI, L., S. K. SINGH, R. W. NEWCOMB, A. RASMUSSEN, and M. E. ZAGHLOUL. "VLSI FLOATING RESISTORS FOR NEURAL TYPE CELL ARRAYS." Journal of Circuits, Systems and Computers 08, no. 05n06 (October 1998): 559–69. http://dx.doi.org/10.1142/s0218126698000353.

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Two novel CMOS circuit designs implementing floating resistors are introduced, using the structure of a two-transistor CMOS bilateral linear resistor in the first configuration and two two-transistor CMOS bilateral linear resistors and cascode current mirrors in the second configuration. Linearity is achieved through nonlinearity cancellation via current mirrors over an applied range of ±5V. PSpice simulation results using parameters of MOSIS transistors are presented to verify the theory. These floating resistors can be used for coupling weights in VLSI neural-type cell arrays.

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Weng, Wu-Te, Yao-Jen Lee, Horng-Chih Lin, and Tiao-Yuan Huang. "Plasma-Induced Damage on the Reliability of Hf-Based High-k/Dual Metal-Gates Complementary Metal Oxide Semiconductor Technology." International Journal of Plasma Science and Engineering 2009 (December 14, 2009): 1–10. http://dx.doi.org/10.1155/2009/308949.

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This study examines the effects of plasma-induced damage (PID) on Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates that thinning the gate dielectric reduces the impact of damage on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO2/poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for high-k/metal-gate CMOS technology.

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Jiang, Jin Tao, Li Fang Ye, and Jian Ping Hu. "Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration." Applied Mechanics and Materials 39 (November 2010): 73–78. http://dx.doi.org/10.4028/www.scientific.net/amm.39.73.

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Leakage power reduction is extremely important in the design of nano-circuits. Gate leakage has become a significant component in currently used nanometer CMOS processes with gate oxide structure. The structure and operation of the PAL-2P (pass-transistor adiabatic logic with PMOS pull-up configuration) circuits that consist mostly of PMOS transistors are complementary to PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) ones that consist mostly of NMOS transistors. This paper investigates gate leakage reduction of the PAL-2P circuits in nanometer CMOS processes with gate oxide materials. An s27 benchmark circuit from the ISCAS89 sequential benchmark set is verified using the PAL-2P scheme. All circuits are simulated with HSPICE using the 65nm CMOS process with gate oxide materials. Based on the power dissipation models of PAL-2P adiabatic circuits, active leakage dissipations are estimated by testing total leakage dissipations using SPICE simulations. The PAL-2P circuits consume low static power compared with traditional PAL-2N ones.

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Lee, Sang-Hoon, Min-Jae Seo, Amos Amoako Boampong, Jae-Hyeok Cho, Kyeong Min Yu, and Min-Hoi Kim. "Solution-Processed Organic and Oxide Hybrid CMOS Inverter for Low Cost Electronic Circuits." Journal of Nanoscience and Nanotechnology 20, no. 7 (July 1, 2020): 4381–84. http://dx.doi.org/10.1166/jnn.2020.17600.

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We demonstrated an organic and oxide hybrid CMOS inverter with the solution-processed semiconductor and source/drain electrodes. For the solution-processed n- and p-type semiconductor, InGaZnO solution and TIPS-pentacene/PαMS blend were spin-coated respectively while Silver ink and PEDOT:PSS solution were drop-casted with the help of the bank to serve as source/drain electrodes. The InGaZnO and the TIPS-pentacene transistors show typical n- and p-type transistor operations with low off-current. Based on the combination of the solution-processed n- and p-type transistors, full-swing characteristic curve with low static current of the hybrid CMOS were obtained.

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Ahmad, Nabihah, and Rezaul Hasan. "A 0.8 V 0.23 nW 1.5 ns Full-Swing Pass-Transistor XOR Gate in 130 nm CMOS." Active and Passive Electronic Components 2013 (2013): 1–6. http://dx.doi.org/10.1155/2013/148518.

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A power efficient circuit topology is proposed to implement a low-voltage CMOS 2-input pass-transistor XOR gate. This design aims to minimize power dissipation and reduce transistor count while at the same time reducing the propagation delay. The XOR gate utilizes six transistors to achieve a compact circuit design and was fabricated using the 130 nm IBM CMOS process. The performance of the XOR circuit was validated against other XOR gate designs through simulations using the same 130 nm CMOS process. The area of the core circuit is only about 56 sq · µm with 1.5659 ns propagation delay and 0.2312 nW power dissipation at 0.8 V supply voltage. The proposed six-transistor implementation thus compares favorably with other existing XOR gate designs.

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Vidhyadharan, Abhay Sanjay, and Sanjay Vidhyadharan. "Improved hetero-junction TFET-based Schmitt trigger designs for ultra-low-voltage VLSI applications." World Journal of Engineering 18, no. 5 (March 26, 2021): 750–59. http://dx.doi.org/10.1108/wje-08-2020-0367.

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Purpose Tunnel field effect transistors (TFETs) have significantly steeper sub-threshold slope (24–30 mv/decade), as compared with the conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), which have a sub-threshold slope of 60 mv/decade at room temperature. The steep sub-threshold slope of TFETs enables a much faster switching, making TFETs a better option than MOSFETs for low-voltage VLSI applications. The purpose of this paper is to present a novel hetero-junction TFET-based Schmitt triggers, which outperform the conventional complementary metal oxide semiconductor (CMOS) Schmitt triggers at low power supply voltage levels. Design/methodology/approach The conventional Schmitt trigger has been implemented with both MOSFETs and HTFETs for operation at a low-voltage level of 0.4 V and a target hysteresis width of 100 mV. Simulation results have indicated that the HTFET-based Schmitt trigger not only has significantly lower delays but also consumes lesser power as compared to the CMOS-based Schmitt trigger. The limitations of the conventional Schmitt trigger design have been analysed, and improved CMOS and CMOS–HTFET hybrid Schmitt trigger designs have been presented. Findings The conventional Schmitt trigger implemented with HTFETs has 99.9% lower propagation delay (29ps) and 41.2% lesser power requirement (4.7 nW) than the analogous CMOS Schmitt trigger, which has a delay of 36 ns and consumes 8 nW of power. An improved Schmitt trigger design has been proposed which has a transistor count of only six as compared to the eight transistors required in the conventional design. The proposed improved Schmitt trigger design, when implemented with only CMOS devices enable a reduction of power delay product (PDP) by 98.4% with respect to the CMOS conventional Schmitt trigger design. The proposed CMOS–HTFET hybrid Schmitt trigger further helps in decreasing the delay of the improved CMOS-only Schmitt trigger by 70% and PDP by 21%. Originality/value The unique advantage of very steep sub-threshold slope of HTFETs has been used to improve the performance of the conventional Schmitt trigger circuit. Novel CMOS-only and CMOS–HTFET hybrid improved Schmitt trigger designs have been proposed which requires lesser number of transistors (saving 70% chip area) for implementation and has significantly lower delays and power requirement than the conventional designs.

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Park, ChangMin, SeHan Lee, MinSu Choi, MyungGil Kang, YoungChai Jung, SungWoo Hwang, Doyeol Ahn, JungHyeon Lee, and ChangRyong Song. "Fabrication of Poly-Silicon Nano-Wire Transistors on Plastic Substrates." Journal of Nanoscience and Nanotechnology 7, no. 11 (November 1, 2007): 4150–53. http://dx.doi.org/10.1166/jnn.2007.015.

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We report the fabrication and characterization of poly-Si nanowire transistors on flexible substrates. The nanowire transistors are fabricated on a SiO2/Si substrate using conventional CMOS processes, and then they are transferred onto polyimide substrates. The transfer process is performed by spin-coating of polyimide, curing (annealing) of the polyimide layer, and removal of the SiO2 sacrificial layer. The optimized curing condition results in the maximum bending of 150° with full recovery. The nanowire transistors exhibit transistor characteristics as a function of the backgate bias. Our new process can be applied to the fabrication of Si-nanowire transistors with larger mobilities.

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Park, ChangMin, SeHan Lee, MinSu Choi, MyungGil Kang, YoungChai Jung, SungWoo Hwang, Doyeol Ahn, JungHyeon Lee, and ChangRyong Song. "Fabrication of Poly-Silicon Nano-Wire Transistors on Plastic Substrates." Journal of Nanoscience and Nanotechnology 7, no. 11 (November 1, 2007): 4150–53. http://dx.doi.org/10.1166/jnn.2007.18093.

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We report the fabrication and characterization of poly-Si nanowire transistors on flexible substrates. The nanowire transistors are fabricated on a SiO2/Si substrate using conventional CMOS processes, and then they are transferred onto polyimide substrates. The transfer process is performed by spin-coating of polyimide, curing (annealing) of the polyimide layer, and removal of the SiO2 sacrificial layer. The optimized curing condition results in the maximum bending of 150° with full recovery. The nanowire transistors exhibit transistor characteristics as a function of the backgate bias. Our new process can be applied to the fabrication of Si-nanowire transistors with larger mobilities.

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Jin, Xin Yu, Cheng Li, Jun Biao Liu, Xiao Feng Jiang, and Xiang Bing Zeng. "Ternary Logic Dynamic CMOS Comparators." Advanced Materials Research 317-319 (August 2011): 1177–82. http://dx.doi.org/10.4028/www.scientific.net/amr.317-319.1177.

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In this paper, a new method of ternary logic circuit design is developed. It’s proposed that two types of static ternary CMOS comparators and three types of dynamic CMOS comparators, designed by new method, with low transistor count, high speed and low power consumption. The proposed comparators are the rearrangement and reordering of transistors in the evaluation block of a dynamic cell. These ternary comparators can be used as equality comparators, mutual comparators and zero/one/two detectors, which are widely used in build in self test and memory testing.

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FLANDRE, D., J. P. RASKIN, and D. VANHOENACKER-JANVIER. "SOI CMOS TRANSISTORS FOR RF AND MICROWAVE APPLICATIONS." International Journal of High Speed Electronics and Systems 11, no. 04 (December 2001): 1159–248. http://dx.doi.org/10.1142/s0129156401001076.

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The new communication markets are vey demanding: high frequency, high degree of integration, low power consumption. Silicon-on-Insulator offers many advantages and this paper illustrates the potentialities of this technology for RF and microwave applictions. After an overview of the SOI material, the properties of the SOI MOSFET's are analyzed and compared to bulk Si MOSFET's. The models of transmission lines and inductors on SOI are compared and further used in the on-wafer characterization of the transistors. Various models for the transistors are presented and their limitations are given. A new model is described, valid from DC to the microwave region. This model agrees very well with the measurements for various transistor dimensions. Finally, variuos RF and microware circuits are presented. Ths paper does not fully describe all the properties and applications of SOI but the numerous references offered to the reader help him to gather more informations.

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Lu, Bin Bin, and Jian Ping Hu. "Complementary Pass-Transistor Adiabatic Logic Using Dual Threshold CMOS Techniques." Applied Mechanics and Materials 39 (November 2010): 55–60. http://dx.doi.org/10.4028/www.scientific.net/amm.39.55.

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With rapid technology scaling down, the energy dissipation of nanometer CMOS circuits is becoming a major concern, because of the increasing sub-threshold leakage in nanometer CMOS processes. This paper introduces a dual threshold CMOS (DTCMOS) technique for CPAL (complementary pass-transistor adiabatic logic) circuits to reduce sub-threshold leakage dissipations. The method to size the transistors of the dual-threshold CPAL gates is also discussed. A full adder using dual-threshold CPAL circuits is realized using 45nm BSIM4 CMOS model. HSPICE simulation results show that leakage dissipations of the CPAL full adder with DTCMOS techniques are reduced compared with the basic CPAL one.

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Ferndahl, Mattias, Ted Johansson, and Herbert Zirath. "Design and evaluation of 20-GHz power amplifiers in 130-nm CMOS." International Journal of Microwave and Wireless Technologies 1, no. 4 (June 19, 2009): 301–7. http://dx.doi.org/10.1017/s1759078709990316.

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The use of 130-nm CMOS for power amplifiers at 20 GHz is explored through a set of power amplifiers as well as transistor level measurements. The power amplifiers explore single versus cascode configuration, smaller versus larger transistor sizes, and the combination of two amplifiers using power splitters/combiners. A maximum output power of 63 mW at 20 GHz was achieved. Transistor-level characterization using load pull measurements on 1-mm gate width transistors yielded 148-mW/mm output power. Transistor modeling and layout for power amplifiers are also discussed. An estimate on the maximum achievable output at 20 GHz from 130-nm CMOS power amplifiers, based on findings in this paper and the literature, is finally presented.

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Shaheen, Saleh, Gady Golan, Moshe Azoulay, and Joseph Bernstein. "A comparative study of reliability for finfet." Facta universitatis - series: Electronics and Energetics 31, no. 3 (2018): 343–66. http://dx.doi.org/10.2298/fuee1803343s.

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The continuous downscaling of CMOS technologies over the last few decades resulted in higher Integrated Circuit (IC) density and performance. The emergence of FinFET technology has brought with it the same reliability issues as standard CMOS with the addition of a new prominent degradation mechanism. The same mechanisms still exist as for previous CMOS devices, including Bias Temperature Instability (BTI), Hot Carrier Degradation (HCD), Electro-migration (EM), and Body Effects. A new and equally important reliability issue for FinFET is the Self -heating, which is a crucial complication since thermal time-constant is generally much longer than the transistor switching times. FinFET technology is the newest technological paradigm that has emerged in the past decade, as downscaling reached beyond 20 nm, which happens also to be the estimated mean free path of electrons at room temperature in silicon. As such, the reliability physics of FinFET was modified in order to fit the newly developed transistor technology. This paper highlights the roles and impacts of these various effects and aging mechanisms on FinFET transistors compared to planar transistors on the basic approach of the physics of failure mechanisms to fit to a comprehensive aging model.

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ZHANG, WEIQIANG, LI SU, YU ZHANG, LINFENG LI, and JIANPING HU. "LOW-LEAKAGE FLIP-FLOPS BASED ON DUAL-THRESHOLD AND MULTIPLE LEAKAGE REDUCTION TECHNIQUES." Journal of Circuits, Systems and Computers 20, no. 01 (February 2011): 147–62. http://dx.doi.org/10.1142/s0218126611007128.

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The scaling of transistor sizes has resulted in dramatic increase of leakage currents. The sub-threshold and gate leakages have now become a major contributor to total power dissipations. This paper presents two flip-flops based on dual-threshold CMOS and multiple leakage reduction techniques to reduce their leakage dissipations. In the DT-TG FF (Dual-Threshold Transmission Gate Flip-Flop), some transistors on non-critical paths use high-threshold devices to reduce their leakage currents, while the other transistors on critical paths use low-threshold devices to maintain performance. The MLRT FF (Multiple Leakage Reduction Technique Flip-Flop) uses P-type CMOS techniques, MTCMOS (Multi-Threshold CMOS) power-gating and dual-threshold technique to reduce both sub-threshold and gate leakage dissipations. Taken as an example, a practical sequential system realized with the two low-leakage flip-flops is demonstrated using a mode-5 × 5 × 5 counter. The simulation results show that the two flip-flops achieve considerable leakage reductions.

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Agha, Firas, Yasir Naif, and Mohammed Shakib. "Review of Nanosheet Transistors Technology." Tikrit Journal of Engineering Sciences 28, no. 1 (May 20, 2021): 40–48. http://dx.doi.org/10.25130/tjes.28.1.05.

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Nano-sheet transistor can be defined as a stacked horizontally gate surrounding the channel on all direction. This new structure is earning extremely attention from research to cope the restriction of current Fin Field Effect Transistor (FinFET) structure. To further understand the characteristics of nano-sheet transistors, this paper presents a review of this new nano-structure of Metal Oxide Semiconductor Field Effect Transistor (MOSFET), this new device that consists of a metal gate material. Lateral nano-sheet FET is now targeting for 3nm Complementary MOS (CMOS) technology node. In this review, the structure and characteristics of Nano-Sheet FET (NSFET), FinFET and NanoWire FET (NWFET) under 5nm technology node are presented and compared. According to the comparison, the NSFET shows to be more impregnable to mismatch in ON current than NWFET. Furthermore, as comparing with other nanodimensional transistors, the NSFET has the superior control of gate all-around structures, also the NWFET realize lower mismatch in sub threshold slope (SS) and drain induced barrier lowering (DIBL).

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Nam, Hyoungsik, Young-In Kim, Jina Bae, and Junhee Lee. "GateRL: Automated Circuit Design Framework of CMOS Logic Gates Using Reinforcement Learning." Electronics 10, no. 9 (April 26, 2021): 1032. http://dx.doi.org/10.3390/electronics10091032.

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This paper proposes a GateRL that is an automated circuit design framework of CMOS logic gates based on reinforcement learning. Because there are constraints in the connection of circuit elements, the action masking scheme is employed. It also reduces the size of the action space leading to the improvement on the learning speed. The GateRL consists of an agent for the action and an environment for state, mask, and reward. State and reward are generated from a connection matrix that describes the current circuit configuration, and the mask is obtained from a masking matrix based on constraints and current connection matrix. The action is given rise to by the deep Q-network of 4 fully connected network layers in the agent. In particular, separate replay buffers are devised for success transitions and failure transitions to expedite the training process. The proposed network is trained with 2 inputs, 1 output, 2 NMOS transistors, and 2 PMOS transistors to design all the target logic gates, such as buffer, inverter, AND, OR, NAND, and NOR. Consequently, the GateRL outputs one-transistor buffer, two-transistor inverter, two-transistor AND, two-transistor OR, three-transistor NAND, and three-transistor NOR. The operations of these resultant logics are verified by the SPICE simulation.

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Ghabri, H., D. Ben Issa, and H. Samet. "Performance Optimization of 1-bit Full Adder Cell based on CNTFET Transistor." Engineering, Technology & Applied Science Research 9, no. 6 (December 1, 2019): 4933–36. http://dx.doi.org/10.48084/etasr.3156.

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The full adder is a key component for many digital circuits like microprocessors or digital signal processors. Its main utilization is to perform logical and arithmetic operations. This has empowered the designers to continuously optimize this circuit and ameliorate its characteristics like robustness, compactness, efficiency, and scalability. Carbon Nanotube Field Effect Transistor (CNFET) stands out as a substitute for CMOS technology for designing circuits in the present-day technology. The objective of this paper is to present an optimized 1-bit full adder design based on CNTFET transistors inspired by new CMOS full adder design [1] with enhanced performance parameters. For a power supply of 0.9V, the count of transistors is decreased to 10 and the power is almost split in two compared to the best existing CNTFET based adder. This design offers significant improvement when compared to existing designs such as C-CMOS, TFA, TGA, HPSC, 18T-FA adder, etc. Comparative data analysis shows that there is 37%, 50%, and 49% amelioration in terms of area, delay, and power delay product respectively compared to both CNTFET and CMOS based adders in existing designs. The circuit was designed in 32nm technology and simulated with HSPICE tools.

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Holmes, Jim, A. Matthew Francis, Ian Getreu, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. "Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application." Journal of Microelectronics and Electronic Packaging 13, no. 4 (October 1, 2016): 143–54. http://dx.doi.org/10.4071/imaps.527.

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In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circuits for extended periods (up to 100 h) are presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at extreme temperatures for any period. Based on these results, Venus nominal temperature (470°C) transistor models and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller. A 16-bit microcontroller, based on the OpenMSP 16-bit core, is demonstrated through physical design and simulation in SiC-CMOS, with an eye for Venus as well as terrestrial applications.

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Nebhen, Jamel, Julien Dubois, Sofiene Mansouri, and Dominique Ginhac. "Low-noise and low power CMOS photoreceptor using split-length MOSFET." Journal of Electrical Engineering 70, no. 6 (December 1, 2019): 480–85. http://dx.doi.org/10.2478/jee-2019-0081.

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Abstract This paper presents the design of a low-power and low-noise CMOS photo-transduction circuit. We propose to use the new technique of composite transistors for noise reduction of photoreceptor in the subthreshold by exploiting the small size effects of CMOS transistors. Several power and noise optimizations, design requirements, and performance limitations relating to the CMOS photoreceptor are presented. This new structure with composite transistors ensures low noise and low power consumption. The CMOS photoreceptor, implemented in a 130 nm standard CMOS technology with a 1.2 V supply voltage, achieves a noise floor of 2μV/⎷Hz within the frequency range from 1 Hz to 10 kHz. The current consumption of the CMOS photoreceptor is 541 nA. This paper shows the need for the design of phototransduction circuit at low voltage, low noise and how these constraints are reflected in the design of CMOS vision sensor.

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NASEH, SASAN, and M. JAMAL DEEN. "RF CMOS RELIABILITY." International Journal of High Speed Electronics and Systems 11, no. 04 (December 2001): 1249–95. http://dx.doi.org/10.1142/s0129156401001088.

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In this chapter the effects of hot carrier on the reliability of NMOS transistors are investigated. First, it is explained why the hot carrier issue can be important in RF CMOS circuits. Important mechanisms of hot carrier generation are reviewed and some of the techniques used in the measurement of hot carrier damages are explained. Next, results of measurement of DC hot carrier stress on the NMOS transistors are presented. The main focus here is the RF performance of the NMOS devices and circuits mode of them, but DC parameters of the device such as its I-V characteristics and threshold voltage are presented, as they directly affect the RF performance. Finally, using the measurements of hot carrier effects on single NMOS transistors, the effects of hot carriers on three parameters of a low noise amplifier, matching, power gain and stability, are predicted using circuit simulation.

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Li, Zhichao, Shiheng Yang, Samuel B. S. Lee, and Kiat Seng Yeo. "A Two-Stage X-Band 20.7-dBm Power Amplifier in 40-nm CMOS Technology." Electronics 9, no. 12 (December 20, 2020): 2198. http://dx.doi.org/10.3390/electronics9122198.

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For higher integration density, X-band power amplifiers (PAs) with CMOS technology have been widely discussed in recent publications. However, with reduced power supply voltage and device size, it is a great challenge to design a compact PA with high output power and power-added efficiency (PAE). In the proposed design, a 40-nm standard CMOS process is used for higher integration with other RF building blocks, compared with other CMOS PA designs with larger process node. Transistor cells are designed with neutralization capacitors to increase stability and gain performance of the PA. As a trade-off among gain, output power, and PAE, the transistor cells in driving stage and power stage are biased for class A and class AB operation, respectively. Both transistor cells consist of two transistors working in differential mode. Furthermore, transformer-based matching networks (TMNs) are used to realize a two-stage X-band CMOS PA with compact size. The PA achieves an effective conductivity (EC) of 117.5, which is among the highest in recently reported X-band PAs in CMOS technology. The PA also attains a saturated output power (Psat) of 20.7 dBm, a peak PAE of 22.4%, and a gain of 25.6 dB at the center frequency of 10 GHz under a 1 V supply in 40-nm CMOS.

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Idris, Muhammad I., Ming Hung Weng, H. K. Chan, A. E. Murphy, Dave A. Smith, R. A. R. Young, Ewan P. Ramsay, David T. Clark, Nick G. Wright, and Alton B. Horsfall. "Electrical Stability Impact of Gate Oxide in Channel Implanted SiC NMOS and PMOS Transistors." Materials Science Forum 897 (May 2017): 513–16. http://dx.doi.org/10.4028/www.scientific.net/msf.897.513.

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Operation of SiC MOSFETs beyond 300°C opens up opportunities for a wide range of CMOS based digital and analogue applications. However the majority of the literature focuses only on the optimization of a single type of MOS device (either PMOS or more commonly NMOS) and there is a lack of a comprehensive study describing the challenge of optimizing CMOS devices. This study reports on the impact of gate oxide performance in channel implanted SiC on the electrical stability for both NMOS and PMOS capacitors and transistors. Parameters including interface state density (Dit), flatband voltage (VFB), threshold voltage (VTH) and effective charge (NEFF) have been acquired from C-V characteristics to assess the effectiveness of the fabrication process in realising high quality gate dielectrics. The performance of SiC based CMOS transistors were analyzed by correlating the characteristics of the MOS interface properties, the MOSFET 1/f noise performance and transistor on-state stability at 300°C. The observed instability of PMOS devices is more significant than in equivalent NMOS devices. The results from MOS capacitors comprising interface state density (Dit), flatband voltage (VFB), threshold voltage (VTH) for both N and P MOS are in agreement with the expected characteristics of the respective transistors.

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Roberts, J., T. MacElwee, and L. Yushyna. "The Thermal Integrity of Integrated GaN Power Modules." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, HITEN (January 1, 2013): 000061–68. http://dx.doi.org/10.4071/hiten-mp12.

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In this paper the authors describe GaN (gallium nitride) power switching transistors that use copper post and substrate via interconnect techniques. These transistors can be matrixed to allow a parallel array of the devices to provide very low on-resistance and high operating voltages. At 150 °C the basic building block which is a 2 × 2 mm die, provides 1200 V / 14 A. A 2×2 matrix array of these transistors provides for example, 1200 V / 56 A operation. The overall GaN device size is 4 × 4 mm. This high current density is achieved by using a unique castellated island topology. This provides short fingers that are not required to carry high current. No high current tracks are provided on-chip because on-chip metal is typically less than 3 microns thick. The die has 12 copper posts on the source islands that carry the current to the CMOS driver device. The CMOS driver is used in a cascode configuration which allows the normally-on GaN transistor to be operated with convenient normally-off functionality. The two devices are combined in a modular assembly. The paper provides a thermal analysis of the assembly. The objective of the design is to keep the ‘junction’ temperature of the GaN transistor below 150 °C.

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Puhan, Janez, Dušan Raič, Tadej Tuma, and Árpád Bűrmen. "Break-before-Make CMOS Inverter for Power-Efficient Delay Implementation." Scientific World Journal 2014 (2014): 1–11. http://dx.doi.org/10.1155/2014/349131.

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A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell.

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Han, Heesung, and Chang-Hyun Kim. "Prediction of a Two-Transistor Vertical QNOT Gate." Applied Sciences 10, no. 21 (October 29, 2020): 7597. http://dx.doi.org/10.3390/app10217597.

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A new design of quaternary inverter (QNOT gate) is proposed by means of finite-element simulation. Traditionally, increasing the number of data levels in digital logic circuits was achieved by increasing the number of transistors. Our QNOT gate consists of only two transistors, resembling the binary complementary metal-oxide-semiconductor (CMOS) inverter, yet the two additional levels are generated by controlling the charge-injection barrier and electrode overlap. Furthermore, these two transistors are stacked vertically, meaning that the entire footprint only consumes the area of one single transistor. We explore several key geometrical and material parameters in a series of simulations to show how to systematically modulate and optimize the quaternary logic behaviors.

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., Gudala Konica, and Sreenivasulu Mamilla . "Design and Analysis of CMOS and CNTFET based Ternary Operators for Scrambling." Volume 4,Issue 5,2018 4, no. 5 (January 5, 2019): 575–79. http://dx.doi.org/10.30799/jnst.187.18040530.

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As silicon technology scales down, it is a dominant choice to have high-performance digital circuits. As researchers investigated for high-performance digital circuits for future generations, Carbon Nanotube Field Effect Transistors (CNTFETs) is considered as the most promising technology due to their excellent current driving capability and proved to be an alternative to conventional CMOS technology. A CNTFET based energy efficient ternary operators are proposed for scrambling applications. The transistor-level implementations of operators namely Scrambling Operator1 (SOP1), Scrambling Operator2 (SOP2) and SUM operators are simulated with CMOS and CNTFET in 32 nm technology at 0.9 V supply voltage using Synopsys HSPICE. The performance metrics like Power, Delay and Power-delay product (PDP) are measured and a comparative analysis for CNTFET and CMOS technologies is carried out. The results demonstrate that CNTFET designs have better-optimized results in power, energy consumption, and reduced transistor count.

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Reid, Dave, Campbell Millar, Scott Roy, Gareth Roy, Richard Sinnott, Gordon Stewart, Graeme Stewart, and Asen Asenov. "Enabling cutting-edge semiconductor simulation through grid technology." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 367, no. 1897 (June 28, 2009): 2573–84. http://dx.doi.org/10.1098/rsta.2009.0031.

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The progressive scaling of complementary metal oxide semiconductor (CMOS) transistors drives the success of the global semiconductor industry. Detailed knowledge of transistor behaviour is necessary to overcome the many fundamental challenges faced by chip and systems designers. Grid technology has enabled the unavoidable statistical variations introduced by scaling to be examined in unprecedented detail. Over 200 000 transistors have been simulated, the results of which provide detailed insight into underlying physical processes. This paper outlines recent scientific results of the nanoCMOS project and describes the way in which the scientific goals have been reflected in the grid-based e-Infrastructure.

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Kempf, P., R. Hadaway, and J. Kolk. "Complementary metal oxide semiconductor compatible high-voltage transistors." Canadian Journal of Physics 65, no. 8 (August 1, 1987): 1003–8. http://dx.doi.org/10.1139/p87-161.

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The purpose of this work was to study the implementation of high-voltage transistors using standard 3–5 μm complementary metal oxide semiconductor (CMOS) technology with a minimum of additional photolithographic or implant steps. A fabrication process was designed to accommodate a variety of high-voltage transistors with greater than 450 V breakdown voltage and low-voltage CMOS. Extensive use was made of a two-dimensional device model and a one-dimensional process model to determine suitable process parameters. The necessary conditions to produce a high-voltage double-diffused metal oxide semiconductor (DMOS) structure, as well as both n-well and p-well regions for CMOS transistors, and a thick gate oxide required to sustain the full blocking voltage were the main determinants of the process flow. Lateral DMOS (LDMOS), vertical DMOS (VDMOS), conductivity modulated FET (COMFET), and MOS triac (TRIMOS) devices were fabricated on the same chip as standard CMOS transistors using the developed fabrication sequence. This paper includes the results of the process modelling, device design, and electrical measurements.

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Schmitz, A., and R. Tielert. "A new circuit technique for reduced leakage current in Deep Submicron CMOS technologies." Advances in Radio Science 3 (May 13, 2005): 355–58. http://dx.doi.org/10.5194/ars-3-355-2005.

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Abstract. Modern CMOS processes in the Deep Submicron regime are restricted to supply voltages below 2 volts and further to account for the transistors' field strength limitations and to reduce the power per logic gate. To maintain the high switching performance, the threshold voltage must be scaled according with the supply voltage. However, this leads to an increased subthreshold current of the transistors in standby mode (VGS=0). Another source of leakage is gate current, which becomes significant for gate oxides of 3nm and below. We propose a Self-Biasing Virtual Rails (SBVR) - CMOS technique which acts like an adaptive local supply voltage in case of standby mode. Most important sources of leakage currents are reduced by this technique. Moreover, SBVR-CMOS is capable of conserving stored information in sleep mode, which is vital for memory circuits. Memories are exposed to radiation causing soft errors. This well-known problem becomes even worse in standby mode of typical SRAMs, that have low driving performance to withstand alpha particle hits. In this paper, a 16-transistor SRAM cell is proposed, which combines the advantage of extremely low leakage currents with a very high soft error stability.

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Krutchinsky, Sergey, Vasiliy Bespyatov, Alexander Korolev, Eugeniy Zhebrun, and Anton Zolotarev. "Circuitry Design Feature of Stages with High-Gain Coefficient on Field-Effect Transistors." Advanced Materials Research 320 (August 2011): 589–96. http://dx.doi.org/10.4028/www.scientific.net/amr.320.589.

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The feature of implementing of loops with self-compensation of CMOS transistors differential resistance in the gain stages is reviewed. Shown that these compensation loops reduce the parametric sensitivity of the stage and the transistors output capacitance influence on a range of operating frequencies. А set of loops of cancellation of the CMOS transistors parasitic parameters influence on stage cutoff frequency was proposed. The conclusions were made. An example of cost-stage high gain was given.

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Bisht, Uma. "FinFET Response under Radiation and Bias Stress: A Review." International Journal for Research in Applied Science and Engineering Technology 9, no. 9 (September 30, 2021): 76–80. http://dx.doi.org/10.22214/ijraset.2021.37929.

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Abstract: Electronics devices are made on IC’s, the basic building block of these IC’s are transistors. Transistors are continuously upgraded to new forms from conventional BJT to the latest FinFET. The purpose of this paper is to provide a clear and exhaustive understanding of the state of the art, challenges, and future trends of silicon based devices to produced reliable output for a longer time period even in abnormal conditions like in space. The modeling techniques for the conventional transistor, different strategies have been proposed over the last years to model the FinFET behavior and increasing the storage capacity of the IC by increasing the number of transistors without occupying more space on the same IC. The behavior of the device is impacted by radiation, heat, and temperature, by which the overall performance of the devices is affected a lot. Keywords: CMOS, MOSFET, FinFET, diode, transistor, subthreshold voltage, threshold voltage, electromigration, and charge trapping.

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Bhasin, Inderpreet, and Joseph G. Tront. "Block-Level Logic Extraction from CMOS VLSI Layouts." VLSI Design 1, no. 3 (January 1, 1994): 243–59. http://dx.doi.org/10.1155/1994/67035.

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This paper describes a Prolog based Block Extraction System (ProBES) which converts a transistor level description of a CMOS circuit into a logic block level description. The operation of ProBES is conceptually similar to that of a circuit extractor. However, whereas a circuit extractor is used to identify circuit primitives such as transistors, resistors and capacitors from the geometrical information in a mask level layout description, ProBES can be used to identify predefined gates and logic blocks in a CMOS transistor network. ProBES operates according to the circuit hierarchy. Basic gates such as inverters, transmission-gates, nands, nors, etc. are identified first. Logic blocks composed of these gates are then identified. More complex blocks which contain blocks already identified are recognized next and so on. ProBES is meant to be used as an aid in the verification of logic design. It can provide a connectivity check for a circuit.

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Wróblewski, Artur, Christian V. Schimpfle, Otto Schumacher, and Josef A. Nossek. "Minimizing Spurious Switching Activities with Transistor Sizing." VLSI Design 15, no. 2 (January 1, 2002): 537–45. http://dx.doi.org/10.1080/1065514021000012156.

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In combinatorial blocks of static CMOS circuits transistor sizing can be applied for delay balancing as to guarantee synchronously arriving signal slopes at the input of logic gates, thereby avoiding glitches. Since the delay of logic gates depends directly on transistor sizes, their variation allows equalizing different path delays without influencing the total delay of the circuit. Unfortunately, not only the delay, but also power consumption circuits depend on the transistor sizes. To achieve optimal results, transistor lengths have to be increased, which results in both increased gate capacitances and area. Splitting the long transistors counteracts this negative influence.

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Wang, Chua-Chin, Zong-You Hou, Yu-Lin Deng, U.-Fat Chio, and Wei Wang. "2-GHz 2×VDD 28-nm CMOS Digital Output Buffer with Slew Rate Auto-Adjustment Against Process and Voltage Variations." Journal of Circuits, Systems and Computers 29, no. 06 (August 5, 2019): 2050088. http://dx.doi.org/10.1142/s0218126620500887.

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A 2[Formula: see text]VDD CMOS output buffer with process, voltage and leakage (PVL) detection mechanism is proposed such that slew rate is auto-adjusted to reduce the variations at different corners. To boost the driving current, low threshold voltage transistors are used instead of devices with typical threshold voltage in the driving transistor of output stage. More importantly, to prevent large leakage of those large low threshold voltage devices, leakage detection resistors are added at the gates of the always-on low threshold voltage transistors to clamp the leakage. The static power consumption is reduced when it is not activated. Another feature of the proposed design is that the gate-oxide leakage is also reduced by lengthening the driving transistors. Besides, all biases in the proposed design are generated from bandgap circuits such that not only is the variation caused by temperature drifting reduced, the area overhead and power dissipation are also minimized. The proposed design is carried out by using 28-nm CMOS process. The data rate proved by physical measurement is proved to be 2.0[Formula: see text]GHz given 1.8/1.05[Formula: see text]V supply voltage, namely, VDD or 2[Formula: see text]VDD, when the proposed PVL detection as well as the compensation circuitry are activated.

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Kumar, Umesh. "Measurements and Analytical Computer-Based Study of CMOS Inverters and Schmitt Triggers." Active and Passive Electronic Components 19, no. 1 (1996): 41–54. http://dx.doi.org/10.1155/1996/52421.

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Modified CMOS inverters with three and four transistors have been made. Two varieties of CMOS Schmitt Triggers have been considered. CMOS Schmitt Trigger with wide hysteresis has been obtained. Complete detailed theoretical, experimental and computer based results are derived and exhibited.

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40

Tlelo-Cuautle, Esteban, Martín Alejandro Valencia-Ponce, and Luis Gerardo de la Fraga. "Sizing CMOS Amplifiers by PSO and MOL to Improve DC Operating Point Conditions." Electronics 9, no. 6 (June 22, 2020): 1027. http://dx.doi.org/10.3390/electronics9061027.

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The sizes of the metal-oxide-semiconductor (MOS) transistors in an operational amplifier must guarantee strong direct current operating point (DCOP) conditions. This paper shows the usefulness of two population-based optimization algorithms to size transistors, namely—particle swarm optimization (PSO) and many optimizing liaisons (MOL). Both optimization algorithms link the circuit simulator SPICE to measure electrical characteristics. However, SPICE provides an output-file indicating that a transistor is in strong inversion but the DCOP can be in the limit, and it can switch to a different condition. In this manner, we highlight the application of PSO and MOL to size operational transconductance amplifiers (OTAs), which DCOP conditions are improved by the introduction of a procedure that handles constraints to ensure that the transistors are in the appropriate DCOP. The Miller and RFC-OTA are the cases of study, and their sizing is performed using UMC 180 nm CMOS technology. In both OTAs, the objective function is the maximization of the gain-bandwidth product under the main constraint of guaranteeing DCOPs to improve two figures of merit and to provide robustness to Monte Carlo simulations and PVT variations.

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BISDOUNIS, LABROS. "ANALYTICAL MODELING OF OVERSHOOTING EFFECT IN SUB-100 nm CMOS INVERTERS." Journal of Circuits, Systems and Computers 20, no. 07 (November 2011): 1303–21. http://dx.doi.org/10.1142/s0218126611007967.

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Modeling of CMOS inverters and consequently, CMOS gates, is a critical task for improving accuracy and speed of simulation in modern sub-100 nm digital circuits. One of the key factors that determine the operation of a CMOS structure is the influence of the input-to-output coupling capacitance, also called overshooting effect. In this paper, an analytical model for this effect is presented, that computes the time period which is necessary to eliminate the extra output charge transferred through the input-to-output capacitance at the beginning of the switching process in a CMOS inverter. In addition, the maximum or minimum output voltage (depending on the considered edge) is analytically computed. The derived model is based on analytical expressions of the CMOS inverter output voltage waveform, which include the influences of both transistor currents and the input-to-output (gate-to-drain) coupling and load capacitances. An accurate version of the alpha-power law MOSFET model is used to relate the terminal voltages to the drain current in sub-100 nm devices, with an extension for varying transistor widths. The resulting model also accounts for the influences of input voltage transition time, transistors' sizes, as well as device carrier velocity saturation and narrow-width effects. The results produced by the presented model for three sub-100 nm CMOS technologies, several input voltage transition times, capacitive loads and device sizes, show very good agreement with BSIM4 HSPICE simulations.

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POPA, COSMIN. "LOGARITHMICAL CURVATURE-CORRECTED VOLTAGE REFERENCES WITH IMPROVED TEMPERATURE BEHAVIOR." Journal of Circuits, Systems and Computers 18, no. 03 (May 2009): 519–34. http://dx.doi.org/10.1142/s0218126609005253.

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Two voltage reference circuits will be presented. For the first circuit, the linear compensation of V GS (T) for an MOS transistor in subthreshold region will be realized using an original offset voltage follower block as PTAT voltage generator, with the advantages of reducing the silicon area and of increasing accuracy by replacing matched resistors with matched transistors. A new logarithmic curvature-correction technique will be implemented using an asymmetric differential amplifier for compensating the logarithmic temperature dependent term from V GS (T). Because of the operation in weak inversion of all MOS transistors, the circuit will have a very small current consumption, making it compatible with low-power low-voltage designs. The simulated temperature coefficient of the reference voltage for V DD = 2.5 V and a temperature range 0 < t < 30° C is 36.5 ppm/K, confirming the theoretical estimations. The variation of the reference voltage with respect to the supply voltage is 1.5 mV/V for 2–4 V. The circuit current consumption is about 1 μA and the minimal supply voltage is 2 V. The main goal of the second proposed voltage reference is to improve the temperature behavior of a previous reported bipolar voltage reference, by replacing the bipolar transistors with MOS transistors working in weak inversion, with the advantage of obtaining the compatibility with CMOS technology. The new proposed curvature-correction technique will be based on the compensation of the nonlinear temperature dependence of the gate-source voltage for a subthreshold operated MOS transistor by a correction current obtained by taking the difference between two gate-source voltages for MOS transistors biased at drain currents with different temperature dependencies. The circuit is implemented in 0.35 μm CMOS technology. The SPICE simulation confirms the theoretical estimated results, reporting a temperature coefficient of 4.23 ppm/K for the commercial temperature range, 0 < t < 70° C and a small supply voltage, V DD = 2.5 V . The variation of the reference voltage with respect to the supply voltage is 0.9 mV/V for 2–4 V.

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Et.al, M. Naga Gowtham. "Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 3 (April 10, 2021): 3037–45. http://dx.doi.org/10.17762/turcomat.v12i3.1338.

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In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.

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44

K Jeevitha, K Hari Kishore, E Raghuveera, Shaik Razia, M. Naga Gowtham, P. S. Hari Krishna Reddy,. "Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 5 (April 11, 2021): 92–100. http://dx.doi.org/10.17762/turcomat.v12i5.734.

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In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.

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45

DOKIĆ, B. L., and Z. V. BUNDALO. "Regenerative logic circuits with CMOS transistors." International Journal of Electronics 58, no. 6 (June 1985): 907–20. http://dx.doi.org/10.1080/00207218508939086.

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Leland Chang, Yang-Kyu Choi, J. Kedzierski, N. Lindert, Peiqi Xuan, J. Bokor, Chenming Hu, and Tsu-Jae King. "Moore's law lives on [CMOS transistors]." IEEE Circuits and Devices Magazine 19, no. 1 (January 2003): 35–42. http://dx.doi.org/10.1109/mcd.2003.1175106.

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Deferm, L., C. Claeys, and R. Mertens. "Parasitic lateral bipolar transistors in CMOS." Solid-State Electronics 32, no. 2 (February 1989): 103–9. http://dx.doi.org/10.1016/0038-1101(89)90175-5.

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Rao Tirumalasetty, Venkata, C. V. Mohan Krishna, K. Sai Sree Tanmaie, T. Lakshmi Naveena, and Ch Jonathan. "A novel design of high performance1-bit adder circuit at deep sub-micron technology." International Journal of Engineering & Technology 7, no. 1.1 (December 21, 2017): 660. http://dx.doi.org/10.14419/ijet.v7i1.1.10822.

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In this paper, the design of hybrid 1-bit full adder circuit using both pass transistor and CMOS logic was implemented. Performance pa-rameters such as power, delay, and PDP were compared with the existing designs such as complementary pass-transistor logic, transmis-sion gate adder. At 0.4V supply at 22nm technology, the average power consumption is 1. 525 uW was found to be extremely low with moderately low delay 90. 25 ps and PDP found to be 0.137 fJ. The present implementation has very good improvement in terms of delay, power and power delay product when compared to the existing hybrid 1-bit full adders. Also the number of transistors has been reduced to 13 where as the existiing hybrid full adder circuit has 16 transistors. The proposed circuit was implemented using mentor graphics tool in 45nm, 32nm and 22nm technologies with different supply voltages.

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Beg, Azam. "Accurate Calculation of Unreliability of CMOS Logic Cells and Circuits." Journal of Circuits, Systems and Computers 29, no. 13 (February 26, 2020): 2050202. http://dx.doi.org/10.1142/s0218126620502023.

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Modern decananometer-sized MOS transistors tend to exhibit high rates of failure, underscoring the need for accurately estimating the unreliabilities of circuits built from such transistors. This paper presents a methodology for unreliability calculation that extends from individual transistors to complete logic circuits. As a logic cell’s or logic circuit’s unreliability is highly dependent on its transistors’ drain–source and gate–source voltages, SPICE simulations are used to determine the voltages for the individual transistors. The voltage measurements are then utilized by the mathematical equations to predict the unreliabilities with high accuracy. A scalable framework based on the proposed methodology has been successfully implemented. The framework has been validated using ISCAS85 benchmark circuits.

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Biswas, Subrata, Poly Kundu, Md Hasnat Kabir, Sagir Ahmed, and Md Moidul Islam. "Design and Analysis of High Frame Rate Capable Active Pixel Sensor by Using CNTFET Devices for Nanoelectronics." International Journal of Recent Contributions from Engineering, Science & IT (iJES) 3, no. 4 (December 14, 2015): 20. http://dx.doi.org/10.3991/ijes.v3i4.5185.

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This paper presents a high frame rate capable Active Pixel Sensor (APS) using Carbon Nanotube Field Effect Transistor (CNTFET) instead of Complementary Metal Oxide Semiconductor (CMOS). Conventionally, the design of a single APS circuit is based on three transistors (3T) model. In order to achieve higher frame rate, one extra transistor with a column sensor circuit has been introduced in the proposed design to reduce the readout time. This study also concerns about the effect of transistor sizing, bias current, and moreover, the chiral vector of CNTFET. The power consumption and power delay product (PDP) are also investigated for specific sets of reset and row selector signal. Data for these studies were collected with the help of HSPICE software which were further plotted in OriginPro to analyze the optimal operation point of APS circuit. The bias current was also recorded for the readout transistor which is uniquely introduced in the proposed model for achieving better readout time. Hence, the main focus of this paper is to improve the frame rate by reducing the readout time. Results of the proposed CNTFET APS circuit are compared with the conventional CMOS APS circuit. The performance benchmarking shows that CNTFET APS cell significantly reduces readout time, PDP, and thus can achieve much higher frame rate than that of conventional CMOS APS cell.

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Journal articles on the topic 'CMOS Transistors'

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