Relevant bibliographies by topics / CMOS VLSI

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'CMOS VLSI'

Author: Grafiati
Published: 4 June 2021
Last updated: 5 February 2022

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Journal articles on the topic "CMOS VLSI"

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Rajsuman, R. "Iddq testing for CMOS VLSI." Proceedings of the IEEE 88, no. 4 (April 2000): 544–68. http://dx.doi.org/10.1109/5.843000.

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Chen, John Y. "CMOS — The emerging VLSI technology." IEEE Circuits and Devices Magazine 2, no. 2 (March 1986): 16–31. http://dx.doi.org/10.1109/mcd.1986.6311801.

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Sechler, R. F. "Interconnect design with VLSI CMOS." IBM Journal of Research and Development 39, no. 1.2 (January 1995): 23–31. http://dx.doi.org/10.1147/rd.391.0023.

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Sabine, K. A., and H. A. Kemhadjian. "Selective epitaxy for CMOS VLSI." IEEE Electron Device Letters 6, no. 1 (January 1985): 43–46. http://dx.doi.org/10.1109/edl.1985.26036.

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Milovanović, Draeiša P. "Iddq Testing for CMOS VLSI." Microelectronics Journal 26, no. 4 (May 1995): xxiii. http://dx.doi.org/10.1016/0026-2692(95)90074-8.

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Lisenker, Boris, and Yosef Nevo. "CMOS VLSI reliability test model." Microelectronics Reliability 37, no. 1 (January 1997): 115–20. http://dx.doi.org/10.1016/0026-2714(96)00243-0.

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Zhuravleva, I., and Elena Popova. "Technologies for creating radiation-resistant VLSI." Modeling of systems and processes 14, no. 3 (September 22, 2021): 16–22. http://dx.doi.org/10.12737/2219-0767-2021-14-3-16-22.

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The technology of radiation-resistant CMOS VLSI is based on industrial IC technology. The design uses feedback circuits and guard rings to compensate for single effects of cosmic particles (SEE). In most critical cases, these influences in digital circuits lead to single faults (SEU), which temporarily disrupt the state of memory cells, to latching (SEL), and in the long term to a catastrophic change of state. Various space programs confirm great prospects for their use in future space structures. The article discusses the effects of using radiation-resistant CMOS technology, technology based on a silicon-on-sapphire structure, CMOS technology on an insulating substrate taking into account typical characteristics, SIMOX-SOI technology, which consists in separation by implantation of oxygen ions. In new designs of circuits, more advanced algorithms should be implemented for the future.
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Stojcev, Mile. "Analog Design for CMOS VLSI Systems." Microelectronics Journal 34, no. 2 (February 2003): 161. http://dx.doi.org/10.1016/s0026-2692(02)00072-1.

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Myers, D. J., and P. A. Ivey. "A Design Style for VLSI CMOS." IEEE Journal of Solid-State Circuits 20, no. 3 (June 1985): 741–45. http://dx.doi.org/10.1109/jssc.1985.1052376.

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A., SHEHATA, TAHA K., ISMAIL A., and MORSI M. "CMOS LOGIC FAMILIES FOR VLSI DESIGN." International Conference on Aerospace Sciences and Aviation Technology 9, ASAT Conference, 8-10 May 2001 (May 1, 2001): 1–12. http://dx.doi.org/10.21608/asat.2001.31136.

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Dissertations / Theses on the topic "CMOS VLSI"

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Šťastná, Hilda. "Simulace CMOS VLSI obvodů." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2017. http://www.nusl.cz/ntk/nusl-363732.

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This diploma thesis deals with processes of electrical circuits calculations in the last years' worldwide standards like Dymola, MATLAB, Maple or SPICE applications. Circuits calculations are linked with methods for solving linear differential equations, used in this work also by verification of functionality of designed models for CMOS inverter, CMOS NAND, CMOS NOR. Numerical integration method in combination with Taylor series is a suitable method also for parallel calculations of CMOS VLSI circuits. CMOS circuits simulation was implemented with this method in applications in MATLAB language, solving circuits, represented by differential equations. Functionality of the applications was verified by some real examples. Significant acceleration of calculations using Taylor series compared to other methods is an important factor in choosing methods used in circuit simulations.
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Mende, Ole. "Laserumschalterstruktur in CMOS-Technologie." [S.l. : s.n.], 2003. http://deposit.ddb.de/cgi-bin/dokserv?idn=969347189.

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Wang, Guoyu. "CMOS VLSI circuits for imaging." Thesis, University of Edinburgh, 1993. http://hdl.handle.net/1842/13190.

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MOS technology is very attractive for achieving low-cost miniature cameras. It also permits the inclusion of the sensor with other control and processing functions on the same chip. However, this technique has never been developed to the point at which MOS sensor performance matches that of CCD cameras. The objective of this project has been to develop design techniques to achieve single chip video cameras, in unmodified CMOS processes, with improved performance (aimed to match the performance of CCD cameras) and enhanced functionality. In this thesis, following an overview of solid state image sensors, the fundamentals and basic sensor array structure suitable for CMOS implementation is presented. The pixel structure and sensor array, the sense amplifier, scan circuitry, and the output amplifier and buffer are described. Noise analysis is also presented with the main noise sources highlighted and compensation schemes proposed. Other useful on-chip techniques including auto-exposure control, gain control, and data conversion are then discussed. A successfully designed device, named ASIS-1011 which incorporates all these circuit techniques, is finally reported. This design shows that the aim of achieving good picture quality and incorporating sensors and control logic on one chip can be achieved.
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Chung, Chih-Ping. "Setting CMOS environment for VLSI design." Ohio : Ohio University, 1989. http://www.ohiolink.edu/etd/view.cgi?ohiou1182433560.

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Cloutier, Jocelyn. "Layout automatique orienté de circuits CMOS VLSI /." [S.l.] : [s.n.], 1990. http://library.epfl.ch/theses/?nr=875.

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Yang, Hai-Gang. "Timing verification in digital CMOS VLSI design." Thesis, University of Cambridge, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.387095.

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Heim, Pascal. "CMOS analogue VLSI implementation of a kohonen map /." [S.l.] : [s.n.], 1993. http://library.epfl.ch/theses/?nr=1174.

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Mather, Peter James. "Automated performance optimisation of combinational VLSI CMOS structures." Thesis, University of Huddersfield, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.295996.

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Ziesemer, Junior Adriel Mota. "Geração automática de partes operativas de circuitos VLSI." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2007. http://hdl.handle.net/10183/15530.

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Tanto nos circuitos integrados para processamento de sinais digitais quanto em microprocessadores, a parte operativa é o núcleo onde a computação dos dados é realizada. A geração deste bloco costuma ser crítica para o desempenho global dos dispositivos. Ferramentas específicas para a geração de parte operativa costumam tirar proveito da regularidade estrutural do circuito para produzir leiautes mais densos e com melhor desempenho. Este trabalho apresenta um novo fluxo de projeto para geração de parte operativa onde foi desenvolvido um gerador automático de leiaute de células CMOS com suporte à lógica não-complementar e um compilador de parte operativa. O uso destas duas ferramentas permite a rápida prototipação de uma biblioteca inteira de células lógicas otimizadas, para atender diferentes requisitos de desempenho, que em seguida são utilizadas para montagem de cada um dos blocos funcionais da parte operativa pelo compilador. Comparações feitas com a ferramenta de síntese de células lógicas mostraram que a metodologia desenvolvida é capaz de produzir resultados similares em área e tempo de geração que métodos exatos e ainda possui a vantagem de suportar o uso de múltiplas métricas de qualidade durante o posicionamento dos transistores. As células geradas automaticamente apresentaram acréscimo de área médio de apenas 14% quando comparado às standard-cells e com resultado de atraso e consumo de potência muito próximos ou melhores. Circuitos de parte operativa foram gerados automaticamente pelo compilador e apresentaram na média, menor área, consumo de potência e atraso que circuitos gerados com um fluxo de síntese automático para standard-cells.
Datapath is the core where all the computations are performed in circuits for digital signal processing and also in microprocessors. The performance of the whole system is frequently determined by the implementation of the datapath. Tools dedicated for synthesis of this unit are called datapath compilers and use to take advantage on the structural regularity of the circuit to produce dense layouts and with good performance. This work presents a new flow for datapath generation. An automatic cell synthesis tool with support to non-complementary logic is used in conjunction with a datapath compiler to achieve timing optimization and technology independence. The cell library produced as result of the synthesis process is used by the compiler to place the cells and generate each one of the datapath operators. Comparisons with other cell sythesis tools shown that our approach was able to produce results comparable in area and generation time. Automatically generated cells were compared to standard-cell layouts and presented an average area overhead of just 14% while our circuits presented better or very close delay and power consumption. The datapaths produced by the compiler were compared to a traditional standard-cell based synthesis design flow and presented smaller area, delay and power consumption in average than this approach.
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Voysey, Matthew David. "Inexact analogue CMOS neurons for VLSI neural network design." Thesis, University of Southampton, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.264387.

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Books on the topic "CMOS VLSI"

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Kuo, James B., and Ker-Wei Su. CMOS VLSI Engineering. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-2823-1.

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Iddq testing for CMOS VLSI. Boston: Artech House, 1995.

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Uyemura, John P. Circuit Design for CMOS VLSI. Boston, MA: Springer US, 1992.

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Jea-Hong, Luo, ed. Low-voltage CMOS VLSI circuits. New York: Wiley, 1999.

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Uyemura, John P. Circuit Design for CMOS VLSI. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3620-8.

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Circuit design for CMOS VLSI. Boston: Kluwer Academic Publishers, 1992.

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CMOS devices and technology for VLSI. Englewood Cliffs, N.J: Prentice Hall, 1990.

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Roy, Kaushik. Low-power CMOS VLSI circuit design. New York: Wiley, 2000.

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Maloberti, F. Analog design for CMOS VLSI systems. Boston: Kluwer Academic, 2001.

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Analog design for CMOS VLSI systems. Boston: Kluwer Academic Publishers, 2001.

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Book chapters on the topic "CMOS VLSI"

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Chandrasetty, Vikram Arkalgud. "CMOS Digital Design." In VLSI Design, 1–15. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4614-1120-8_1.

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Kuo, James B., and Ker-Wei Su. "SOI CMOS Technology." In CMOS VLSI Engineering, 15–70. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-2823-1_2.

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Kuo, James B., and Ker-Wei Su. "SOI CMOS Circuits." In CMOS VLSI Engineering, 71–120. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-2823-1_3.

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Kuo, James B., and Ker-Wei Su. "Introduction." In CMOS VLSI Engineering, 1–14. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-2823-1_1.

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Kuo, James B., and Ker-Wei Su. "SOI CMOS Devices—Basic." In CMOS VLSI Engineering, 121–206. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-2823-1_4.

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Kuo, James B., and Ker-Wei Su. "SOI CMOS Devices—Advanced." In CMOS VLSI Engineering, 207–306. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-2823-1_5.

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Kuo, James B., and Ker-Wei Su. "SOI-Technology ST-SPICE." In CMOS VLSI Engineering, 307–44. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-2823-1_6.

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Kuo, James B., and Ker-Wei Su. "Special-Purpose SOI." In CMOS VLSI Engineering, 345–414. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-2823-1_7.

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Bellaouar, Abdellatif, and Mohamed I. Elmasry. "VLSI CMOS Subsystem Design." In Low-Power Digital VLSI Design, 409–87. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2355-0_7.

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Uyemura, John P. "Introduction to CMOS." In Circuit Design for CMOS VLSI, 1–20. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3620-8_1.

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Conference papers on the topic "CMOS VLSI"

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Ashouei, Maryam, Adit D. Singh, and Abhijit Chatterjee. "Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS." In 21st International Conference on VLSI Design (VLSID 2008). IEEE, 2008. http://dx.doi.org/10.1109/vlsi.2008.104.

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Gunn, Cary. "Fully Integrated VLSI CMOS and Photonics "CMOS Photonics"." In 2007 IEEE Symposium on VLSI Technology. IEEE, 2007. http://dx.doi.org/10.1109/vlsit.2007.4339680.

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Prasad, Chetan. "Advanced CMOS reliability challenges." In 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA). IEEE, 2014. http://dx.doi.org/10.1109/vlsi-tsa.2014.6839637.

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Prasad, Chetan. "Advanced CMOS reliability challenges." In 2014 International Symposium on VLSI Design, Automation and Test (VLSI-DAT). IEEE, 2014. http://dx.doi.org/10.1109/vlsi-dat.2014.6834931.

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Buss, Dennis D. "Physics of Deep Submicron CMOS VLSI." In PHYSICS OF SEMICONDUCTORS: 27th International Conference on the Physics of Semiconductors - ICPS-27. AIP, 2005. http://dx.doi.org/10.1063/1.1994727.

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Onishi, Imai, Nakamura, Matsubara, Yamada, Tamura, Sakai, and Horiuchi. "A 5-mask CMOS Technology." In Symposium on VLSI Technology. IEEE, 1997. http://dx.doi.org/10.1109/vlsit.1997.623681.

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Sung, Chun-Yung. "Post Si CMOS graphene nanoelectronics." In 2011 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA). IEEE, 2011. http://dx.doi.org/10.1109/vtsa.2011.5872211.

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Itonaga, K. "CMOS image sensor design methodology." In 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA). IEEE, 2013. http://dx.doi.org/10.1109/vlsi-tsa.2013.6545640.

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Livramento, Vinícius Dos Santos, and José Luís Güntzel. "Timing Optimization During the Physical Synthesis of Cell-Based VLSI Circuits." In XXX Concurso de Teses e Dissertações da SBC. Sociedade Brasileira de Computação - SBC, 2017. http://dx.doi.org/10.5753/ctd.2017.3465.

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The evolution of CMOS technology made possible integrated circuits with billions of transistors assembled into a single silicon chip, giving rise to the jargon Very-Large-Scale Integration (VLSI). VLSI circuits span a wide range class of applications, including Application Specific Circuits and Systems-On-Chip. The latter are responsible for fueling the consumer electronics market, especially in the segment of smartphones and tablets, which are responsible for pushing hardware performance requirements every new generation. The required clock frequency affects the performance of a VLSI circuit and induces timing constraints that must be properly handled by synthesis tools. This thesis focuses on techniques for timing closure of cellbased VLSI circuits, i.e. techniques able to iteratively reduce the number of timing violations until the synthesis of the synchronous digital system reaches the specified target frequency.
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Sasagawa, Kiyotaka, Makito Haruta, Yasumi Ohta, Hironari Takehara, and Jun Ohta. "Miniaturized CMOS imaging device for implantable applications." In 2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT). IEEE, 2020. http://dx.doi.org/10.1109/vlsi-dat49148.2020.9196250.

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Reports on the topic "CMOS VLSI"

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Trotter, J. D., and G. S. Prasad. Bulk CMOS VLSI Technology Studies. Part 4. Design of a CMOS Microsequencer. Fort Belvoir, VA: Defense Technical Information Center, June 1985. http://dx.doi.org/10.21236/ada158369.

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Pouliquen, Philippe O., and Mark N. Martin. Latch-Up Detection and Cancellation in CMOS VLSI Circuits. Fort Belvoir, VA: Defense Technical Information Center, June 2000. http://dx.doi.org/10.21236/ada399884.

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Trotter, J. D., and A. K. R. Naini. Bulk CMOS VLSI Technology Studies. Part 1. Scalable CMOS Design Rules. Part 2. CMOS Approaches to PLA (Programmable Logic Array) Design. Fort Belvoir, VA: Defense Technical Information Center, June 1985. http://dx.doi.org/10.21236/ada158367.

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