Relevant bibliographies by topics / CMOS VLSI circuit

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'CMOS VLSI circuit'

Author: Grafiati
Published: 4 June 2021
Last updated: 15 February 2022

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Journal articles on the topic "CMOS VLSI circuit"

1

Kamde, Shilpa, Jitesh Shinde, Sanjay Badjate, and Pratik Hajare. "Comparative Analysis Domino Logic Based Techniques For VLSI Circuit." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 12, no. 8 (2014): 3803–8. http://dx.doi.org/10.24297/ijct.v12i8.2998.

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Domino logic is a CMOS-based evolution of the dynamic logic techniques  based on either PMOS or NMOS transistors. Domino logic technique is widely used in modern digital VLSI circuit. Dynamic logic is twice as fast as static CMOS logic because it uses only N fast transistors. The Dynamic (Domino) logic circuit are often favored in high performance designs because of the high speed and low area advantage.Four different dynamic circuit techniques including Basic domino logic circuit are compared in this paper for low power consumption and speed of domino logic circuits. For digital circui
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Summerfield, S. "Simple multiplexer circuit for CMOS VLSI." Electronics Letters 26, no. 13 (1990): 878. http://dx.doi.org/10.1049/el:19900574.

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Tiwari, Ayush. "Leakage Power Reduction in CMOS VLSI Circuits using Advance Leakage Reduction Method." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (2021): 962–66. http://dx.doi.org/10.22214/ijraset.2021.35065.

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Recently, consumption of power is key problem of logic circuits based on Very Large Scale Integration. More potentiality consumption isn’t considered an appropriate for storage cell life for the use in cell operations and changes parameters such as optimality, efficiency etc, more consumption of power also provides for minimization of cell storage cycle. In present scenario static consumption of power is major troubles in logic circuits based on CMOS. Layout of drainage less circuit is typically complex. Several derived methods for minimization of consumption of potentiality for logic circuits
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Rajaei, Ramin. "A Reliable, Low Power and Nonvolatile MTJ-Based Flip-Flop for Advanced Nanoelectronics." Journal of Circuits, Systems and Computers 27, no. 13 (2018): 1850205. http://dx.doi.org/10.1142/s0218126618502055.

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Very large-scale integrated circuit (VLSI) design faces many challenges with today’s nanometer CMOS technology, including leakage current and reliability issues. Magnetic tunnel junction (MTJ) hybrid with CMOS transistors can offer many advantages for future VLSI design such as high performance, low power consumption, easy integration with CMOS and also nonvolatility. However, MTJ-based logic circuits suffer from a reliability challenge that is the read disturbance issue. This paper proposes a new nonvolatile magnetic flip-flop (MFF) that offers a disturbance-free sensing and a low power write
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Hayward, G., A. Gottlieb, S. Jain, and D. Mahoney. "CMOS VLSI Applications in Broadband Circuit Switching." IEEE Journal on Selected Areas in Communications 5, no. 8 (1987): 1231–41. http://dx.doi.org/10.1109/jsac.1987.1146652.

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Herr, N., and J. J. Barnes. "Statistical Circuit Simulation Modeling of CMOS VLSI." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 5, no. 1 (1986): 15–22. http://dx.doi.org/10.1109/tcad.1986.1270173.

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Williams, R. W. "An undergraduate VLSI CMOS circuit design laboratory." IEEE Transactions on Education 34, no. 1 (1991): 47–51. http://dx.doi.org/10.1109/13.79880.

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Mather, P. J., P. Hallam, and M. Brouwer. "Sensitivity-based CMOS VLSI circuit performance optimisation." Electronics Letters 31, no. 22 (1995): 1918–19. http://dx.doi.org/10.1049/el:19951336.

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Bhasin, Inderpreet, and Joseph G. Tront. "Block-Level Logic Extraction from CMOS VLSI Layouts." VLSI Design 1, no. 3 (1994): 243–59. http://dx.doi.org/10.1155/1994/67035.

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This paper describes a Prolog based Block Extraction System (ProBES) which converts a transistor level description of a CMOS circuit into a logic block level description. The operation of ProBES is conceptually similar to that of a circuit extractor. However, whereas a circuit extractor is used to identify circuit primitives such as transistors, resistors and capacitors from the geometrical information in a mask level layout description, ProBES can be used to identify predefined gates and logic blocks in a CMOS transistor network. ProBES operates according to the circuit hierarchy. Basic gates
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Upadhyay, Shipra, R. A. Mishra, R. K. Nagaria, and S. P. Singh. "DFAL: Diode-Free Adiabatic Logic Circuits." ISRN Electronics 2013 (February 10, 2013): 1–12. http://dx.doi.org/10.1155/2013/673601.

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The manufacturing advances in semiconductor processing (continually reducing minimum feature size of transistors, increased complexity and ever increasing number of devices on a given IC) change the design challenges for circuit designers in CMOS technology. The important challenges are low power high speed computational devices. In this paper a novel low power adiabatic circuit topology is proposed. By removing the diode from the charging and discharging path, higher output amplitude is achieved and also the power dissipation of the diodes is eliminated. A mathematical expression has been dev
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Dissertations / Theses on the topic "CMOS VLSI circuit"

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Madhyastha, Sadhana. "Design of circuit breakers for large area CMOS VLSI circuits." Thesis, McGill University, 1989. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=59551.

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Large-area ICs require adequate defect-tolerance to achieve a reasonable yield. One concern is that the power distribution network is shared by a number of modules, and any single short between the supply (V$ sb{dd}$) and ground can disable all these modules. The object of this thesis is to evaluate the feasibility of incorporating circuit breakers in large area ICs, which provide protection against such defects by disconnecting the defective modules from the array. A critical analysis and comparison of MOS transistors and parasitic bipolar transistors as circuit breakers are carried out. It i
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Šťastná, Hilda. "Simulace CMOS VLSI obvodů." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2017. http://www.nusl.cz/ntk/nusl-363732.

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This diploma thesis deals with processes of electrical circuits calculations in the last years' worldwide standards like Dymola, MATLAB, Maple or SPICE applications. Circuits calculations are linked with methods for solving linear differential equations, used in this work also by verification of functionality of designed models for CMOS inverter, CMOS NAND, CMOS NOR. Numerical integration method in combination with Taylor series is a suitable method also for parallel calculations of CMOS VLSI circuits. CMOS circuits simulation was implemented with this method in applications in MATLAB language
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Hamed, M. M. "Selective growth of silicon with application to CMOS processing." Thesis, University of Southampton, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.384208.

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Li, Xiaojun. "Deep submicron CMOS VLSI circuit reliability modeling, simulation and design." College Park, Md. : University of Maryland, 2005. http://hdl.handle.net/1903/3124.

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Thesis (Ph. D.) -- University of Maryland, College Park, 2005.<br>Thesis research directed by: Mechanical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
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Buchanan, Brent E. "A mixed-signal CMOS VLSI image convolution circuit using error spectrum shaping." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15420.

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Blanchard, Yves. "Conception d'un circuit cmos-vlsi integrant une fonction de correlation numerique." Paris 11, 1991. http://www.theses.fr/1991PA112348.

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Cette these traite de l'implantation sous forme de circuit integre vlsi cmos d'une fonction de traitement de signal utilisee en particulier dans les radars et les sonars: la fonction de correlation. Apres une breve introduction de la fonction, l'integration vlsi est abordee par la presentation de differentes architectures possibles. En cherchant a implanter directement la fonction mathematique, on arrive a une architecture classique a base d'additionneurs, qui, si elle a l'avantage d'etre facile a implanter, a cependant les defauts d'occuper trop de place et de ne pouvoir tenir la frequence so
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Hung, Chung-Chih. "Low voltage, low power CMOS analog circuit design techniques for mobile, portable VLSI applications /." The Ohio State University, 1997. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487943341527253.

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Sulistyo, Jos Budi. "High Speed Circuit Design Based on a Hybrid of Conventional and Wave Pipelining." Diss., Virginia Tech, 2005. http://hdl.handle.net/10919/29091.

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The increasing capabilities of multimedia appliances demand arithmetic circuits with higher speed and reasonable power dissipation. A common technique to attain those goals is synchronous pipelining, which increases the throughput of a circuit at the expense of longer latency, and it is therefore suitable where throughput takes priority over latency. Two synchronous pipelining approaches, conventional pipelining and wave pipelining, are commonly employed. Conventional pipelining uses registers to divide the circuit into shorter paths and synchronize among sub-blocks, while wave pipelining use
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Dandache, Abbas. "Conception de PLA CMOS." Phd thesis, Grenoble 2 : ANRT, 1986. http://catalogue.bnf.fr/ark:/12148/cb37596962j.

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MAL, PROSENJIT. "DESIGN AND DEMONSTRATION OF A MULTI-TECHNOLOGY FIELD PROGRAMMABLE GATE ARRAY ARCHITECTURE." University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1081274672.

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Books on the topic "CMOS VLSI circuit"

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Uyemura, John P. Circuit Design for CMOS VLSI. Springer US, 1992.

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Uyemura, John P. Circuit Design for CMOS VLSI. Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3620-8.

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Circuit design for CMOS VLSI. Kluwer Academic Publishers, 1992.

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Roy, Kaushik. Low-power CMOS VLSI circuit design. Wiley, 2000.

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Money, Harris David, and Weste Neil H. E, eds. CMOS VLSI design: A circuits and systems perspective. 3rd ed. Pearson/Addison-Wesley, 2005.

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Jea-Hong, Luo, ed. Low-voltage CMOS VLSI circuits. Wiley, 1999.

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CMOS nanoelectronics: Analog and RF VLSI circuits. McGraw-Hill, 2011.

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Aswin, Sreedhar, ed. Nanoscale CMOS VLSI circuits: Design for manufacturability. McGraw-Hill, 2010.

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Iddq testing for CMOS VLSI. Artech House, 1995.

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Maloberti, F. Analog design for CMOS VLSI systems. Kluwer Academic, 2001.

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Book chapters on the topic "CMOS VLSI circuit"

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Uyemura, John P. "Analog CMOS Circuits." In Circuit Design for CMOS VLSI. Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3620-8_9.

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Uyemura, John P. "Introduction to CMOS." In Circuit Design for CMOS VLSI. Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3620-8_1.

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Uyemura, John P. "The CMOS Inverter." In Circuit Design for CMOS VLSI. Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3620-8_3.

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Uyemura, John P. "CMOS Switch Logic." In Circuit Design for CMOS VLSI. Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3620-8_5.

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Uyemura, John P. "BiCMOS Circuits." In Circuit Design for CMOS VLSI. Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3620-8_10.

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Sharaf, Khaled M., and Mohamed I. Elmasry. "CMOS High-Performance Circuits." In High-Performance Digital VLSI Circuit Design. Springer US, 1996. http://dx.doi.org/10.1007/978-1-4615-2297-3_4.

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Uyemura, John P. "Static Logic Circuits." In Circuit Design for CMOS VLSI. Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3620-8_4.

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Uyemura, John P. "Design of Basic Circuits." In Circuit Design for CMOS VLSI. Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3620-8_8.

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Uyemura, John P. "MOSFET Characteristics." In Circuit Design for CMOS VLSI. Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3620-8_2.

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Uyemura, John P. "Chip Design." In Circuit Design for CMOS VLSI. Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3620-8_6.

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Conference papers on the topic "CMOS VLSI circuit"

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Livramento, Vinícius Dos Santos, and José Luís Güntzel. "Timing Optimization During the Physical Synthesis of Cell-Based VLSI Circuits." In XXX Concurso de Teses e Dissertações da SBC. Sociedade Brasileira de Computação - SBC, 2017. http://dx.doi.org/10.5753/ctd.2017.3465.

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The evolution of CMOS technology made possible integrated circuits with billions of transistors assembled into a single silicon chip, giving rise to the jargon Very-Large-Scale Integration (VLSI). VLSI circuits span a wide range class of applications, including Application Specific Circuits and Systems-On-Chip. The latter are responsible for fueling the consumer electronics market, especially in the segment of smartphones and tablets, which are responsible for pushing hardware performance requirements every new generation. The required clock frequency affects the performance of a VLSI circuit
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Nandyala, Venkata Ramakrishna, and Kamala Kanta Mahapatra. "A circuit technique for leakage power reduction in CMOS VLSI circuits." In 2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA). IEEE, 2016. http://dx.doi.org/10.1109/vlsi-sata.2016.7593044.

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Zhang, Kevin. "Circuit design in nano-scale CMOS technologies." In 2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA). IEEE, 2018. http://dx.doi.org/10.1109/vlsi-tsa.2018.8403798.

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Zhang, Kevin. "Circuit design in nano-scale CMOS technologies." In 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT). IEEE, 2018. http://dx.doi.org/10.1109/vlsi-dat.2018.8373276.

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Nigam, T. "CMOS reliability: From discrete device degradation to circuit aging." In 2013 International Symposium on VLSI Design, Automation and Test (VLSI-DAT). IEEE, 2013. http://dx.doi.org/10.1109/vldi-dat.2013.6533830.

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Nigam, Tanya. "CMOS reliability: From discrete device degradation to circuit aging." In 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA). IEEE, 2013. http://dx.doi.org/10.1109/vlsi-tsa.2013.6545624.

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Chen, Luis, and C. Patrick Yue. "Adaptive biasing circuit overcoming process variation for high-speed circuits in scaled CMOS technology." In 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT). IEEE, 2008. http://dx.doi.org/10.1109/vdat.2008.4542458.

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Shanbhag, S. S. "CMOS integrated circuit for sensing applications." In 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06). IEEE, 2006. http://dx.doi.org/10.1109/vlsid.2006.61.

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Ghosh, Arpita. "Stability of Hybrid SET-CMOS Based NOT Gate." In 2020 IEEE VLSI Device Circuit and System (VLSI DCS). IEEE, 2020. http://dx.doi.org/10.1109/vlsidcs47293.2020.9179937.

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Schruefer, K., K. von Arnim, C. Pacha, et al. "Circuit Performance of Low-Power Optimized Multi-Gate CMOS Technologies." In 2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA). IEEE, 2007. http://dx.doi.org/10.1109/vtsa.2007.378961.

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Reports on the topic "CMOS VLSI circuit"

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Pouliquen, Philippe O., and Mark N. Martin. Latch-Up Detection and Cancellation in CMOS VLSI Circuits. Defense Technical Information Center, 2000. http://dx.doi.org/10.21236/ada399884.

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