Relevant bibliographies by topics / CMOS VLSI circuit / Dissertations / Theses
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Dissertations / Theses on the topic 'CMOS VLSI circuit'

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Published: 4 June 2021
Last updated: 15 February 2022

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1

Madhyastha, Sadhana. "Design of circuit breakers for large area CMOS VLSI circuits." Thesis, McGill University, 1989. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=59551.

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Large-area ICs require adequate defect-tolerance to achieve a reasonable yield. One concern is that the power distribution network is shared by a number of modules, and any single short between the supply (V$ sb{dd}$) and ground can disable all these modules. The object of this thesis is to evaluate the feasibility of incorporating circuit breakers in large area ICs, which provide protection against such defects by disconnecting the defective modules from the array. A critical analysis and comparison of MOS transistors and parasitic bipolar transistors as circuit breakers are carried out. It i
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2

Šťastná, Hilda. "Simulace CMOS VLSI obvodů." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2017. http://www.nusl.cz/ntk/nusl-363732.

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This diploma thesis deals with processes of electrical circuits calculations in the last years' worldwide standards like Dymola, MATLAB, Maple or SPICE applications. Circuits calculations are linked with methods for solving linear differential equations, used in this work also by verification of functionality of designed models for CMOS inverter, CMOS NAND, CMOS NOR. Numerical integration method in combination with Taylor series is a suitable method also for parallel calculations of CMOS VLSI circuits. CMOS circuits simulation was implemented with this method in applications in MATLAB language
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3

Hamed, M. M. "Selective growth of silicon with application to CMOS processing." Thesis, University of Southampton, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.384208.

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4

Li, Xiaojun. "Deep submicron CMOS VLSI circuit reliability modeling, simulation and design." College Park, Md. : University of Maryland, 2005. http://hdl.handle.net/1903/3124.

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Thesis (Ph. D.) -- University of Maryland, College Park, 2005.<br>Thesis research directed by: Mechanical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
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5

Buchanan, Brent E. "A mixed-signal CMOS VLSI image convolution circuit using error spectrum shaping." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15420.

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6

Blanchard, Yves. "Conception d'un circuit cmos-vlsi integrant une fonction de correlation numerique." Paris 11, 1991. http://www.theses.fr/1991PA112348.

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Cette these traite de l'implantation sous forme de circuit integre vlsi cmos d'une fonction de traitement de signal utilisee en particulier dans les radars et les sonars: la fonction de correlation. Apres une breve introduction de la fonction, l'integration vlsi est abordee par la presentation de differentes architectures possibles. En cherchant a implanter directement la fonction mathematique, on arrive a une architecture classique a base d'additionneurs, qui, si elle a l'avantage d'etre facile a implanter, a cependant les defauts d'occuper trop de place et de ne pouvoir tenir la frequence so
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7

Hung, Chung-Chih. "Low voltage, low power CMOS analog circuit design techniques for mobile, portable VLSI applications /." The Ohio State University, 1997. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487943341527253.

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8

Sulistyo, Jos Budi. "High Speed Circuit Design Based on a Hybrid of Conventional and Wave Pipelining." Diss., Virginia Tech, 2005. http://hdl.handle.net/10919/29091.

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The increasing capabilities of multimedia appliances demand arithmetic circuits with higher speed and reasonable power dissipation. A common technique to attain those goals is synchronous pipelining, which increases the throughput of a circuit at the expense of longer latency, and it is therefore suitable where throughput takes priority over latency. Two synchronous pipelining approaches, conventional pipelining and wave pipelining, are commonly employed. Conventional pipelining uses registers to divide the circuit into shorter paths and synchronize among sub-blocks, while wave pipelining use
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9

Dandache, Abbas. "Conception de PLA CMOS." Phd thesis, Grenoble 2 : ANRT, 1986. http://catalogue.bnf.fr/ark:/12148/cb37596962j.

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10

MAL, PROSENJIT. "DESIGN AND DEMONSTRATION OF A MULTI-TECHNOLOGY FIELD PROGRAMMABLE GATE ARRAY ARCHITECTURE." University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1081274672.

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11

Tarog, Emanuel S. "Design techniques to improve time dependent dielectric breakdown based failure for CMOS circuits." DigitalCommons@CalPoly, 2010. https://digitalcommons.calpoly.edu/theses/229.

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This project investigates the failure of various CMOS circuits as a result of Time Dependent Dielectric Breakdown (TDDB) and explores design techniques to increase the mean time to failure (MTTF) of large-scale circuits. Time Dependent Dielectric Breakdown is a phenomenon where the oxide underneath the gate degrades as a result of the electric field in the material. Currently, there are few well documented design techniques that can increase lifetime, but with a tool chain I created called the MTTF Analyzing Program, or MAP, I was able to test circuits under various conditions in order to ide
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12

Moraes, Fernando Gehm. "Synthese topologique de macro-cellules en technologie cmos." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 1994. http://hdl.handle.net/10183/17853.

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Les problèmes majeurs de la génération automatique du dessin des masques des circuits intégrés sont la dépendance vis-à-vis des règles de dessin et le dimensionnement correct des transistors. Les méthodes traditionnelles, telles que l'utilisation de cellules pré-caractérisées, manquent de flexibilité, car les portes des bibliothèques (en nombre limité) sont dessinées et dimensionnées (independarnment de l'application) pour une technologie donnée. Les méthodes de synthèse automatique du dessin des masques ont pour but de surmonter ces problèmes. Les techniques les plus couramment utilisées sont
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13

Levski, Dimitrov Deyan. "A Cyclic Analog to Digital Converter for CMOS image sensors." Thesis, Linköpings universitet, Elektroniksystem, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-103193.

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The constant strive for improvement of digital video capturing speeds together with power efficiency increase, has lead to tremendous research activities in the image sensor readout field during the past decade. The improvement of lithography and solid-state technologies provide the possibility of manufacturing higher resolution image sensors. A double resolution size-up, leads to a quadruple readout speed requirement, if the same capturing frame rate is to be maintained. The speed requirements of conventional serial readout techniques follow the same curve and are becoming more challenging to
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14

Save, Didier. "Etude et developpement de technologies d'isolation cmos pour circuits integres ulsi." Toulouse 3, 1988. http://www.theses.fr/1988TOU30011.

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L'isolation des circuits cmos est une des cles de leur miniaturisation extreme. Les technologies d'isolation de l'ulsi devront eliminer les risques de courants de fuite et de "latch up" a la peripherie du caisson, ainsi que les phenomenes perimetriques, dus a l'isolation de champ, qui degradent les performances des petits transistors (tension de seuil, capacite de diffusion). L'isolation dielectrique du caisson par tranchee profonde est choisie ici pour sa compatilibite avec les filieres de fabrication existantes. La principale difficulte de la technique reside dans la gravure parfaitement ver
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15

Baschiera, Daniel. "Modélisation de pannes et méthodes de test de circuits intégrés CMOS." Phd thesis, Grenoble INPG, 1986. http://tel.archives-ouvertes.fr/tel-00320020.

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Étude pour des circuits VLSI sur substrat de silicium. Les modèles de pannes développés pour la technologie NMOS ne sont plus adaptes à la vérification des pannes en technologie CMOS. On examine les pannes de type déclenchement parasite, court-circuit, blocage sur et blocage ouvert. Pour chacune de ces pannes un modèle est défini et on détermine les méthodes de vérification correspondantes. Les principaux comportements étudies sont la transformation d'un circuit logique en analogique et la transformation d'un circuit combinatoire en un circuit séquentiel. On démontre un ensemble de lemmes et t
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16

Wang, Guoyu. "CMOS VLSI circuits for imaging." Thesis, University of Edinburgh, 1993. http://hdl.handle.net/1842/13190.

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MOS technology is very attractive for achieving low-cost miniature cameras. It also permits the inclusion of the sensor with other control and processing functions on the same chip. However, this technique has never been developed to the point at which MOS sensor performance matches that of CCD cameras. The objective of this project has been to develop design techniques to achieve single chip video cameras, in unmodified CMOS processes, with improved performance (aimed to match the performance of CCD cameras) and enhanced functionality. In this thesis, following an overview of solid state imag
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17

Cloutier, Jocelyn. "Layout automatique orienté de circuits CMOS VLSI /." [S.l.] : [s.n.], 1990. http://library.epfl.ch/theses/?nr=875.

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18

Yang, Hai-Gang. "Timing verification in digital CMOS VLSI design." Thesis, University of Cambridge, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.387095.

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19

Ziesemer, Junior Adriel Mota. "Geração automática de partes operativas de circuitos VLSI." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2007. http://hdl.handle.net/10183/15530.

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Tanto nos circuitos integrados para processamento de sinais digitais quanto em microprocessadores, a parte operativa é o núcleo onde a computação dos dados é realizada. A geração deste bloco costuma ser crítica para o desempenho global dos dispositivos. Ferramentas específicas para a geração de parte operativa costumam tirar proveito da regularidade estrutural do circuito para produzir leiautes mais densos e com melhor desempenho. Este trabalho apresenta um novo fluxo de projeto para geração de parte operativa onde foi desenvolvido um gerador automático de leiaute de células CMOS com suporte à
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20

Khellah, Muhammad M. "Low-power digital CMOS VLSI circuits and design methodologies." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0007/NQ44771.pdf.

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21

Wang, Fan Agrawal Vishwani D. "Soft error rate determination for nanometer CMOS VLSI circuits." Auburn, Ala, 2008. http://hdl.handle.net/10415/1517.

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22

Zarabadi, Seyed Ramezan. "Design of analog VLSI circuits in BICMOS/CMOS technology /." The Ohio State University, 1992. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487777170407338.

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23

Manetakis, Konstantinos. "Intermediate frequency CMOS analogue cells for wireless communications." Thesis, Imperial College London, 1999. http://hdl.handle.net/10044/1/11275.

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24

Bracey, Mark. "Current domain analogue-to-digital conversion techniques for CMOS VLSI." Thesis, University of Southampton, 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.242618.

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25

Chung, Chih-Ping. "Setting CMOS environment for VLSI design." Ohio : Ohio University, 1989. http://www.ohiolink.edu/etd/view.cgi?ohiou1182433560.

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26

Rogenmoser, Robert. "The design of high-speed dynamic CMOS circuits for VLSI /." Konstanz : Hartung-Gorre, 1996. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=11421.

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27

Voysey, Matthew David. "Inexact analogue CMOS neurons for VLSI neural network design." Thesis, University of Southampton, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.264387.

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28

Aziz, Syed Mahfuzul. "The realisation of high-speed, testable multipliers suitable for synthesis using differential CMOS circuits." Thesis, University of Kent, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.240166.

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29

Rosa, André Luís Rodeghiero. "Projeto de células e circuitos VLSI digitais CMOS para operação em baixa tensão." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/118526.

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Este trabalho propõe uma estratégia para projeto de circuitos VLSI operando em amplo ajuste de tensão e frequência (VFS), desde o regime em Near-threshold, onde uma tensão de VDD caracteriza-se por permitir o funcionamento do circuito com o mínimo dispêndio de energia por operação (MEP), até tensões nominais, dependendo da carga de trabalho exigida pela aplicação. Nesta dissertação é proposto o dimensionamento de transistores para três bibliotecas de células utilizando MOSFETs com tensões de limiar distintas: Regular-VT (RVT), High-VT (HVT) e Low-VT (LVT). Tais bibliotecas possuem cinco célula
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30

Lakshmikanthan, Preetham. "Novel energy-efficient leakage current minimization techniques for CMOS VLSI circuits." Related electronic resource: Current Research at SU : database of SU dissertations, recent titles available full text, 2007. http://wwwlib.umi.com/cr/syr/main.

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31

Bensouiah, Djamel Abderrahmane. "Testability and redundancy techniques for improved yield and reliability of CMOS VLSI circuits." Thesis, Durham University, 1992. http://etheses.dur.ac.uk/6008/.

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The research presented in this thesis is concerned with the design of fault-tolerant integrated circuits as a contribution to the design of fault-tolerant systems. The economical manufacture of very large area ICs will necessitate the incorporation of fault-tolerance features which are routinely employed in current high density dynamic random access memories. Furthermore, the growing use of ICs in safety-critical applications and/or hostile environments in addition to the prospect of single-chip systems will mandate the use of fault-tolerance for improved reliability. A fault-tolerant IC must
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32

Zaveri, Jainish K. "Asic Design of RF Energy Harvester Using 0.13UM CMOS Technology." DigitalCommons@CalPoly, 2018. https://digitalcommons.calpoly.edu/theses/1940.

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Recent advances in wireless sensor nodes, data acquisition devices, wearable and implantable medical devices have paved way for low power (sub 50uW) devices. These devices generally use small solid state or thin film batteries for power supply which need replacement or need to be removed for charging. RF energy harvesting technology can be used to charge these batteries without the need to remove the battery from the device, thus providing a sustainable power supply. In other cases, a battery can become unnecessary altogether. This enables us to deploy wireless network nodes in places where re
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33

Caldeira, Laercio. "Blocos CMOS de alta performance para aplicações em VLSI." [s.n.], 1993. http://repositorio.unicamp.br/jspui/handle/REPOSIP/260420.

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Orientador: Jose Antonio Siqueira Dias<br>Tese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica<br>Made available in DSpace on 2018-07-19T03:44:15Z (GMT). No. of bitstreams: 1 Caldeira_Laercio_D.pdf: 10099585 bytes, checksum: 173e2f6a8ff46de0de4b0b42573529e4 (MD5) Previous issue date: 1993<br>Resumo: Este trabalho integra o projeto de três blocos CMOS digitais de alta performance idealizados para incorporarem CIs VLSI, onde se buscou o melhor compromisso área/velocidade. Um dos blocos, o do Conversor A/D de 8 Bits, desenvolvido em arquitetura "flash" modifica
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Pereira, dos Santos Rodolfo. "Mecanismo de otimização para redução de potência estática de circuitos integrados baseado na técnica Dual-VTH." Universidade Federal de Pernambuco, 2010. https://repositorio.ufpe.br/handle/123456789/2443.

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Made available in DSpace on 2014-06-12T15:58:17Z (GMT). No. of bitstreams: 2 arquivo3360_1.pdf: 1861373 bytes, checksum: da4095d44ee2bf2199c241b47e6516e9 (MD5) license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2010<br>Com o advento de novas tecnologias de fabricação, a complexidade e a capacidade de processamento dos sistemas microeletrônicos tornaram-se cada vez maiores. Contudo devido às tendências de mercado atuais, dispositivos portáteis, alimentados à bateria, estão sendo cada vez mais procurados, de modo que uma demanda de produtos que te
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35

Taris, Thierry. "Conception de circuits radiofréquences en technologie CMOS VLSI sous contrainte de basse tension." Bordeaux 1, 2003. http://www.theses.fr/2003BOR16015.

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Ma thèse intitulée "conception de circuits radiofréquences en technologie CMOS VLSI sous contrainte de faible tension" s'est déroulée au sein du laboratoire IXL de l'Université de bordeaux 1. Elle a permis dans un premier temps de mettre en avant les contraintes de conception induites par le marché de masse des objets sans fil qui sont : la faible consommation, la faible tension d'alimentation, l'utilisation de technologies CMOS VLSI et la nécessité de réaliser des architectures innovantes. Ainsi, s'appuyant au préalable sur une étude théorique et analytique de l'effet de substrat, nous avons
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36

Pancholy, Ashish. "Automated fault diagnosis and empirical validation of fault models in CMOS VLSI circuits." Thesis, McGill University, 1990. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=60420.

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The selection of adequate fault models is crucial to generating tests of high quality for complex digital VLSI circuits. This thesis presents a methodology to perform empirical validation of fault models and to get measures of effectiveness of test sets based on the targeted fault models.<br>The methodology is based on the automated fault diagnosis of test circuits, representative of the class of circuits being studied and designed to capture the characteristics of the fabrication process, cell libraries and CAD tools used in their development.<br>The methodology is applied to study the faulty
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37

Rafeei, Lalleh. "Fast Approximation Framework for Timing and Power Analysis of Ultra-Low-Voltage Circuits." Thesis, Virginia Tech, 2012. http://hdl.handle.net/10919/31678.

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Ultra-Low-Voltage operation, which can be considered an extreme case of voltage scaling, can greatly reduce the power consumption of circuits. Despite the fact that Ultra-Low-Voltage operation has been proven to be very effective by several successful prototypes in recent years, there is no fast, effective, and comprehensive technique for designers to estimate power and delay of a design operating in the Ultra-Low-Voltage region. While some frameworks and mathematical models exist to estimate power or delay, certain limitations exist, such as being applicable to either power or delay, or wit
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38

Naouss, Mohammad. "Conception et exploitation d'un banc d'auto-caractérisation pour la prévision de la fiabilité des circuits numériques programmables." Thesis, Bordeaux, 2016. http://www.theses.fr/2016BORD0159/document.

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Les circuits logiques programmables (FPGA) bénéficient des technologies les plus avancés de noeuds CMOS, afin de répondre aux demandes croissantes de haute performance et de faible puissance des circuits intégrés numériques. Cela les rend sensibles aux différents mécanismes de dégradations à l'échelle nanométrique. Dans cette thèse, nous nous concentrons sur le vieillissements des tables de correspondances (LUT) sur FPGA. L'utilisation de la dernière technologie d'échelle réduite et la flexibilité de l'architecture du FPGA, permettent de développer un nouveau banc de test à faible coût pour év
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39

Elgebaly, Mohamed. "Energy Efficient Design for Deep Sub-micron CMOS VLSIs." Thesis, University of Waterloo, 2005. http://hdl.handle.net/10012/892.

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Over the past decade, low power, energy efficient VLSI design has been the focal point of active research and development. The rapid technology scaling, the growing integration capacity, and the mounting active and leakage power dissipation are contributing to the growing complexity of modern VLSI design. Careful power planning on all design levels is required. This dissertation tackles the low-power, low-energy challenges in deep sub-micron technologies on the architecture and circuit levels. Voltage scaling is one of the most efficient ways for reducing power and energy. For
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40

Estève, Eric. "Etude des éléments parasites et de leur impact sur les performances des circuits CMOS-VLSI." Grenoble 2 : ANRT, 1987. http://catalogue.bnf.fr/ark:/12148/cb37604917j.

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41

Estève, Eric. "Etude des elements parasites et de leur impact sur les performances des circuits cmos-vlsi." Paris 7, 1987. http://www.theses.fr/1987PA077008.

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L'etude des elements parasites (resistances et capacites) a ete faite sur une technologie cmos-2 microns. La structure de test et les mesures obtenues ont permis de degager une modelisation analytique de la resistance de contact, decouplant la resistance d'interface et la resistance due a la repartition du courant au sortir du contact. Des etudes en fonction de la temperature ont permis de valider ce modele. Concernant les capacites, une nouvelle technique de mesure, la methode comparative, a permis d'avoir acces a des capacites de 10**(-13) farads et, associee a des techniques plus classiques
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42

Junqueira, Alexandre Ambrozi. "Risco : microprocessador RISC CMOS de 32 bits." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 1993. http://hdl.handle.net/10183/21530.

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Este trabalho apresenta o estudo, a definição e a simulação elétrica e lógica de um microprocessador CMOS de 32 bits, com arquitetura tipo RISC - o Risco. Dentre as principais características do Risco destacam-se: dados, instruções e endereços são palavras de 32 bits; a unidade de endereçamento é a palavra, permitindo um acesso a 4 Giga palavras (16 Gbytes); a comunição com a memória é feita por um barramento multiplexado de 32 bits para dados e endereços; possui 32 registradores de 32 bits, incluídos nestes o contador de programa, o apontador de pilha, a palavra de status do processador e um
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43

Darlay, François. "Contribution au test des circuits intégrés CMOS : étude du test des pannes stuck-on et stuck-open." Grenoble INPG, 1989. http://www.theses.fr/1989INPG0128.

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Cette thèse traite de la détection des pannes du niveau transistors, pour la technologie CMOS : les pannes de type stuck-on et stuck-open sont considérées<br>Ces pannes confèrent aux circuits CMOS des comportements spécifiques : une panne stuck-on (transistor colle ferme) transforme un circuit logique en circuit analogique, tandis qu'une panne stuck-open (transistor colle ouvert) transforme un circuit séquentiel. Le test de différents types de réseaux logiques est abordé. Nous distinguons les réseaux sans sortance multiple (FOF: Fan-Out Free), à sortance multiple non-reconvergente (NRFO : non-
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44

Ajdari, Bahar. "Laser as a Tool to Study Radiation Effects in CMOS." PDXScholar, 2017. https://pdxscholar.library.pdx.edu/open_access_etds/3769.

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Energetic particles from cosmic ray or terrestrial sources can strike sensitive areas of CMOS devices and cause soft errors. Understanding the effects of such interactions is crucial as the device technology advances, and chip reliability has become more important than ever. Particle accelerator testing has been the standard method to characterize the sensitivity of chips to single event upsets (SEUs). However, because of their costs and availability limitations, other techniques have been explored. Pulsed laser has been a successful tool for characterization of SEU behavior, but to this day,
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45

Mroszczyk, Przemyslaw. "Computation with continuous mode CMOS circuits in image processing and probabilistic reasoning." Thesis, University of Manchester, 2014. https://www.research.manchester.ac.uk/portal/en/theses/computation-with-continuous-mode-cmos-circuits-in-image-processing-and-probabilistic-reasoning(57ae58b7-a08c-4a67-ab10-5c3a3cf70c09).html.

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The objective of the research presented in this thesis is to investigate alternative ways of information processing employing asynchronous, data driven, and analogue computation in massively parallel cellular processor arrays, with applications in machine vision and artificial intelligence. The use of cellular processor architectures, with only local neighbourhood connectivity, is considered in VLSI realisations of the trigger-wave propagation in binary image processing, and in Bayesian inference. Design issues, critical in terms of the computational precision and system performance, are exten
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Alexandrov, Borislav P. "Design methodology for thermal management using embedded thermoelectric devices." Diss., Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/54352.

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The main objectives of this dissertation is to investigate the prospects of embedded thermoelectric devices integrated in a chip package and to develop a design methodology aimed at taking advantage of the on-chip on-demand cooling capabilities of the thermoelectric devices. First a simulation framework is established and validated against experimental results, which helps to study the cooling capabilities of embedded thermoelectric coolers (TEC) in both a transient and steady state. The potential for up to 15°C of total cooling has been shown. The thermal simulation framework allows for rapid
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47

Gómez, Cama José María. "Diseño de moduladores Delta-Sigma en tecnología CMOS-VLSI. Aplicación al desarrollo de circuitos de interfaz para sensores capacitivos." Doctoral thesis, Universitat de Barcelona, 2000. http://hdl.handle.net/10803/1508.

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La tecnología microelectrónica esta entrando a formar parte de la vida cotidiana. Así, además del ordenador PC, tanto en los vehículos, como en las viviendas es difícil encontrar equipos o subsistemas eléctricos que no incluyan algún tipo de circuito integrado para su control.<br/>Aspectos como la automatización de viviendas y edificios se empieza a considerar una cuestión clave para la industria informática. Los cuales se basan en buses de campo. Estos precisan de sensores que le informen del estado de la vivienda, industria, vehículo... que se desea controlar, y actuadores que permitan modif
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48

Berois, Javier Andrés Osinaga. "Interface de controle e monitoramento para circuitos alimentados em alta tensão variável." Universidade de São Paulo, 2017. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-05092017-090653/.

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Nesta dissertação, é apresentado o projeto de uma interface que permite o controle e monitoramento de cargas de alta tensão alimentadas na faixa de 8,5V a 35V. A interface fornece duas funções básicas: a primeira é permitir que circuitos alimentados no domínio dos 5V controlem o chaveamento de transistores de potência PMOS com uma tensão de porta 5V abaixo da tensão de alimentação; a segunda é realizar o monitoramento de sobrecorrentes na carga de alta tensão, alertando, com um sinal de baixa tensão, estas ocorrências. A interface foi projetada e fabricada no processo CMOS XC06 - 0,6µm da XFAB
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49

Nunes, Tulio Ibanez. "Um sistema especialista para verificação de regras de projeto eletrico em circuitos integrados de tecnologia CMOS VLSI." [s.n.], 1991. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259111.

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Orientador: Furio Damiani<br>Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica<br>Made available in DSpace on 2018-07-14T01:23:14Z (GMT). No. of bitstreams: 1 Nunes_TulioIbanez_M.pdf: 5817305 bytes, checksum: 09382b135257f88dc2716b66be0e8f42 (MD5) Previous issue date: 1991<br>Resumo: Este trabalho apresenta os aspectos teóricos e práticos envolvidos na construção de um sistema especialista para verificação de regras elétricas em circuitos integrados de tecnologia CMOS. Inicialmente é feito um estudo sobre os paradigmas e técnicas de construção de si
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50

Choi, Jung Hyun. "Mixed-signal analog-digital circuits design on the pre-diffused digital array using trapezoidal association of transistors." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2001. http://hdl.handle.net/10183/2884.

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The mixed-signal and analog design on a pre-diffused array is a challenging task, given that the digital array is a linear matrix arrangement of minimum-length transistors. To surmount this drawback a specific discipline for designing analog circuits over such array is required. An important novel technique proposed is the use of TAT (Trapezoidal Associations of Transistors) composite transistors on the semi-custom Sea-Of-Transistors (SOT) array. The analysis and advantages of TAT arrangement are extensively analyzed and demonstrated, with simulation and measurement comparisons to equivalent s
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