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Journal articles on the topic 'CMOS VLSI circuit'

Author: Grafiati

Published: 4 June 2021

Last updated: 15 February 2022

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1

Kamde, Shilpa, Jitesh Shinde, Sanjay Badjate, and Pratik Hajare. "Comparative Analysis Domino Logic Based Techniques For VLSI Circuit." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 12, no. 8 (2014): 3803–8. http://dx.doi.org/10.24297/ijct.v12i8.2998.

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Domino logic is a CMOS-based evolution of the dynamic logicÂ techniques Â basedÂ onÂ eitherÂ PMOSÂ orÂ NMOS transistors. Domino logic technique is widely used in modern digital VLSI circuit. Dynamic logic is twice as fast as static CMOS logic because it uses only N fast transistors. The Dynamic (Domino) logic circuit are often favored in high performance designs because of the high speed and low area advantage.Four different dynamic circuit techniques including Basic domino logic circuit are compared in this paper for low power consumption and speed of domino logic circuits. For digital circui

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2

Summerfield, S. "Simple multiplexer circuit for CMOS VLSI." Electronics Letters 26, no. 13 (1990): 878. http://dx.doi.org/10.1049/el:19900574.

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3

Tiwari, Ayush. "Leakage Power Reduction in CMOS VLSI Circuits using Advance Leakage Reduction Method." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (2021): 962–66. http://dx.doi.org/10.22214/ijraset.2021.35065.

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Recently, consumption of power is key problem of logic circuits based on Very Large Scale Integration. More potentiality consumption isn’t considered an appropriate for storage cell life for the use in cell operations and changes parameters such as optimality, efficiency etc, more consumption of power also provides for minimization of cell storage cycle. In present scenario static consumption of power is major troubles in logic circuits based on CMOS. Layout of drainage less circuit is typically complex. Several derived methods for minimization of consumption of potentiality for logic circuits

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Rajaei, Ramin. "A Reliable, Low Power and Nonvolatile MTJ-Based Flip-Flop for Advanced Nanoelectronics." Journal of Circuits, Systems and Computers 27, no. 13 (2018): 1850205. http://dx.doi.org/10.1142/s0218126618502055.

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Very large-scale integrated circuit (VLSI) design faces many challenges with today’s nanometer CMOS technology, including leakage current and reliability issues. Magnetic tunnel junction (MTJ) hybrid with CMOS transistors can offer many advantages for future VLSI design such as high performance, low power consumption, easy integration with CMOS and also nonvolatility. However, MTJ-based logic circuits suffer from a reliability challenge that is the read disturbance issue. This paper proposes a new nonvolatile magnetic flip-flop (MFF) that offers a disturbance-free sensing and a low power write

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5

Hayward, G., A. Gottlieb, S. Jain, and D. Mahoney. "CMOS VLSI Applications in Broadband Circuit Switching." IEEE Journal on Selected Areas in Communications 5, no. 8 (1987): 1231–41. http://dx.doi.org/10.1109/jsac.1987.1146652.

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6

Herr, N., and J. J. Barnes. "Statistical Circuit Simulation Modeling of CMOS VLSI." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 5, no. 1 (1986): 15–22. http://dx.doi.org/10.1109/tcad.1986.1270173.

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7

Williams, R. W. "An undergraduate VLSI CMOS circuit design laboratory." IEEE Transactions on Education 34, no. 1 (1991): 47–51. http://dx.doi.org/10.1109/13.79880.

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8

Mather, P. J., P. Hallam, and M. Brouwer. "Sensitivity-based CMOS VLSI circuit performance optimisation." Electronics Letters 31, no. 22 (1995): 1918–19. http://dx.doi.org/10.1049/el:19951336.

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9

Bhasin, Inderpreet, and Joseph G. Tront. "Block-Level Logic Extraction from CMOS VLSI Layouts." VLSI Design 1, no. 3 (1994): 243–59. http://dx.doi.org/10.1155/1994/67035.

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This paper describes a Prolog based Block Extraction System (ProBES) which converts a transistor level description of a CMOS circuit into a logic block level description. The operation of ProBES is conceptually similar to that of a circuit extractor. However, whereas a circuit extractor is used to identify circuit primitives such as transistors, resistors and capacitors from the geometrical information in a mask level layout description, ProBES can be used to identify predefined gates and logic blocks in a CMOS transistor network. ProBES operates according to the circuit hierarchy. Basic gates

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10

Upadhyay, Shipra, R. A. Mishra, R. K. Nagaria, and S. P. Singh. "DFAL: Diode-Free Adiabatic Logic Circuits." ISRN Electronics 2013 (February 10, 2013): 1–12. http://dx.doi.org/10.1155/2013/673601.

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The manufacturing advances in semiconductor processing (continually reducing minimum feature size of transistors, increased complexity and ever increasing number of devices on a given IC) change the design challenges for circuit designers in CMOS technology. The important challenges are low power high speed computational devices. In this paper a novel low power adiabatic circuit topology is proposed. By removing the diode from the charging and discharging path, higher output amplitude is achieved and also the power dissipation of the diodes is eliminated. A mathematical expression has been dev

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11

Card, H. C., and W. R. Moore. "VLSI DEVICES AND CIRCUITS FOR NEURAL NETWORKS." International Journal of Neural Systems 01, no. 02 (1989): 149–65. http://dx.doi.org/10.1142/s0129065789000062.

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This paper provides a tutorial of various VLSI approaches to synthesizing artificial neural networks as microelectronic systems. The means by which the network learns and the synaptic weights become modified is a central theme in this study. The majority of the presentation is concerned with analog circuit approaches to neurons and synapses, employing CMOS circuits. Also included is recent work towards VLSI in situ learning circuits which implement qualitative approximations to Hebbian learning with economy of transistors. An attempt is also made to anticipate relevant developments in VLSI dev

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12

KILIÇ, RECAI, MUSTAFA ALÇI, UǦUR ÇAM, and HAKAN KUNTMAN. "IMPROVED REALIZATION OF MIXED-MODE CHAOTIC CIRCUIT." International Journal of Bifurcation and Chaos 12, no. 06 (2002): 1429–35. http://dx.doi.org/10.1142/s0218127402005236.

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An improved realization of mixed-mode chaotic circuit which has both autonomous and nonautonomous chaotic dynamics is proposed. Central to this study is inductorless realization of mixed-mode chaotic circuit using FTFN-based inductance simulator. FTFN-based topology used in this realization enables the simulation of ideal floating and grounded inductance. This modification provides an alternative solution to the integration problem of not only mixed-mode chaotic circuit but also other chaotic circuits in the literature using CMOS VLSI technologies. In addition to this major improvement, CFOA-b

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13

Hussain, Inamul, and Saurabh Chaudhury. "CNFET Based Low Power Full Adder Circuit for VLSI Applications." Nanoscience & Nanotechnology-Asia 10, no. 3 (2020): 286–91. http://dx.doi.org/10.2174/2210681209666190220122553.

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Background: The Adder is one of the most prominent building blocks in VLSI circuits and systems. Performance of such systems depends mostly on the performance of the adder cell. The scaling down of devices has been the driving force in technological advances. However, in CMOS technology performance of adder cell decreases as technology node scaled down to deep micron regime. Objective: With the growth of research, new device model has been proposed based on carbon nano tube field effect transistor (CNFET). Therefore, there is a need of full adder cell, which performs sufficiently well in CNFET

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14

Sharma, Suruchi, Santosh Kumar, Alok Kumar Mishra, D. Vaithiyanathan, and Baljit Kaur. "Process, Voltage, and Temperature Aware Analysis of ISCAS C17 Benchmark Circuit." Advanced Science, Engineering and Medicine 12, no. 10 (2020): 1289–95. http://dx.doi.org/10.1166/asem.2020.2707.

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High leakage currents such as sub-threshold leakage, junction leakage, and gate leakage currents have become prominent sources of power consumption in CMOS VLSI circuits due to rapid technology scaling in the nanometer regimen accompanied by supply voltage reduction. Consequently, in the nanometer regime, it is imperative to estimate and reduce leakage capacity. However, this continuous aggressive scaling makes the CMOS circuits more prone to Process, Voltage, and Temperature (PVT) variations at nanometer technologies. This paper explores a systematic analysis of various leakage power reductio

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15

Aylapogu, Pramod Kumar, B. L. V. S. S. Aditya, G. Sony, et al. "Estimation of power and delay in CMOS circuits using LCT." Indonesian Journal of Electrical Engineering and Computer Science 14, no. 2 (2019): 990. http://dx.doi.org/10.11591/ijeecs.v14.i2.pp990-998.

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<p>With a rapid growth in semiconductor Industry, complex applications are being implemented using small size chips, with the use of Complementary Metal Oxide Semi-Conductors (CMOS). With the introduction of new Integrated Circuit (IC) technology, the speed of the circuits has been increased by around 30%. But it was observed that for every two years, the power dissipation of a circuit doubles. The main reason for this power dissipation is leakage currents in the circuit. To reduce these leakage currents, we can reduce the width of the device. In addition to this, we can use lector techn

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16

Lorenzo, Rohit, and Saurabh Chaudhury. "Review of Circuit Level Leakage Minimization Techniques in CMOS VLSI Circuits." IETE Technical Review 34, no. 2 (2016): 165–87. http://dx.doi.org/10.1080/02564602.2016.1162116.

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17

Hatano, H. "Radiation hardened high performance CMOS VLSI circuit designs." IEE Proceedings G Circuits, Devices and Systems 139, no. 3 (1992): 287. http://dx.doi.org/10.1049/ip-g-2.1992.0048.

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18

Chen, Wang‐Jin, and Sung‐Chang Fang. "Maximal power estimation for CMOS VLSI circuit design." Journal of the Chinese Institute of Engineers 22, no. 2 (1999): 251–57. http://dx.doi.org/10.1080/02533839.1999.9670462.

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19

Hatano, Hiroshi, and Katsuyuki Doi. "Radiation-Tolerant High-Performance CMOS VLSI Circuit Design." IEEE Transactions on Nuclear Science 32, no. 6 (1985): 4031–35. http://dx.doi.org/10.1109/tns.1985.4334063.

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20

Lopez-Martin, Antonio J., and Alfonso Carlosena. "Design of MOS-translinear Multiplier/Dividers in Analog VLSI." VLSI Design 11, no. 4 (2000): 321–29. http://dx.doi.org/10.1155/2000/21852.

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A general framework for designing current-mode CMOS analog multiplier/divider circuits based on the cascade connection of a geometric-mean circuit and a squarer/divider is presented. It is shown how both building blocks can be readily obtained from a generic second-order MOS translinear loop. Various implementations are proposed, featuring simplicity, favorable precision and wide dynamic range. They can be successfully employed in a wide range of analog VLSI processing tasks. Experimental results of two versions, based on stacked and folded MOS-translinear loops and fabricated in a 2.4-μm CMOS

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21

García, José C., Juan A. Montiel-Nelson, and Saeid Nooshabadi. "Versatile CMOS Current Conveyor for Digital VLSI Systems with Low-Voltage Power Supply." Journal of Low Power Electronics 15, no. 3 (2019): 323–28. http://dx.doi.org/10.1166/jolpe.2019.1617.

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A low voltage supply CMOS current conveyor circuit for digital input signals from 0.25 V up to 1.2 V is presented. The circuit is optimized and pre-layout simulated in a 65 nm CMOS process technology. At the target design voltage of 1.2 V, the current conveyor has a propagation delay of 2.86 ns, an energy consumption of only 80.9 pJ, and energy-delay product (EDP) of 231 pJns for resistive load of 10 kΩ. Superior performance of this work is demonstrated through comparison with other similar published work at a frequency of 5 MHz. It is shown that the proposed circuit is suitable for digital si

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22

SELLAMI, L., S. K. SINGH, R. W. NEWCOMB, A. RASMUSSEN, and M. E. ZAGHLOUL. "VLSI FLOATING RESISTORS FOR NEURAL TYPE CELL ARRAYS." Journal of Circuits, Systems and Computers 08, no. 05n06 (1998): 559–69. http://dx.doi.org/10.1142/s0218126698000353.

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Two novel CMOS circuit designs implementing floating resistors are introduced, using the structure of a two-transistor CMOS bilateral linear resistor in the first configuration and two two-transistor CMOS bilateral linear resistors and cascode current mirrors in the second configuration. Linearity is achieved through nonlinearity cancellation via current mirrors over an applied range of ±5V. PSpice simulation results using parameters of MOSIS transistors are presented to verify the theory. These floating resistors can be used for coupling weights in VLSI neural-type cell arrays.

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23

Kumar, Aylapogu Pramod, B. L. V. S. S. Aditya, G. Sony, Ch Prasanna, and A. Satish. "Estimation of Power and Delay in CMOS Circuits using Leakage Control Transistor." Carpathian Journal of Electronic and Computer Engineering 11, no. 2 (2018): 25–28. http://dx.doi.org/10.2478/cjece-2018-0014.

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Abstract With a rapid growth in semiconductor Industry, complex applications are being implemented using small size chips, with the use of Complementary Metal Oxide Semi-Conductors (CMOS). With the introduction of new Integrated Circuit (IC) technology, the speed of the circuits has been increased by around 30%. But it was observed that for every two years, the power dissipation of a circuit doubles. The main reason for this power dissipation is leakage currents in the circuit. To reduce these leakage currents, we can reduce the width of the device. In addition to this, we can use lector techn

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24

Swanson, J. G. "VLSI Design at the Undergraduate Level." International Journal of Electrical Engineering & Education 24, no. 4 (1987): 309–18. http://dx.doi.org/10.1177/002072098702400403.

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This paper describes the experience gained in teaching a VLSI design course to students in the final year of a three-year course in Electronic Engineering. Each of the twenty students designed and tested their own full-custom CMOS integrated circuit within one academic year.

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25

Герасимов, Ю. М., Н. Г. Григорьев, А. В. Кобыляцкий, Я. Я. Петричкович та Д. К. Сергеев. "ОСОБЕННОСТИ ПРОЕКТИРОВАНИЯ СБОЕУСТОЙЧИВЫХ СВЕРХБЫСТРОДЕЙСТВУЮЩИХ ЛОГИЧЕСКИХ ЦЕПЕЙ КМОП СБИС СНК". NANOINDUSTRY Russia 96, № 3s (2020): 220–28. http://dx.doi.org/10.22184/1993-8578.2020.13.3s.220.228.

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Проанализированы асимптотические параметры быстродействия нанометровых (суб-100 нм) КМОП-технологий объемного кремния (ОК) уровня 90-28 нм. Показано, что сбоеустойчивость логических цепей при воздействии отдельных ядерных частиц (ОЯЧ) зависит от частоты синхронизации СБИС и ухудшается при ее повышении. Даны рекомендации по проектированию сбоеустойчивых быстродействующих логических цепей в составе СБИС типа «система на кристалле» (СнК). The paper deals with asymptotic performance parameters of nanometer-CMOS technologies at a level of90-28 nm. It is shown that the single nuclear particle tolera

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26

Guggenmos, X., and R. Holzner. "A new ESD protection concept for VLSI CMOS circuits avoiding circuit stress." Journal of Electrostatics 29, no. 1 (1992): 21–39. http://dx.doi.org/10.1016/0304-3886(92)90004-d.

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27

Sharma, Vijay Kumar. "Design of Low Leakage PVT Variations Aware CMOS Bootstrapped Driver Circuit." Journal of Circuits, Systems and Computers 26, no. 09 (2017): 1750137. http://dx.doi.org/10.1142/s0218126617501377.

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This paper describes a novel complementary metal oxide semiconductor (CMOS) bootstrapped driver circuit for driving large resistive capacitive (RC) loads. The proposed bootstrapped driver reduces the leakage as well as process, voltage and temperature (PVT) variations from the boosted nodes with higher switching speed. Very large scale integration (VLSI) designers need boosted output for the logic circuits which are operating in ultra-deep submicron regime under widespread use of low voltage. Proposed CMOS bootstrapped driver circuit is easy in design; built with minimum number of transistors

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28

Sasipriya, P., and V. S. Kanchana Bhaaskaran. "Design of Low Power VLSI Circuits Using Two Phase Adiabatic Dynamic Logic (2PADL)." Journal of Circuits, Systems and Computers 27, no. 04 (2017): 1850052. http://dx.doi.org/10.1142/s0218126618500524.

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This paper presents the quasi-adiabatic logic for low power powered by two phase sinusoidal clock signal. The proposed logic called two phase adiabatic dynamic logic (2PADL) realizes the advantages of energy efficiency through the use of gate overdrive and reduced switching power. It has a single rail output and the proposed logic does not require the complementary input signals for any of its variables. The 2PADL logic is operated by two complementary clock signals acting as power supply. The validation of the proposed logic is carried out through practical circuits such as (i) sequential cir

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29

Sharma, Vijay Kumar, and Manisha Pattanaik. "VLSI scaling methods and low power CMOS buffer circuit." Journal of Semiconductors 34, no. 9 (2013): 095001. http://dx.doi.org/10.1088/1674-4926/34/9/095001.

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30

Najm, Farid N., and Michael G. Xakellis. "Statistical Estimation of the ,Switching Activity in VLSI Circuits." VLSI Design 7, no. 3 (1998): 243–54. http://dx.doi.org/10.1155/1998/46819.

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Higher levels of integration have led to a generation of integrated circuits for which power dissipation and reliability are major design concerns. In CMOS circuits, both of these problems are directly related to the extent of circuit switching activity. The average number of transitions per second at a circuit node is a measure of switching activity that has been called the transition density. This paper presents a statistical simulation technique to estimate individual node transition densities in combinational logic circuits. The strength of this approach is that the desired accuracy and co

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31

Tanveer, Adil. "Estimation of Delay to Consider Leakage in CMOS VLSI Circuit." SMART MOVES JOURNAL IJOSCIENCE 4, no. 11 (2018): 7. http://dx.doi.org/10.24113/ijoscience.v4i11.205.

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In digital CMOS circuits, parametric yield improvement may be achieved by reducing the variability of performance and power consumption of individual cell instances. In recent years, increasing demand of portable digital systems has led to rapid and innovative development in the field of low power design. Such improvement of variation robustness can be attained by evaluating parameter variation impact at gate level. Statistical characterization of logic gates are usually obtained by computationally expensive electrical simulations. An efficient gate delay variability estimation method is propo

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32

Ming-Dou Ker, Chung-Yu Wu, and Hun-Hsien Chang. "Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI." IEEE Transactions on Electron Devices 43, no. 4 (1996): 588–98. http://dx.doi.org/10.1109/ted.1996.1210725.

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33

Wairya, Subodh, Rajendra Kumar Nagaria, and Sudarshan Tiwari. "Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design." VLSI Design 2012 (April 4, 2012): 1–18. http://dx.doi.org/10.1155/2012/173079.

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This paper presents a comparative study of high-speed and low-voltage full adder circuits. Our approach is based on hybrid design full adder circuits combined in a single unit. A high performance adder cell using an XOR-XNOR (3T) design style is discussed. This paper also discusses a high-speed conventional full adder design combined with MOSCAP Majority function circuit in one unit to implement a hybrid full adder circuit. Moreover, it presents low-power Majority-function-based 1-bit full addersthat use MOS capacitors (MOSCAP) in its structure. This technique helps in reducing power consumpti

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34

Krishna, B. T., and Shaik mohaseena Salma. "A Flux Controlled Memristor using 90nm Technology." Indian Journal of Signal Processing 1, no. 2 (2021): 1–6. http://dx.doi.org/10.35940/ijsp.b1004.051221.

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A flux-controlled memristor using complementary metal–oxide–(CMOS) structure is presented in this study. The proposed circuit provides higher power efficiency, less static power dissipation, lesser area, and can also reduce the power supply by using CMOS 90nm technology. The circuit is implemented based on the use of a second-generation current conveyor circuit (CCII) and operational transconductance amplifier (OTA) with few passive elements. The proposed circuit uses a current-mode approach which improves the highfrequency performance. The reduction of a power supply is a crucial aspect to de

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NG, K. W., and K. T. LAU. "AN ADIABATIC 4:2 COMPRESSOR DESIGN FOR LOW POWER VLSI." Journal of Circuits, Systems and Computers 09, no. 05n06 (1999): 339–46. http://dx.doi.org/10.1142/s021812669900027x.

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4:2 compressors are basic components in the design of parallel multipliers. Low power consuming 4:2 compressors can result in a significant reduction of power when realizing power-efficient multipliers in any low power oriented systems. In the area of low power integrated circuit design, adiabatic switching technique has received considerable attention in the recent years. Many adiabatic logic architectures have been reported. In this letter, a low power 4:2 compressor circuit based on the adiabatic switching principle is proposed. When simulated using HSPICE, it was shown that the proposed ci

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36

Hari Kishore, K., K. DurgaKoteswara Rao, G. Manvith, K. Biswanth, and P. Alekhya. "Area, power and delay efficient 2-bit magnitude comparator using modified gdi technique in tanner 180nm technology." International Journal of Engineering & Technology 7, no. 2.8 (2018): 222. http://dx.doi.org/10.14419/ijet.v7i2.8.10413.

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Of late, low power configuration took shape into the mostimportant concentrations in designing the latest VLSI circuits. By considering the same at the maximum priority, another outline of two-bit GDI based Magnitude or Digital Comparator are recommended and actualized with the assistance of Modified GDI transistors. Comparators are building blocks in advanced VLSI configuration circuits. In the current patterns the necessity for occupying less area in chip and low power compact devices. In this paper we introduced another Magnitude Comparator which willutilize low power, and gives a quick res

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Kaur, Maninder, and Jasdeep Kaur. "IDDQ Testing of Low Voltage CMOS Operational Transconductance Amplifier." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 3 (2018): 1467. http://dx.doi.org/10.11591/ijece.v8i3.pp1467-1477.

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The paper describes the design for testability (DFT) of low voltage two stage operational transconductance amplifiers based on quiescent power supply current (IDDQ) testing. IDDQ testing refers to the integral circuit testing method based upon measurement of steady state power supply current for testing both digital as well as analog VLSI circuit. A built in current sensor, which introduces insignificant performance degradation of the circuit-under-test, has been proposed to monitor the power supply quiescent current changes in the circuit under test. Moreover, the BICS requires neither an ext

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Singh, Anil, Ayushi Goel, and Alpana Agarwal. "A Digital-Based Low-Power Fully Differential Comparator." Journal of Circuits, Systems and Computers 26, no. 01 (2016): 1750002. http://dx.doi.org/10.1142/s0218126617500025.

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Low-power circuits are highly in demand in this power-hungry world of batteries and portable devices. Though many low-power techniques are prevalent at various stages of a VLSI design cycle, but most of them have retained their own domain. A novel, digital-in-concept, fully differential voltage comparator circuit has been implemented in this paper. This provides substantial reduction in the power consumption. It is highly cost-effective, both in terms of time and efforts as an analog circuit is being designed on digital basis. The proposed voltage comparator has been designed and simulated in

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39

De, Bishnu Prasad, Kanchan Baran Maji, Rajib Kar, Durbadal Mandal, and Sakti Prasad Ghoshal. "Design of Optimal CMOS Analog Amplifier Circuits Using a Hybrid Evolutionary Optimization Technique." Journal of Circuits, Systems and Computers 27, no. 02 (2017): 1850029. http://dx.doi.org/10.1142/s0218126618500299.

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This paper proposes an efficient design technique for two commonly used VLSI circuits, namely, CMOS current mirror load-based differential amplifier circuit and CMOS two-stage operational amplifier. The hybrid evolutionary method utilized for these optimal designs is random particle swarm optimization with differential evolution (RPSODE). Random PSO utilizes the weighted particles for monitoring the search directions. DE is a robust evolutionary technique. It has demonstrated an exclusive performance for the optimization problems which are continuous and global but suffers from the uncertainty

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40

Julian, P., A. G. Andreou, and D. H. Goldberg. "A low-power correlation-derivative CMOS VLSI circuit for bearing estimation." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14, no. 2 (2006): 207–12. http://dx.doi.org/10.1109/tvlsi.2005.863740.

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Segura, J., M. Roca, A. Rubio, and D. Mateo. "Built-in dynamic current sensor circuit for digital VLSI CMOS testing." Electronics Letters 30, no. 20 (1994): 1668–69. http://dx.doi.org/10.1049/el:19941168.

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42

Kassa, Sankit, Neeraj Misra, and Rajendra Nagaria. "Forced stack sleep transistor (FORTRAN): A new leakage current reduction approach in CMOS based circuit designing." Facta universitatis - series: Electronics and Energetics 34, no. 2 (2021): 259–80. http://dx.doi.org/10.2298/fuee2102259k.

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Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design

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Sharma, Anjali, Harsh Sohal, and Harsimran Jit Kaur. "Sleepy CMOS-Sleepy Stack (SC-SS): A Novel High Speed, Area and Power Efficient Technique for VLSI Circuit Design." Journal of Circuits, Systems and Computers 28, no. 12 (2019): 1950197. http://dx.doi.org/10.1142/s0218126619501974.

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This paper presents a novel ultra-low-power Sleepy CMOS-Sleepy Stack (SC-SS) technique for nano scale VLSI technologies. Eight prior techniques are taken for comparison with proposed technique on 65[Formula: see text]nm technology. All the techniques are applied on four benchmark circuits: XOR gate, 1-bit adder, 1-bit comparator and 4-bit up-down counter for measurement of area consumption and total power dissipation. The proposed SC-SS technique achieved very high power efficiency as compared to Complementary CMOS technique (CCT), Dual sleep Technique (DST), Forced stack technique (FST), Slee

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Kanazawa, Yusuke, Tetsuya Asai, and Yoshihito Amemiya. "Basic Circuit Design of a Neural Processor: Analog CMOS Implementation of Spiking Neurons and Dynamic Synapses." Journal of Robotics and Mechatronics 15, no. 2 (2003): 208–18. http://dx.doi.org/10.20965/jrm.2003.p0208.

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We discuss the integration architecture of spiking neurons, predicted to be next-generation basic circuits of neural processor and dynamic synapse circuits. A key to development of a brain-like processor is to learn from the brain. Learning from the brain, we try to develop circuits implementing neuron and synapse functions while enabling large-scale integration, so large-scale integrated circuits (LSIs) realize functional behavior of neural networks. With such VLSI, we try to construct a large-scale neural network on a single semiconductor chip. With circuit integration now reaching micron le

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BISDOUNIS, L., D. GOUVETAS, and O. KOUFOPAVLOU. "A comparative study of CMOS circuit design styles for low-power high-speed VLSI circuits." International Journal of Electronics 84, no. 6 (1998): 599–613. http://dx.doi.org/10.1080/002072198134454.

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GHANAVTI, BEHZAD, and GHOLAMREZA SHOMALNASAB. "DESIGN OF A VLSI HAMMING NEURAL NETWORK FOR ARRHYTHMIA CLASSIFICATION." Journal of Circuits, Systems and Computers 18, no. 04 (2009): 825–39. http://dx.doi.org/10.1142/s0218126609005381.

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The implantable cardioverter defibrillators (ICDs) detect and treat dangerous cardiac arrhythmia. This paper describes a VLSI neural network chip to be implemented using 0.35 μ CMOS technology which acts as an intercardia tachycardia classification system. The Hamming network used to classify non binary input pattern and also reduce impact of noise, drift and offset inherent in analog application. Simulation result using HSPICE and level 49 parameters (BSIM3V3) that verify the functionality of circuit are presented.

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Srinivasulu, Avireni, and Madugula Rajesh. "ULPD and CPTL Pull-Up Stages for Differential Cascode Voltage Switch Logic." Journal of Engineering 2013 (2013): 1–5. http://dx.doi.org/10.1155/2013/595296.

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Two new structures for Differential Cascode Voltage Switch Logic (DCVSL) pull-up stage are proposed. In conventional DCVSL structure, low-to-high propagation delay is larger than high-to-low propagation delay this could be brought down by using DCVSL-R. Promoting resistors in DCVSL-R structure increase the parasitic effects and unavoidable delay and it also occupies more area on the chip (Turker et al., 2011). In order to minimize these problems, a new Ultra-Low-Power Diode (ULPD) structures in place of resistors have been suggested. This provides the minimum parasitic effects and reduces area

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Vahabi, Mohsen, Pavel Lyakhov, and Ali Newaz Bahar. "Design and Implementation of Novel Efficient Full Adder/Subtractor Circuits Based on Quantum-Dot Cellular Automata Technology." Applied Sciences 11, no. 18 (2021): 8717. http://dx.doi.org/10.3390/app11188717.

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One of the emerging technologies at the nanoscale level is the Quantum-Dot Cellular Automata (QCA) technology, which is a potential alternative to conventional CMOS technology due to its high speed, low power consumption, low latency, and possible implementation at the atomic and molecular levels. Adders are one of the most basic digital computing circuits and one of the main building blocks of VLSI systems, such as various microprocessors and processors. Many research studies have been focusing on computable digital computing circuits. The design of a Full Adder/Subtractor (FA/S), a composite

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Kushwah, Preeti, Saurabh Khandelwal, and Shyam Akashe. "Multi-Threshold Voltage CMOS Design for Low-Power Half Adder Circuit." International Journal of Nanoscience 14, no. 05n06 (2015): 1550022. http://dx.doi.org/10.1142/s0219581x15500222.

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The new era of portable electronic devices demands lesser power dissipation for longer battery life and design compactability. Leakage current and leakage power are dominating factors which greatly affect the power consumption in low voltage and low power applications. For many numerical representations of binary numbers, combinational circuits like adder, encoder, multiplexer, etc. are useful circuits for arithmetic operation. A novel high speed and low power half adder cell is introduced here which consists of AND gate and OR gate. This cell shows high speed, lower power consumption than con

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Priyanka, M. Sahithi, G. Manikanta, K. Bhaskar, A. Ganesh, and V. Swetha. "High Performance and Low power VLSI CMOS Circuit Designs using ONOFIC Approach." International Journal of Engineering Research and Applications 07, no. 03 (2017): 71–76. http://dx.doi.org/10.9790/9622-0703067176.

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