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Šťastná, Hilda. "Simulace CMOS VLSI obvodů." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2017. http://www.nusl.cz/ntk/nusl-363732.
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This diploma thesis deals with processes of electrical circuits calculations in the last years' worldwide standards like Dymola, MATLAB, Maple or SPICE applications. Circuits calculations are linked with methods for solving linear differential equations, used in this work also by verification of functionality of designed models for CMOS inverter, CMOS NAND, CMOS NOR. Numerical integration method in combination with Taylor series is a suitable method also for parallel calculations of CMOS VLSI circuits. CMOS circuits simulation was implemented with this method in applications in MATLAB language, solving circuits, represented by differential equations. Functionality of the applications was verified by some real examples. Significant acceleration of calculations using Taylor series compared to other methods is an important factor in choosing methods used in circuit simulations.
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Mende, Ole. "Laserumschalterstruktur in CMOS-Technologie." [S.l. : s.n.], 2003. http://deposit.ddb.de/cgi-bin/dokserv?idn=969347189.
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Wang, Guoyu. "CMOS VLSI circuits for imaging." Thesis, University of Edinburgh, 1993. http://hdl.handle.net/1842/13190.
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MOS technology is very attractive for achieving low-cost miniature cameras. It also permits the inclusion of the sensor with other control and processing functions on the same chip. However, this technique has never been developed to the point at which MOS sensor performance matches that of CCD cameras. The objective of this project has been to develop design techniques to achieve single chip video cameras, in unmodified CMOS processes, with improved performance (aimed to match the performance of CCD cameras) and enhanced functionality. In this thesis, following an overview of solid state image sensors, the fundamentals and basic sensor array structure suitable for CMOS implementation is presented. The pixel structure and sensor array, the sense amplifier, scan circuitry, and the output amplifier and buffer are described. Noise analysis is also presented with the main noise sources highlighted and compensation schemes proposed. Other useful on-chip techniques including auto-exposure control, gain control, and data conversion are then discussed. A successfully designed device, named ASIS-1011 which incorporates all these circuit techniques, is finally reported. This design shows that the aim of achieving good picture quality and incorporating sensors and control logic on one chip can be achieved.
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Chung, Chih-Ping. "Setting CMOS environment for VLSI design." Ohio : Ohio University, 1989. http://www.ohiolink.edu/etd/view.cgi?ohiou1182433560.
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Cloutier, Jocelyn. "Layout automatique orienté de circuits CMOS VLSI /." [S.l.] : [s.n.], 1990. http://library.epfl.ch/theses/?nr=875.
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Yang, Hai-Gang. "Timing verification in digital CMOS VLSI design." Thesis, University of Cambridge, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.387095.
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Heim, Pascal. "CMOS analogue VLSI implementation of a kohonen map /." [S.l.] : [s.n.], 1993. http://library.epfl.ch/theses/?nr=1174.
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Mather, Peter James. "Automated performance optimisation of combinational VLSI CMOS structures." Thesis, University of Huddersfield, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.295996.
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Ziesemer, Junior Adriel Mota. "Geração automática de partes operativas de circuitos VLSI." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2007. http://hdl.handle.net/10183/15530.
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Tanto nos circuitos integrados para processamento de sinais digitais quanto em microprocessadores, a parte operativa é o núcleo onde a computação dos dados é realizada. A geração deste bloco costuma ser crítica para o desempenho global dos dispositivos. Ferramentas específicas para a geração de parte operativa costumam tirar proveito da regularidade estrutural do circuito para produzir leiautes mais densos e com melhor desempenho. Este trabalho apresenta um novo fluxo de projeto para geração de parte operativa onde foi desenvolvido um gerador automático de leiaute de células CMOS com suporte à lógica não-complementar e um compilador de parte operativa. O uso destas duas ferramentas permite a rápida prototipação de uma biblioteca inteira de células lógicas otimizadas, para atender diferentes requisitos de desempenho, que em seguida são utilizadas para montagem de cada um dos blocos funcionais da parte operativa pelo compilador. Comparações feitas com a ferramenta de síntese de células lógicas mostraram que a metodologia desenvolvida é capaz de produzir resultados similares em área e tempo de geração que métodos exatos e ainda possui a vantagem de suportar o uso de múltiplas métricas de qualidade durante o posicionamento dos transistores. As células geradas automaticamente apresentaram acréscimo de área médio de apenas 14% quando comparado às standard-cells e com resultado de atraso e consumo de potência muito próximos ou melhores. Circuitos de parte operativa foram gerados automaticamente pelo compilador e apresentaram na média, menor área, consumo de potência e atraso que circuitos gerados com um fluxo de síntese automático para standard-cells.Datapath is the core where all the computations are performed in circuits for digital signal processing and also in microprocessors. The performance of the whole system is frequently determined by the implementation of the datapath. Tools dedicated for synthesis of this unit are called datapath compilers and use to take advantage on the structural regularity of the circuit to produce dense layouts and with good performance. This work presents a new flow for datapath generation. An automatic cell synthesis tool with support to non-complementary logic is used in conjunction with a datapath compiler to achieve timing optimization and technology independence. The cell library produced as result of the synthesis process is used by the compiler to place the cells and generate each one of the datapath operators. Comparisons with other cell sythesis tools shown that our approach was able to produce results comparable in area and generation time. Automatically generated cells were compared to standard-cell layouts and presented an average area overhead of just 14% while our circuits presented better or very close delay and power consumption. The datapaths produced by the compiler were compared to a traditional standard-cell based synthesis design flow and presented smaller area, delay and power consumption in average than this approach.
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Voysey, Matthew David. "Inexact analogue CMOS neurons for VLSI neural network design." Thesis, University of Southampton, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.264387.
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Khellah, Muhammad M. "Low-power digital CMOS VLSI circuits and design methodologies." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0007/NQ44771.pdf.
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Ngole, Jey E. E. "Correlation-based networks for implementaion in CMOS analogue VLSI." Thesis, University of Newcastle Upon Tyne, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.260083.
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Wang, Fan Agrawal Vishwani D. "Soft error rate determination for nanometer CMOS VLSI circuits." Auburn, Ala, 2008. http://hdl.handle.net/10415/1517.
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Caldeira, Laercio. "Blocos CMOS de alta performance para aplicações em VLSI." [s.n.], 1993. http://repositorio.unicamp.br/jspui/handle/REPOSIP/260420.
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Orientador: Jose Antonio Siqueira DiasTese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica
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Resumo: Este trabalho integra o projeto de três blocos CMOS digitais de alta performance idealizados para incorporarem CIs VLSI, onde se buscou o melhor compromisso área/velocidade. Um dos blocos, o do Conversor A/D de 8 Bits, desenvolvido em arquitetura "flash" modificada, permite taxas de conversão superiores a 1 MHz adequando-o à grande maioria dos sistemas digitais. Os demais blocos, os Multiplicadores Paralelo e Série, foram desenvolvidos com base no Algoritmo de Booth e, portanto, exibem excelente desempenho trabalhando com palavras de até 64 bits. Projetou-se um Multiplicador Paralelo de 4 Bits operando com taxas de até 35 MHz e um Multiplicador Série de 8 Bits operando até 2,6 MHz
Abstract: This work compiles the design of three high performance CMOSdigital circuits blocks where the best area/speed relationship was required. Those circuits are intended to be implemented in VISI circuits. One of the blocks, the 8 bits A/D Converter, was implemented using a modified flash architecture, which allows conversion ratio above 1 MHz, suitable to the most of the digital systems. The other blocks, a parallel and a Serial Multipliers were developed based on the Booth Algorithm, wich has higher performance with words up to 64 bits. The 4 bits parallel multiplier designed works up to 35 MHz and the 8 bits serial multiplier works up to 2,6 MHz
Doutorado
Eletrônica e Microeletrônica
Doutor em Engenharia Elétrica
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Zarabadi, Seyed Ramezan. "Design of analog VLSI circuits in BICMOS/CMOS technology /." The Ohio State University, 1992. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487777170407338.
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Hamed, M. M. "Selective growth of silicon with application to CMOS processing." Thesis, University of Southampton, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.384208.
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Manetakis, Konstantinos. "Intermediate frequency CMOS analogue cells for wireless communications." Thesis, Imperial College London, 1999. http://hdl.handle.net/10044/1/11275.
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Pattnaik, Abhijeet. "DESIGN OF A CMOS BASED IMAGE SENSOR USING COMPRESSIVE IMAGE SENSING." OpenSIUC, 2021. https://opensiuc.lib.siu.edu/theses/2868.
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This work optimizes a CMOS image pixel sensor circuit for being used in a compressive sensing (CS) image sensor. The CS image sensor sums neighbor pixel outputs and hence reduces analog to digital conversions. Efforts are also made to improve the circuit that performs such pixel summation. With the optimized design, a CMOS image sensor circuit with a compression ratio of 4 is designed using a 130 nm CMOS technology from Global foundries. The design pixel sensor has a 256X256 pixel array. Simulation shows that the developed image sensors can achieve peak signal to noise ratio (PSNR) of 28 dB and 37.8 dB for benchmark images Cameraman and Lenna, respectively.
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Zhao, Si Ping. "Hot electron induced degradation in VLSI MOS devices." Thesis, University of Liverpool, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.320607.
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Madhyastha, Sadhana. "Design of circuit breakers for large area CMOS VLSI circuits." Thesis, McGill University, 1989. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=59551.
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Large-area ICs require adequate defect-tolerance to achieve a reasonable yield. One concern is that the power distribution network is shared by a number of modules, and any single short between the supply (V$ sb{dd}$) and ground can disable all these modules. The object of this thesis is to evaluate the feasibility of incorporating circuit breakers in large area ICs, which provide protection against such defects by disconnecting the defective modules from the array. A critical analysis and comparison of MOS transistors and parasitic bipolar transistors as circuit breakers are carried out. It is shown that MOS transistors offer a better and a more practical solution than their bipolar counterparts. Several rules applicable to a MOS circuit breaker in a bulk CMOS process are defined and discussed. These rules, if strictly adhered to, are predicted to result in a design which is defect-tolerant, latch-up free and optimal in size. The design of a large MOS transistor, based on the Manhattan style of "waffle-iron" design is described. Results of two test chips provide the experimental validation of this design. The peak instantaneous current through the modules has to be known in order to realize a circuit breaker of optimal size. A preliminary analysis of a possible technique to estimate the magnitude of this worst case peak current for a CMOS combinational block is carried out. Finally a short discussion on the defect sensitivity of the power switch is presented.
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Rogenmoser, Robert. "The design of high-speed dynamic CMOS circuits for VLSI /." Konstanz : Hartung-Gorre, 1996. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=11421.
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Li, Xiaojun. "Deep submicron CMOS VLSI circuit reliability modeling, simulation and design." College Park, Md. : University of Maryland, 2005. http://hdl.handle.net/1903/3124.
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Thesis (Ph. D.) -- University of Maryland, College Park, 2005.Thesis research directed by: Mechanical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
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Bracey, Mark. "Current domain analogue-to-digital conversion techniques for CMOS VLSI." Thesis, University of Southampton, 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.242618.
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Rothman, Daniel J. "CMOS VLSI implementation of the Quick Look Global Positioning System." Thesis, Massachusetts Institute of Technology, 1992. http://hdl.handle.net/1721.1/41782.
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Rosa, André Luís Rodeghiero. "Projeto de células e circuitos VLSI digitais CMOS para operação em baixa tensão." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/118526.
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Este trabalho propõe uma estratégia para projeto de circuitos VLSI operando em amplo ajuste de tensão e frequência (VFS), desde o regime em Near-threshold, onde uma tensão de VDD caracteriza-se por permitir o funcionamento do circuito com o mínimo dispêndio de energia por operação (MEP), até tensões nominais, dependendo da carga de trabalho exigida pela aplicação. Nesta dissertação é proposto o dimensionamento de transistores para três bibliotecas de células utilizando MOSFETs com tensões de limiar distintas: Regular-VT (RVT), High-VT (HVT) e Low-VT (LVT). Tais bibliotecas possuem cinco células combinacionais: INV, NAND, NOR, OAI21 e AOI22 em múltiplos strengths. A regra para dimensionamento dos transistores das células lógicas foi adaptada de trabalhos relacionados, e fundamenta-se na equalização dos tempos de subida e descida na saída de cada célula, objetivando à redução dos efeitos de variabilidade em baixas tensões de operação. Dois registradores também foram incluídos na biblioteca RVT e sua caracterização foi realizada considerando os parâmetros de processo CMOS 65 nm typical, fast e slow; nas temperaturas de operação de -40°C, 25°C e 125°C, e para tensões variando de 200 mV até 1,2V, para incluir a região de interesse, próxima ao MEP. Os experimentos foram realizados utilizando dez circuitos VLSI de teste: filtro digital notch, um núcleo compatível com o micro-controlador 8051, quatro circuitos combinacionais e quatro sequenciais do benchmark ISCAS. Em termos de economia de energia, operar no MEP resulta em uma redução média de 54,46% em relação ao regime de sub-limiar e até 99,01% quando comparado com a tensão nominal, para a temperatura de 25°C e processo típico. Em relação ao desempenho, operar em regime de VFS muito amplo propicia frequências máximas que variam de centenas de kHz até a faixa de centenas de MHz a GHz, para as temperaturas de -40°C e 25°C, e de MHz até GHz em 125°C. Os resultados desta dissertação, quando comparados a trabalhos relacionados, demonstraram, em média, redução de energia e ganho de desempenho de 24,1% e 152,68%, respectivamente, considerando os mesmos circuitos de teste, operando no ponto de mínima energia (MEP).This work proposes a strategy for designing VLSI circuits to operate in a very-wide Voltage-Frequency Scaling (VFS) range , from the supply voltage at which the minimum energy per operation (MEP) is achieved, at the Near-Threshold regime, up to the nominal supply voltage for the processes, if so demanded by applications workload. This master thesis proposes the sizing of transistors for three library cells using MOSFETs with different threshold voltages: Regular-VT (RVT), High-VT (HVT), and Low-VT (LVT). These libraries have five combinational cells: INV, NAND, NOR, OAI21, and AOI22 with multiple strengths. The sizing rule for the transistors of the digital cells was an adapted version from related works and it is directly driven by requiring equal rise and fall times at the output for each cell in order to attenuate variability effects in the low supply voltage regime. Two registers were also included in the RVT library cell. This library cell was characterized for typical, fast, and slow processes conditions of a CMOS 65nm technology; for operation at -40ºC, 25ºC, and 125ºC temperatures, and for supply voltages varying from 200 mV up to 1.2V, to include the region of interest, for VDD near the MEP. Experiments were performed with ten VLSI circuit benchmarks: notch filter, 8051 compatible core, four combinational and four sequential ISCAS benchmark circuits. From the energy savings point of view, to operate in MEP results on average reduction of 54.46% and 99.01% when compared with the sub-threshold and nominal supply voltages, respectively. This analysis was performed for 25⁰C and typical process. When considered the performance, the very-wide VFS regime enables maximum operating frequencies varying from hundreds of kHz up to MHz/GHz at -40ºC and 25ºC, and from MHz up to GHz at 125ºC. This master thesis results, when compared with related works, showed on average an energy reduction and performance gain of 24.1% and 152.68%, respectively, for the same circuit benchmarks operating with VDD at the minimum energy point (MEP).
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Wang, Shiwei. "Biomimetic cochlea filters : from modelling, design to analogue VLSI implementation." Thesis, University of Edinburgh, 2014. http://hdl.handle.net/1842/9695.
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This thesis presents a novel biomimetic cochlea filter which closely resembles the biological cochlea behaviour. The filter is highly feasible for analogue very-large-scale integration (VLSI) circuits, which leads to a micro-watt-power and millimetre-sized hardware implementation. By virtue of such features, the presented filter contributes to a solid foundation for future biologically-inspired audio signal processors. Unlike existing works, the presented filter is developed by taking direct inspirations from the physiologically measured results of the biological cochlea. Since the biological cochlea has prominently different characteristics of frequency response from low to high frequencies, the biomimetic cochlea filter is built by cascading three sub-filters accordingly: a 2nd-order bandpass filter for the constant gentle low-frequency response, a 2nd-order tunable low-pass filter for the variable and selective centre frequency response and a 5th-order elliptic filter for the ultra-steep roll-off at stop-band. As a proof of concept, a biomimetic cochlea filter bank is built to process audio signals, which demonstrates the highly discriminative spectral decomposition and high-resolution time-frequency analysis capabilities similar to the biological cochlea. The filter has simple representation in the Laplace domain which leads to a convenient analogue circuit realisation. A floating-active-inductor circuit cell is developed to build the corresponding RLC ladder for each of the three sub-filters. The circuits are designed based on complementary metal-oxide-semiconductor (CMOS) transistors for VLSI implementation. Non-ideal factors of CMOS transistors including parasitics, noise and mismatches are extensively analysed and consciously considered in the circuit design. An analogue VLSI chip is successfully fabricated using 0.35μ m CMOS process. The chip measurements demonstrate that the centre frequency response of the filter has about 20 dB wide gain tuning range and a high quality factor reaching maximally over 19. The filter has a 20 dB/decade constant gentle low-frequency tail and an over 300 dB/decade sharp stop-band roll-off slope. The measured results agree with the filter model expectations and are comparable with the biological cochlea characteristics. Each filter channel consumes as low as 59.5 ~90μ Wpower and occupies only 0.9 mm2 area. Besides, the biomimetic cochlea filter chip is characterised from a wide range of angles and the experimental results cover not only the auditory filter specifications but also the integrated circuit design considerations. Furthermore, following the progressive development of the acoustic resonator based on microelectro- mechanical systems (MEMS) technology, a MEMS-CMOS implementation of the proposed filter becomes possible in the future. A key challenge for such implementation is the low sensing capacitance of the MEMS resonator which suffers significantly from sensitivity degradation due to the parasitic capacitance. A novel MEMS capacitive interface circuit chip is additionally developed to solve this issue. As shown in the chip results, the interface circuit is able to cancel the parasitic capacitance and increase the sensitivity of capacitive sensors by 35 dB without consuming any extra power. Besides, the chopper-stabilisation technique is employed which effectively reduces the circuit flicker noise and offsets. Due to these features, the interface circuit chip is capable of converting a 7.5 fF capacitance change of a 1-Volt-biased 0.5 pF capacitive sensor pair into a 0.745 V signal-conditioned output while consuming only 165.2μ W power.
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Jackson, Kevin L. "A CMOS, VLSI, implementation of a FFT for cyclic spectral analysis." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1995. http://handle.dtic.mil/100.2/ADA294622.
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Thesis (M.S. in Electrical Engineering) Naval Postgraduate School, March 1995.Thesis advisor(s): Herschel H. Loomis, Jr., Raymond F. Berstein, Jr., Douglas J. Fouts. "March 1995." Includes bibliographical references. Also available online.
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Chalmers, Kenneth. "A CMOS DVD 4x Viterbi detector, system design and VLSI implementation." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0007/MQ45983.pdf.
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Lakshmikanthan, Preetham. "Novel energy-efficient leakage current minimization techniques for CMOS VLSI circuits." Related electronic resource: Current Research at SU : database of SU dissertations, recent titles available full text, 2007. http://wwwlib.umi.com/cr/syr/main.
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Blanchard, Yves. "Conception d'un circuit cmos-vlsi integrant une fonction de correlation numerique." Paris 11, 1991. http://www.theses.fr/1991PA112348.
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Cette these traite de l'implantation sous forme de circuit integre vlsi cmos d'une fonction de traitement de signal utilisee en particulier dans les radars et les sonars: la fonction de correlation. Apres une breve introduction de la fonction, l'integration vlsi est abordee par la presentation de differentes architectures possibles. En cherchant a implanter directement la fonction mathematique, on arrive a une architecture classique a base d'additionneurs, qui, si elle a l'avantage d'etre facile a implanter, a cependant les defauts d'occuper trop de place et de ne pouvoir tenir la frequence souhaitee. On fait donc evoluer cette ebauche vers une solution ou, en systolisant massivement l'operateur, on augmente, certes, le delai entre l'introduction de la premiere donnee et la sortie du premier resultat, mais ou on obtient ensuite un debit constant des sorties: le circuit devient pipe-line avec une frequence de travail beaucoup plus elevee. Cette architecture est ensuite developpee en detail, en tenant compte en particulier, des problemes de test et du chainage possible de circuits. La deuxieme partie decrit la bibliotheque qui a ete developpee pour le circuit en technologie cmos. Toutes les caracteristiques (dessins de masques, caracteristiques electriques et logique comportementale) sont fournies, permettant ainsi une utilisation dans d'autres circuits. Enfin l'implantation physique est detaillee: le circuit lui-meme, ainsi que son implantation dans un boitier 64 broches dip
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Shiraishi, Hisako. "Design of an Analog VLSI Cochlea." University of Sydney. Electrical and Information Engineering, 2003. http://hdl.handle.net/2123/556.
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The cochlea is an organ which extracts frequency information from the input sound wave. It also produces nerve signals, which are further analysed by the brain and ultimately lead to perception of the sound. An existing model of the cochlea by Fragni`ere is first analysed by simulation. This passive model is found to have the properties that the living cochlea does in terms of the frequency response. An analog VLSI circuit implementation of this cochlear model in CMOS weak inversion is proposed, using log-domain filters in current domain. It is fabricated on a chip and a measurement of a basilar membrane section is performed. The measurement shows a reasonable agreement to the model. However, the circuit is found to have a problem related to transistor mismatch, causing different behaviour in identical circuit blocks. An active cochlear model is proposed to overcome this problem. The model incorporates the effect of the outer hair cells in the living cochlea, which controls the quality factor of the basilar membrane filters. The outer hair cells are incorporated as an extra voltage source in series with the basilar membrane resonator. Its value saturates as the input signal becomes larger, making the behaviour rather closer to that of a passive model. The simulation results show this nonlinear phenomenon, which is also seen in the living cochlea. The contribution of this thesis is summarised as follows: a) the first CMOS weak inversion current domain basilar membrane resonator is designed and fabricated, and b) the first active two-dimensional cochlear model for analog VLSI implementation is developed.
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Aziz, Syed Mahfuzul. "The realisation of high-speed, testable multipliers suitable for synthesis using differential CMOS circuits." Thesis, University of Kent, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.240166.
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Zaveri, Jainish K. "Asic Design of RF Energy Harvester Using 0.13UM CMOS Technology." DigitalCommons@CalPoly, 2018. https://digitalcommons.calpoly.edu/theses/1940.
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Recent advances in wireless sensor nodes, data acquisition devices, wearable and implantable medical devices have paved way for low power (sub 50uW) devices. These devices generally use small solid state or thin film batteries for power supply which need replacement or need to be removed for charging. RF energy harvesting technology can be used to charge these batteries without the need to remove the battery from the device, thus providing a sustainable power supply. In other cases, a battery can become unnecessary altogether. This enables us to deploy wireless network nodes in places where regular physical access to the nodes is difficult or cumbersome.
This thesis proposes a design of an RF energy harvesting device able to charge commercially available thin film or solid-state batteries. The energy harvesting amplifier circuit is designed in Global Foundry 0.13um CMOS technology using Cadence integrated circuit design tools. This Application Specific Integrated Circuit (ASIC) is intended to have as small a footprint as possible so that it can be easily integrated with the above-mentioned devices. While a dedicated RF power source is a direct solution to provide sustainable power to the harvesting circuit, harvesting ambient RF power from TV and UHF cellular frequencies increases the possibilities of where the harvesting device can be placed. The biggest challenge for RF energy harvesting technology is the availability of adequate amount of RF power. This thesis also presents a survey of available RF power at various ultra-high frequencies in San Luis Obispo, CA.The idea is to determine the frequency band which can provide maximum RF power for harvesting and design a harvester for that frequency band.
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Pereira, dos Santos Rodolfo. "Mecanismo de otimização para redução de potência estática de circuitos integrados baseado na técnica Dual-VTH." Universidade Federal de Pernambuco, 2010. https://repositorio.ufpe.br/handle/123456789/2443.
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Previous issue date: 2010Com o advento de novas tecnologias de fabricação, a complexidade e a capacidade de processamento dos sistemas microeletrônicos tornaram-se cada vez maiores. Contudo devido às tendências de mercado atuais, dispositivos portáteis, alimentados à bateria, estão sendo cada vez mais procurados, de modo que uma demanda de produtos que tenham uma maior capacidade de prolongar a vida útil das baterias vem crescendo. Recentemente, a redução do tamanho do transistor propiciou uma mudança no comportamento das componentes de energia em transistores CMOS. A componente estática que antigamente era praticamente desprezada tem aumentado exponencialmente com alterações não proporcionais, tais como diminuição do canal e redução de tensão de alimentação dos circuitos. Atualmente, esta componente estática representa uma fração significante da potência total consumida em circuitos com tecnologias de fabricação abaixo de 90 nm, podendo passar de 50% da potência total. Este consumo torna-se cada vez mais expressivo à medida que as tensões de alimentação dos circuitos são reduzidas, devido à necessidade de se minimizar a tensão de threshold para manter o desempenho dos circuitos. O algoritmo desenvolvido para a redução de potência estática em circuitos integrados digitais pode ser inserido no fluxo de desenvolvimento, sem causar penalidades ao mesmo. Na abordagem proposta, baseada na técnica Dual-Threshold, parte das células do circuito é substituída por células com tensão de threshold mais alta sem que haja inserção de violações de tempo no circuito. A troca de cada célula é definida a partir de estimativas do comportamento do circuito caso a célula seja trocada, antes que ela seja de fato substituída. Ao contrário de abordagens baseadas em caminhos, a característica de não haver trocas a cada análise das células do circuito, permite uma redução significativa no tempo de execução do algoritmo. Os resultados obtidos, que apresentaram uma redução de potência estática de até 39%, resultaram da execução do algoritmo utilizando circuitos do benchmark ISCAS85
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Buchanan, Brent E. "A mixed-signal CMOS VLSI image convolution circuit using error spectrum shaping." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15420.
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Barton, Robert James. "A CMOS current-mode full-adder cell for multi-valued logic VLSI." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1995. http://handle.dtic.mil/100.2/ADA306649.
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Thesis (M.S. in Electrical Engineering and M.S. in Computer Science) Naval Postgraduate School, September 1995.Thesis advisor(s): Douglas J. Fouts, Amr Zaky. "September 1995." Includes bibliographical references. Also available online.
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Bingham, Brad D. "Energy-time complexity of algorithms : modelling the trade-offs of CMOS VLSI." Thesis, University of British Columbia, 2007. http://hdl.handle.net/2429/32142.
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Power consumption has become one of the most critical concerns for processor design.
Parallelism offers a pathway to increased performance under power constraints — many
slow processors can complete a parallel implementation of a task using less time and less
energy than a fast uniprocessor. This relies on the energy-time trade-offs present in CMOS
circuits, including voltage scaling. Understanding these trade-offs and their connection with
algorithms will be a key for extracting performance in future multicore processor designs.
I propose simple models for analysing algorithms and deriving lower bounds that
reflect the energy-time trade-offs and parallelism of CMOS circuits. For example, the models
constrain computational elements to lie in a two-dimensional topology. These elements,
called processing elements (PEs), compute arbitrary functions of a constant number of input
bits and store a constant-bounded memory. PEs are used to implement wires; thus
subsuming and accounting for communication costs. Each operation of a PE takes time t
and consumes energy e, where eta remains invariant for some fixed α > 0. Not only may
different PEs independently trade time for energy in this way, but the same PE may vary
the trade-off on an operation by operation basis.
Using these models, I derive lower bounds for the ETα costs of sorting, addition
and multiplication, where E and T are the total energy and time, and present algorithms
that meet these bounds asymptotically. Clearly there exist many algorithms to solve each
of these problems, and furthermore there are many choices of how to implement them with
processing elements. Fortunately, the tight asymptotic bounds collapse the hierarchy of
algorithms, implementations and schedules. This demonstrates that choosing other algorithms
or layout schemes may only improve the energy-time "cost" by constant factors.
In addition to analysing energy-time optimal algorithms for these problems, I also
determine the complexity of many other well-established algorithms. This sheds light on
the relative energy-time efficiency of these algorithms, revealing that some "fast" algorithms
exploit free communication of traditional computation models. I show that energy-time
minimal algorithms are not the same as those that minimize operation count or the
computation depth.Science, Faculty of
Computer Science, Department of
Graduate
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Mohammad, Sakib. "A NOVEL MULTIPLIER USING MODIFIED SHIFT AND ADD ALGORITHM." OpenSIUC, 2021. https://opensiuc.lib.siu.edu/theses/2867.
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Binary multiplier has been a staple in the digital circuit design. It is used in microprocessor design, DSP applications etc. Here, we discuss the design of a novel multiplier that employs a modified shift and add logic to multiply two n-bit unsigned binary numbers. In our work, we changed the shift and add algorithm. We used a barrel shifter and a multiplexer to generate the partial products. We also found out a way to reduce the number of partial products so that we would have fewer numbers to add after we generated all of them. An array of Carry Save Adders (CSA) is used to add the partial products. With all our arrangements and setups, we aim to reduce delays and make the design as efficient as possible. As examples, we have shown it to multiply two 16-bit numbers, however, the design can easily be either scaled up or down according to the environment the multiplier is being used.
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Pancholy, Ashish. "Automated fault diagnosis and empirical validation of fault models in CMOS VLSI circuits." Thesis, McGill University, 1990. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=60420.
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The selection of adequate fault models is crucial to generating tests of high quality for complex digital VLSI circuits. This thesis presents a methodology to perform empirical validation of fault models and to get measures of effectiveness of test sets based on the targeted fault models.The methodology is based on the automated fault diagnosis of test circuits, representative of the class of circuits being studied and designed to capture the characteristics of the fabrication process, cell libraries and CAD tools used in their development.
The methodology is applied to study the faulty behaviour of random logic environments for an experimental VLSI fabrication process. A test circuit is designed, using CMOS technology, and a statistically significant number of samples fabricated. The samples are tested and, subsequently, diagnosed, using a set of software tools developed for the purpose. Results of the ensuing analysis are presented.
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Richstein, James K. "A CMOS VLSI IC for real-time opto-electronic two-dimensional histogram generation." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1993. http://handle.dtic.mil/100.2/ADA277910.
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Thesis (M.S. in Electrical Engineering) Naval Postgraduate School, December 1993.Thesis advisor(s): Ron J. Pieper ; Douglas J. Fouts. "December 1993." Includes bibliographical references. Also available online.
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Bensouiah, Djamel Abderrahmane. "Testability and redundancy techniques for improved yield and reliability of CMOS VLSI circuits." Thesis, Durham University, 1992. http://etheses.dur.ac.uk/6008/.
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The research presented in this thesis is concerned with the design of fault-tolerant integrated circuits as a contribution to the design of fault-tolerant systems. The economical manufacture of very large area ICs will necessitate the incorporation of fault-tolerance features which are routinely employed in current high density dynamic random access memories. Furthermore, the growing use of ICs in safety-critical applications and/or hostile environments in addition to the prospect of single-chip systems will mandate the use of fault-tolerance for improved reliability. A fault-tolerant IC must be able to detect and correct all possible faults that may affect its operation. The ability of a chip to detect its own faults is not only necessary for fault-tolerance, but it is also regarded as the ultimate solution to the problem of testing. Off-line periodic testing is selected for this research because it achieves better coverage of physical faults and it requires less extra hardware than on-line error detection techniques. Tests for CMOS stuck-open faults are shown to detect all other faults. Simple test sequence generation procedures for the detection of all faults are derived. The test sequences generated by these procedures produce a trivial output, thereby, greatly simplifying the task of test response analysis. A further advantage of the proposed test generation procedures is that they do not require the enumeration of faults. The implementation of built-in self-test is considered and it is shown that the hardware overhead is comparable to that associated with pseudo-random and pseudo-exhaustive techniques while achieving a much higher fault coverage through-the use of the proposed test generation procedures. The consideration of the problem of testing the test circuitry led to the conclusion that complete test coverage may be achieved if separate chips cooperate in testing each other's untested parts. An alternative approach towards complete test coverage would be to design the test circuitry so that it is as distributed as possible and so that it is tested as it performs its function. Fault correction relies on the provision of spare units and a means of reconfiguring the circuit so that the faulty units are discarded. This raises the question of what is the optimum size of a unit? A mathematical model, linking yield and reliability is therefore developed to answer such a question and also to study the effects of such parameters as the amount of redundancy, the size of the additional circuitry required for testing and reconfiguration, and the effect of periodic testing on reliability. The stringent requirement on the size of the reconfiguration logic is illustrated by the application of the model to a typical example. Another important result concerns the effect of periodic testing on reliability. It is shown that periodic off-line testing can achieve approximately the same level of reliability as on-line testing, even when the time between tests is many hundreds of hours.
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Barkley, Edward Robert 1977. "Wafer bonding of processed Si CMOS VLSI and GaAs for mixed technology integration." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/8368.
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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, Februaru 2002.Includes bibliographical references (p. 91-94).
The successful bonding of bare thinned Si SOI wafers to bare GaAs wafers in previous research has proven to be an important first step in achieving integration of Si electronics with GaAs optoelectronic devices. The thinning of the SOI wafer has been shown to be a successful solution to the problem of the thermal expansion coefficient mismatch between Si and GaAs, allowing for the potential dense integration of mixed optoelectronic and electronic technologies. This research takes the next logical step toward that end by bonding Si wafers with simulated full back-end processing to GaAs wafers. The back-end processing simulation consists of depositing 1000[Angstroms] of Al, patterning the Al into 5[mu]m serpentine lines on a 5[mu]m pitch, covering the Al with a PECVD oxide, and performing CMP planarization of the oxide. The 1000[Angstroms] variations caused by the Al layer are consistent with surface profiles taken from fully processed SOI wafers obtained from IBM. The result is that these "simulation" wafers model the difficulties presented with bonding fully processed wafers; namely the temperature constraints caused by the existence of buried Al metal and the topography created by the patterned metal. The entire process, including the bonding and post-bond anneal, is carried out at temperatures below 45° C, making it compatible with a fully processed SOI CMOS wafer. The use of dielectric CMP has become a common back-end processing step. The wafer bonding in this work relies on CMP technology to planarize PECVD oxide deposited on the bonding surface of both wafers. The combination of CMP with post CMP cleaning methods results in a PECVD oxide surface with an order of magnitude reduction in the r.m.s. roughness, rendering the surface smooth enough to facilitate wafer bonding. The future goal of this project is to bond fully processed Si CMOS wafers to GaAs wafers containing optoelectronic devices and to test the feasibility of creating interconnects through the bond interface.
by Edward Robert Barkley.
S.M.
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Taris, Thierry. "Conception de circuits radiofréquences en technologie CMOS VLSI sous contrainte de basse tension." Bordeaux 1, 2003. http://www.theses.fr/2003BOR16015.
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Ma thèse intitulée "conception de circuits radiofréquences en technologie CMOS VLSI sous contrainte de faible tension" s'est déroulée au sein du laboratoire IXL de l'Université de bordeaux 1. Elle a permis dans un premier temps de mettre en avant les contraintes de conception induites par le marché de masse des objets sans fil qui sont : la faible consommation, la faible tension d'alimentation, l'utilisation de technologies CMOS VLSI et la nécessité de réaliser des architectures innovantes. Ainsi, s'appuyant au préalable sur une étude théorique et analytique de l'effet de substrat, nous avons conçu des circuits novateurs dédiés aux chaînes d'émission/réception radiofréquences tels : des amplificateurs faible de bruit (LNA), des mélangeurs (MIXER) ainsi qu'un préamplificateur de puissance (PPA). Le test de ces blocs a permis de valider leur adéquation avec les spécifications requises par les standards actuels de communication comme : le GSM, le DCS1800, l'UMTS, les normes IEEE 802. 11aet b, Bluetooch et enfin HiperLAN2.
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Khachab, Nabil Ibrahim. "Analog CMOS nonlinear cells and their applications in VLSI signal and information processing /." The Ohio State University, 1990. http://rave.ohiolink.edu/etdc/view?acc_num=osu148768520496624.
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Hauck, Oliver. "Asynchronous wave pipelines for energy efficient gigahertz VLSI." Phd thesis, [S.l.] : [s.n.], 2007. http://elib.tu-darmstadt.de/diss/000795.
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Elgebaly, Mohamed. "Energy Efficient Design for Deep Sub-micron CMOS VLSIs." Thesis, University of Waterloo, 2005. http://hdl.handle.net/10012/892.
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Over the past decade, low power, energy efficient VLSI design has been the focal point of active research and development. The rapid technology scaling, the growing integration capacity, and the mounting active and leakage power dissipation are contributing to the growing complexity of modern VLSI design. Careful power planning on all design levels is required. This dissertation tackles the low-power, low-energy challenges in deep sub-micron technologies on the architecture and circuit levels.
Voltage scaling is one of the most efficient ways for reducing power and energy. For ultra-low voltage operation, a new circuit technique which allows bulk CMOS circuits to work in the sub-0. 5V supply territory is presented. The threshold voltage of the slow PMOS transistor is controlled dynamically to get a lower threshold voltage during the active mode. Due to the reduced threshold voltage, switching speed becomes faster while active leakage current is increased. A technique to dynamically manage active leakage current is presented. Energy reduction resulting from using the proposed structure is demonstrated through simulations of different circuits with different levels of complexity.
As technology scales, the mounting leakage current and degraded noise immunity impact performance especially that of high performance dynamic circuits. Dual threshold technology shows a good potential for leakage reduction while meeting performance goals. A model for optimally selecting threshold voltages and transistor sizes in wide fan-in dynamic circuits is presented. On the circuit level, a novel circuit level technique which handles the trade-off between noise immunity and energy dissipation for wide fan-in dynamic circuits is presented. Energy efficiency of the proposed wide fan-in dynamic circuit is further enhanced through efficient low voltage operation.
Another direct consequence of technology scaling is the growing impact of interconnect parasitics and process variations on performance. Traditionally, worst case process, parasitics, and environmental conditions are considered. Designing for worst case guarantees a fail-safe operation but requires a large delay and voltage margins. This large margin can be recovered if the design can adapt to the actual silicon conditions. Dynamic voltage scaling is considered a key enabler in reducing such margin. An on-chip process identifier to recover the margin required due to process variations is described. The proposed architecture adjusts supply voltage using a hybrid between the one-time voltage setting and the continuous monitoring modes of operation. The interconnect impact on delay is minimized through a novel adaptive voltage scaling architecture. The proposed system recovers the large delay and voltage margins required by conventional systems by closely tracking the actual critical path at anytime. By tracking the actual critical path, the proposed system is robust and more energy efficient compared to both the conventional open-loop and closed-loop systems.
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Fatine, Steven Carleton University Dissertation Engineering Electronics. "Design and VLSI implementation of CMOS decimation and interpolation half-band FIR digital filters." Ottawa, 1996.
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Hung, Chung-Chih. "Low voltage, low power CMOS analog circuit design techniques for mobile, portable VLSI applications /." The Ohio State University, 1997. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487943341527253.
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Dandache, Abbas. "Conception de PLA CMOS." Phd thesis, Grenoble 2 : ANRT, 1986. http://catalogue.bnf.fr/ark:/12148/cb37596962j.
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Junqueira, Alexandre Ambrozi. "Risco : microprocessador RISC CMOS de 32 bits." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 1993. http://hdl.handle.net/10183/21530.
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Este trabalho apresenta o estudo, a definição e a simulação elétrica e lógica de um microprocessador CMOS de 32 bits, com arquitetura tipo RISC - o Risco. Dentre as principais características do Risco destacam-se: dados, instruções e endereços são palavras de 32 bits; a unidade de endereçamento é a palavra, permitindo um acesso a 4 Giga palavras (16 Gbytes); a comunição com a memória é feita por um barramento multiplexado de 32 bits para dados e endereços; possui 32 registradores de 32 bits, incluídos nestes o contador de programa, o apontador de pilha, a palavra de status do processador e um registrador constante zero; possui um pipeline de instruções de 3 estágios, atingindo no pico de execução uma instrução por ciclo de máquina; e as instruções de salto têm sua execução retardada de uma instrução. A Arquitetura de Computadores é analisada, em especial as Arquiteturas RISC (Reduced Instruction Set Computer - Processador com Conjunto de Instruções Reduzido) e CISC (Complex...), mostrando suas características e comparando-as. Algumas máquinas RISC importantes são vistas e o tema de Arquiteturas VLSI e suas implicações tecnológicas no projeto também é abordado. A arquitetura do Risco é descrita dando-se ênfase aos objetivos do projeto e construindo uma visão geral do processador. O tratamento de exceções é apresentado e o conjunto de instruções é analisado quanto ao formato, aos tipos e ao processamento no pipeline. A organização interna do Risco 6 tratada em detalhes, descrevendo-se a Parte Operativa (barramentos, o banco de registradores, a unidade de tratamento da constante, o contador de programa e incrementador associado, a unidade lógico-aritmética, a unidade de deslocamento/rotação) e a Parte de Controle to funcionamento do pipeline de instrug6es, a decodificação, o autômato de controle, a geração e a validação dos comandos). A simulação funcional do Risco, feita em HDC, também é reportada, incluindo o modelamento, os vetores de testa e os resultados. A implementação do Risco é discutida enfatizando-se alguns blocos críticos quanto A Área e ao desempenho. Os barramentos e o banco de registradores, a ULA e a unidade de deslocamento/rotação são estudados em detalhes pela sua importância no desempenho da maquina. Um teste chip contendo a maior parte dos blocos funcionais da parte operativa foi construído, tendo sido aprovado nos testes funcionais. Por fim, faz-se comentários sobre os resultados obtidos, os problemas encontrados e as etapas futuras no desenvolvimento do Risco, alem de serem expostas as conclusões finais.This work presents the study, the definition, the electric and logic simulation, and the implementation of some blocks of a 32-bit CMOS microprocessor, with RISC architecture - the Risco. Among Risco's main characteristics it is highlighted that data, instructions and addresses are 32-bit words; the address unit is the word, allowing an access to 4-Giga words (16 GBytes); communication with memory is made through a data and address bus of 32 bits; it has 32 registers of 32 bits, including program counter, stack pointer, processor status word, and a zero constant register; it also has an instruction pipeline of three stages, fully capable of issuing one instruction at the execution peak per every machine cycle; and control flow instructions are implemnted as delayed branches. A study on computer architecture is carried out, and special attention is given to the RISC (Reduced Instruction Set Computer) and CISC (Complex...) architectures by means of making comparisons between them, showing their main characteristics and listing some important RISC machines. The VLSI architectures are also discussed, giving emphasis to their technological importance for the Risco's project. Risco's architecture is described, bringing into prominence the aims of the project and an overview of the processor. Exception handling is presented and the instruction set is analysed with regard to format, type and pipeline processing. Risco's internal organization is dealt with in detail, providing descriptions of the data path (buses, register bank, constant unit, program counter and associated incrementer, barrel shifter) and of the control part (operation of pipeline instruction, as well as decodification, control automaton, generation and validation of commands). Risco's functional simulation, through HDC, is mentioned, including modeling, test vectors, and results. Risco's implementation is also discussed giving emphasis to some critical blocks in regard to area and performance. Buses, register bank, arithmetic-logic unit, and barrel shifter are dealt with in detail because of their importance concerning the machine performance. A test-chip, containing most of the functional blocks of the data path, was made and successfully passed the functional tests. Finally, some comments are made with regard to results, main problems, and next stages in the development of Risco.