Relevant bibliographies by topics / CMOS Voltage Reference

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'CMOS Voltage Reference'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "CMOS Voltage Reference"

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Dai, Y., D. T. Comer, D. J. Comer, and C. S. Petrie. "Threshold voltage based CMOS voltage reference." IEE Proceedings - Circuits, Devices and Systems 151, no. 1 (2004): 58. http://dx.doi.org/10.1049/ip-cds:20040217.

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Kim, Jae-Bung, and Seong-Ik Cho. "Modified Low-Votlage CMOS Bandgap Voltage Reference with CTAT Compensation." Transactions of The Korean Institute of Electrical Engineers 61, no. 5 (May 1, 2012): 753–56. http://dx.doi.org/10.5370/kiee.2012.61.5.753.

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Li, Lin An, Ming Tang, Wen Ou, and Yang Hong. "An All CMOS Current Reference." Applied Mechanics and Materials 135-136 (October 2011): 192–97. http://dx.doi.org/10.4028/www.scientific.net/amm.135-136.192.

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In this paper, an all CMOS current reference circuit which generates a reference current independent of PVT (Process, supply Voltage, and Temperature) variations is presented. The circuit consists of a self-biased current source (SBCS) and two nested connected transistors which supply a voltage with positive temperature coefficient and the resulting reference circuit has low temperature coefficient. It is based on CSMC 0.5um mixed-signal process with the supply voltage of 5V. The precision of reference current is about ±3.05% when considering the process, supply voltage and temperature variation at the same time.
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Olivera, Fabian, and Antonio Petraglia. "Adjustable Output CMOS Voltage Reference Design." IEEE Transactions on Circuits and Systems II: Express Briefs 67, no. 10 (October 2020): 1690–94. http://dx.doi.org/10.1109/tcsii.2019.2943303.

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Gu, Y. B., S. F. Yueh, T. W. Chang, and K. C. Huang. "CMOS voltage reference with multiple outputs." IET Circuits, Devices & Systems 2, no. 2 (2008): 222. http://dx.doi.org/10.1049/iet-cds:20070211.

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Lo, Tien-Yu, Chung-Chih Hung, and Mohammed Ismail. "CMOS voltage reference based on threshold voltage and thermal voltage." Analog Integrated Circuits and Signal Processing 62, no. 1 (June 11, 2009): 9–15. http://dx.doi.org/10.1007/s10470-009-9321-y.

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Wang, San-Fu. "A 5 V-to-3.3 V CMOS Linear Regulator with Three-Output Temperature-Independent Reference Voltages." Journal of Sensors 2016 (2016): 1–7. http://dx.doi.org/10.1155/2016/1436371.

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This paper presents a 5 V-to-3.3 V linear regulator circuit, which uses 3.3 V CMOS transistors to replace the 5 V CMOS transistors. Thus, the complexity of the manufacturing semiconductor process can be improved. The proposed linear regulator is implemented by cascode architecture, which requires three different reference voltages as the bias voltages of its circuit. Thus, the three-output temperature-independent reference voltage circuit is proposed, which provides three accurate reference voltages simultaneously. The three-output temperature-independent reference voltages also can be used in other circuits of the chip. By using the proposed temperature-independent reference voltages, the proposed linear regulator can provide an accurate output voltage, and it is suitable for low cost, small size, and highly integrated system-on-chip (SoC) applications. Moreover, the proposed linear regulator uses the cascode technique, which improves both the gain performance and the isolation performance. Therefore, the proposed linear regulator has a good performance in reference voltage to output voltage isolation. The voltage variation of the linear regulator is less than 2.153% in the temperature range of −40°C–120°C, and the power supply rejection ratio (PSRR) is less than −42.8 dB at 60 Hz. The regulator can support 0~200 mA output current. The core area is less than 0.16 mm2.
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Ria, Andrea, Alessandro Catania, Paolo Bruschi, and Massimo Piotto. "A Low-Power CMOS Bandgap Voltage Reference for Supply Voltages Down to 0.5 V." Electronics 10, no. 16 (August 8, 2021): 1901. http://dx.doi.org/10.3390/electronics10161901.

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A voltage reference is strictly required for sensor interfaces that need to perform nonratiometric data acquisition. In this work, a voltage reference capable of working with supply voltages down to 0.5 V is presented. The voltage reference was based on a classic CMOS bandgap core, properly modified to be compatible with low-threshold or zero-threshold MOSFETs. The advantages of the proposed circuit are illustrated with theoretical analysis and supported by numerical simulations. The core was combined with a recently proposed switched capacitor, inverter-like integrator implementing offset cancellation and low-frequency noise reduction techniques. Experimental results performed on a prototype designed and fabricated using a commercial 0.18 μm CMOS process are presented. The prototype produces a reference voltage of 220 mV with a temperature sensitivity of 45 ppm/°C across a 10–50 °C temperature range. The proposed voltage reference can be used to source currents up to 100 μA with a quiescent current consumption of only 630 nA.
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Zhou, Qian Neng, Yun Song Li, Jin Zhao Lin, Hong Juan Li, Chen Li, Yu Pang, Guo Quan Li, Xue Mei Cai, and Qi Li. "A High-Order CMOS Bandgap Voltage Reference." Advanced Materials Research 989-994 (July 2014): 1165–68. http://dx.doi.org/10.4028/www.scientific.net/amr.989-994.1165.

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A high-order bandgap voltage reference (BGR) is designed by adopting a current which is proportional to absolute temperature T1.5. The high-order BGR is analyzed and simulated in SMIC 0.18μm CMOS process. Simulation results show that the designed high-order BGR achieves temperature coefficient of 2.54ppm/°C when temperature ranging from-55°C to 125°C. The high-order BGR at 10Hz, 100Hz, 1kHz, 10kHz and 100kHz achieves, respectively, the power supply rejection ratio of-64.01dB, -64.01dB, -64dB, -63.5dB and-53.2dB. When power supply voltage changes from 1.7V to 2.5V, the output voltage deviation of BGR is only 617.6μV.
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Park, Minseon, and Sung Min Park. "A CMOS symmetric self-biased voltage reference." Microelectronics Journal 80 (October 2018): 28–33. http://dx.doi.org/10.1016/j.mejo.2018.08.002.

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Dissertations / Theses on the topic "CMOS Voltage Reference"

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Holman, William Timothy. "A low noise CMOS voltage reference." Diss., Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/14968.

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Komark, Stina. "Design of an integrated voltage regulator." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1711.

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Many analog systems need a stable power supply voltage that does not vary with temperature and time in order to operate properly. In a battery operated system the battery voltage is not stable, e.g. it decreases with decreasing temperature and with ageing. In that case a voltage regulator must be used, that regulates the battery voltage and generates a stable supply voltage to power other circuitry.

In this thesis a voltage regulator to be used in a battery operated system has been designed which meets the given specification of stability and power capabilities. A voltage reference, which is a commonly used devise in analog circuits, was also designed. The role of a reference voltage in an electrical system is the same as for a tuning fork in a musical ensemble; to set a standard to which other voltages are compared.

A functionality to detect when the lifetime of the battery is about to run out was also developed.

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Kotrč, Václav. "Napěťové reference v bipolárním a CMOS procesu." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2015. http://www.nusl.cz/ntk/nusl-221111.

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This diploma thesis deals with precise design of Brokaw BandGap voltage reference comparing with MOS references. There is STEP BY STEP separation and analysis of proposed devices, using Monte Carlo analysis. There are also presented the methods for achieving a lower deviation of the output voltage for yielding device, which needs no trimming.
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Gupta, Vishal. "An accurate, trimless, high PSRR, low-voltage, CMOS bandgap reference IC." Diss., Available online, Georgia Institute of Technology, 2007, 2007. http://etd.gatech.edu/theses/available/etd-07052007-073154/.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.
Ayazi, Farrokh, Committee Member ; Rincon-Mora, Gabriel, Committee Chair ; Bhatti, Pamela, Committee Member ; Leach, W. Marshall, Committee Member ; Morley, Thomas, Committee Member.
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Kevin, Tom. "Sub-1V Curvature Compensated Bandgap Reference." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2585.

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This thesis investigates the possibility of realizing bandgap reference crcuits for processes having sub-1V supply voltage. With the scaling of gate oxide thickness supply voltage is getting reduced. But the threshold voltage of transistors is not getting scaled at the same rate as that of the supply voltage. This makes it difficult to incorporate conventional designs of bandgap reference circuits to processeshaving near to 1V supply voltage. In the first part of the thesis a comprehensive study on existing low voltage bandgap reference circuits is done. Using these ideas a low-power, low-voltage bandgap reference circuit is designed in the second part of the thesis work.

The proposed bandgap reference circuit is capable of generating a reference voltage of 0.730V. The circuit is implemented in 0.18µm standard CMOS technology and operates with 0.9V supply voltage, consuming 5µA current. The circuit achieves 7 ppm/K of temperature coefficient with supply voltage range from 0.9 to 1.5V and temperature range from 0 to 60C.

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Mattia, Neto Oscar Elisio. "NanoWatt resistorless CMOS voltage references for Sub-1 V applications." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/107131.

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Referências de tensão integradas sempre foram um bloco fundamental de qualquer sistema eletrônico e um importante tópico de pesquisa que tem sido estudado extensivamente nos últimos 50 anos. Uma tensão de referência é um circuito que provê uma tensão estável com baixa sensibilidade a variações em temperatura, alimentação, carga, características do processo de fabricação e tensões mecânicas de encapsulamento. Elas são normalmente implementadas através da soma ponderada de dois fenômenos físicos diferentes, com comportamentos em temperatura opostos. Normalmente, a tensão térmica, relacionada à constante de Boltzmann e à carga do elétron, fornece uma dependência positiva com temperatura, enquanto que a tensão base-emissor VBE de um transistor bipolar ou a tensão de limiar de um MOSFET fornece o termo complementar. Um bloco auxiliar é às vezes utilizado para fornecer as correntes de polarização do circuito, e outros blocos adicionais implementam a soma ponderada. A evolução da tecnologia de processos é o principal fator para aplicações em baixa tensão, enquanto que a emergência de dispositivos portáteis operados a bateria, circuitos biomédicos implantáveis e dispostivos de captura de energia do ambiente restringem cada circuito a consumir o mínimo possivel. Portanto, alimentações abaixo de 1 V e consumos na ordem de nanoWatts se tornaram características fundamentais de tais circuitos. Contudo, existem diversos desafios ao projetar referências de tensão de alta exatidão em processos CMOS modernos sob essas condições. As topologias tradicionais não são adequadas pois elas provêm uma referência de tensão acima de 1 V, e requerem resistências da ordem de G para atingir tão baixo consumo de potência, ocupando assim uma grande área de silício. Avanços recentes atingiram tais níveis de consumo de potência, porém com limitada exatidão, custosos procedimentos de calibração e grande área ocupada em silício. Nesta dissertação apresentam-se duas novas topologias de circuitos: uma tensão de junção bipolar com compensação de curvatura que não utiliza resistores e é auto-polarizada; e um circuito de referência bandgap sem resistores que opera abaixo de 1 V (também chamado de sub-bandgap). Ambos circuitos operam com consumo na ordem de nanoWatts e ocupam pequenas áreas de silício. Resultados de simulação para dois processos diferentes, 180 nm e 130 nm, e resultados experimentais de uma rodada de fabricação em 130 nm apresentam melhorias sobre tais limitações, mantendo as características desejadas de não conter resistores, ultra baixo consumo, baixa tensão de alimentação e áreas muito pequenas.
Integrated voltage references have always been a fundamental block of any electronic system, and an important research topic that has been extensively studied in the past 50 years. A voltage reference is a circuit that provides a stable voltage with low sensitivity to variations in temperature, supply, load, process characteristics and packaging stresses. They are usually implemented through the weighted sum of two independent physical phenomena with opposite temperature dependencies. Usually the thermal voltage, related to the Boltzmann’s constant and the electron charge, provides a positive temperature dependence, while the silicon bandgap voltage or a MOSFET’s threshold voltage provide the complementary term. An auxiliary biasing block is sometimes necessary to provide the necessary currents for the circuit to work, and additional blocks implement the weighted sum. The scaling of process technologies is the main driving factor for low voltage operation, while the emergence of portable battery-operated, implantable biomedical and energy harvesting devices mandate that every circuit consume as little power as possible. Therefore, sub-1 V supplies and nanoWatt power have become key characteristics for these kind of circuits, but there are several challenges when designing high accuracy voltage references in modern CMOS technologies under these conditions. The traditional topologies are not suitable because they provide a reference voltage above 1 V, and to achieve such power consumption levels would require G resistances, that occupy a huge silicon area. Recent advances have achieved these levels of power consumption but with limited accuracy, expensive calibration procedures and large silicon area.
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Caicedo, Jhon Alexander Gomez. "CMOS low-power threshold voltage monitors circuits and applications." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2016. http://hdl.handle.net/10183/144080.

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Um monitor de tensão de limiar (VT0) é um circuito que, idealmente, entrega o valor do VT0 como uma tensão na saída, para uma determinada faixa de temperatura, sem a necessidade de polarização externa, configurações paramétricas, ajuste de curvas ou qualquer cálculo subsequente. Estes circuitos podem ser usados em sensores de temperatura, referências de tensão e corrente, dosímetros de radiação e outras aplicações, uma vez que a dependência do VT0 nas condições de operação é um aspecto bem modelado. Além disso, estes circuitos podem ser utilizados para monitoramento de processos de fabricação e para compensação da variabilidade do processo, uma vez que o VT0 é um parâmetro chave para o comportamento do transistor e sua modelagem. Nesta tese, são apresentadas três novas topologias de circuitos, duas são monitores de VT0 NMOS e a terceira é um monitor de VT0 PMOS. As três estruturas são topologias de circuito auto-polarizadas que não utilizam resistências, e apresentam alta rejeição a variações na alimentação, baixa sensibilidade de Linea, e permitem a extração direta da tensão de limiar para grandes intervalos de temperatura e de tensão de alimentação, com pequeno erro. Sua metodologia de projeto é baseada no modelo unificado controlado por corrente (UICM), um modelo MOSFET que é contínuo, desde o nível de inversão fraca a forte e para as regiões de operação de triodo e saturação. Os circuitos ocupam uma pequena área de silício, consomem apenas dezenas de nanowatts, e podem ser implementados em qualquer processo padrão CMOS digital, uma vez que só utilizam transistores MOS (não precisa de nenhum resistor). Os monitores de VT0 são utilizados em diferentes aplicações, a fim de investigar a sua funcionalidade e comportamento como parte de um sistema. As aplicações variam de uma tensão de referência, que apresenta um desempenho comparável ao estado da arte, para uma configuração que permite obter uma menor variabilidade com processo na saída de um circuito auto-polarizado que gera um tensão CTAT. Além disso, explorando a capacidade de funcionar como um gerador de corrente específica (ISQ) que os monitores de VT0 aqui apresentados oferecem, introduz-se um novo circuito auto-polarizado que gera um tensão CTAT, que é menos sensível a variações de processo, e pode ser usado em referências de tensão band-gap.
A threshold voltage (VT0) monitor is a circuit that ideally delivers the estimated VT0 value as a voltage at its output, for a given temperature range, without external biases, parametric setups, curve fitting or any subsequent calculation. It can be used in temperature sensors, voltage and current references, radiation dosimeters and other applications since the MOSFET VT0 dependence on the operation conditions is a very well modeled aspect. Also, it can be used for fabrication process monitoring and process variability compensation, since VT0 is a key parameter for the transistor behavior and modeling. In this thesis, we present three novel circuit topologies, two of them being NMOS VT0 monitors and the last one being a PMOS VT0 monitor. The three structures are resistorless self-biased circuit topologies that present high power supply rejection, low line sensitivity, and allow the direct extraction of the threshold voltage for wide temperature and power supply voltage ranges, with small error. Its design methodology is based on the Unified Current Control Model (UICM), a MOSFET model that is continuous from weak to strong inversion and from triode to saturation regions. The circuits occupy small silicon area, consume just tens of nanoWatts, and can be implemented in any standard digital CMOS process, since they only use MOS transistors (does not need any resistor). The VT0 monitors are used in different applications in order to prove their functionality, and behavior as part of a system. The applications vary from a reference voltage, that presents performance comparable with state-of-the-art works, to a configuration that allows to obtain a lower process variability, in the output of a self-biased circuit that generates a complementary to the absolute temperature (CTAT) voltage. In addition, exploiting the ability to operate as an specific current (ISQ) generator, that the VT0 monitors presented here offer, we introduced a new self-biased circuit that produces a CTAT voltage and is less sensitive to process variations, and can be used in band-gap voltage references.
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Ishibe, Eder Issao. "Projeto de uma fonte de tensão de referência." Universidade de São Paulo, 2014. http://www.teses.usp.br/teses/disponiveis/18/18155/tde-24072014-165540/.

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Neste trabalho é apresentado o projeto de uma fonte de tensão de referência, um circuito capaz de prover uma tensão invariante com a temperatura, a tensão de alimentação e o processo de fabricação. São apresentadas: as equações de funcionamento, os passos para a elaboração da uma topologia final, o dimensionamento dos parâmetros de projeto com o uso de algoritmos metaheurísticos, o desenho do layout e os resultados e análises finais. O projeto emprega a tecnologia CMOS de 0,35 μm com quatro camadas de metal da Austria Micro Systems, em que os VTH0\'s dos transistores NMOS e PMOS, modelo típico, são, respectivamente, 0,5 V e -0,7 V. O circuito de fonte de referência é do tipo bandgap e faz a soma ponderada de correntes proporcionais a temperatura para atingir uma tensão de referência. Obteve-se um circuito típico com 0,5 V de tensão de referência, coeficiente de temperatura de 15 ppm/ºC em intervalo de temperatura de -10 a 90ºC em 1,0 V de tensão de alimentação, regulação de linha de 263 ppm/V em um intervalo de variação de 1,0 V a 2,5 V em 27ºC, 2,7 μA de corrente consumida e área de 0,11 mm². A introdução de um bloco de ajuste de coeficiente de temperatura, com ajuste digital, permite que mais que 90% dos circuitos produzidos tenham um coeficiente de temperatura de até 30 ppm/ºC. As medidas realizadas no trabalho são provenientes de simulações elétricas realizadas com o ELDO e modelos BSIM3v3.
In this work is presented a design of a reference voltage source, circuits capable to provide an invariant voltage regardless of the temperature, power supply and fabrication process. It\'s presented: the operation equations, the steps to elaborate a final topology, the project parameter sizing using a metaheuristic algorithm, the drawing of the layout, and the final results and its analysis. The design employs an AMS-CMOS 0.35 μm technology with four metal levels, whose NMOS and PMOS VTH0\'s for a typical circuit is 0.5 V and -0.7 V. The reference voltage circuit is bandgap and performs a weighted summation of proportional temperature currents to achieve the voltage reference. A typical circuit was obtained with 0.5 V reference voltage, 15 ppm/ºC temperature coefficient in the temperature range of -10 to 90ºC under 1.0 V power supply, 263 ppm/V line regulation in the range of 1.0 V to 2.5 V under 27ºC, 2.7 μA power consumption in a 0.11 mm² area. For a projected circuit its also possible to ensure a temperate coefficient under 30 ppm/ºC, for more than 95% of the produced circuits, employing an adjustment block which ought to be digitally calibrated for each circuit.
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Mácha, Petr. "Návrh převodníku DA s plně diferenčním výstupem v technologii CMOS." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2017. http://www.nusl.cz/ntk/nusl-316964.

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This diploma thesis deals with the design of eight-bit digital to analog coverter with fully differential outputs in technology I3T25 of ON Semiconductor company. The work contains the description of basic structures and characteristics of digital to analog converters. The main focus of the work is to design a converter and auxiliary circuits at the transistor level. The functionality of designed circuits is verified by simulation environment Cadence.
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Miri, Lavasani Seyed Hossein. "Design and phase-noise modeling of temperature-compensated high frequency MEMS-CMOS reference oscillators." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/41096.

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Frequency reference oscillator is a critical component of modern radio transceivers. Currently, most reference oscillators are based on low-frequency quartz crystals that are inherently bulky and incompatible with standard micro-fabrication processes. Moreover, their frequency limitation (<200MHz) requires large up-conversion ratio in multigigahertz frequency synthesizers, which in turn, degrades the phase-noise. Recent advances in MEMS technology have made realization of high-frequency on-chip low phase-noise MEMS oscillators possible. Although significant research has been directed toward replacing quartz crystal oscillators with integrated micromechanical oscillators, their phase-noise performance is not well modeled. In addition, little attention has been paid to developing electronic frequency tuning techniques to compensate for temperature/process variation and improve the absolute frequency accuracy. The objective of this dissertation was to realize high-frequency temperature-compensated high-frequency (>100MHz) micromechanical oscillators and study their phase-noise performance. To this end, low-power low-noise CMOS transimpedance amplifiers (TIA) that employ novel gain and bandwidth enhancement techniques are interfaced with high frequency (>100MHz) micromechanical resonators. The oscillation frequency is varied by a tuning network that uses frequency tuning enhancement techniques to increase the tuning range with minimal effect on the phase-noise performance. Taking advantage of extended frequency tuning range, and on-chip temperature-compensation circuitry is embedded with the sustaining circuitry to electronically temperature-compensate the oscillator. Finally, detailed study of the phase-noise in micromechanical oscillators is performed and analytical phase-noise models are derived.
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Books on the topic "CMOS Voltage Reference"

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CMOS voltage reference: An analytical and practical perspective. Hoboken: IEEE ; Wiley, 2013.

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Kok, Chi-Wah, and Wing-Shan Tam. CMOS Voltage References. Fusionopolis Walk, Singapore: John Wiley & Sons Singapore Pte. Ltd., 2012. http://dx.doi.org/10.1002/9781118275696.

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Lin, San Lwin. CMOS voltage references. 1985.

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Kok, Chi-Wah, and Wing-Shan Tam. CMOS Voltage References: An Analytical and Practical Perspective. Wiley & Sons, Incorporated, John, 2012.

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Kok, Chi-Wah, and Wing-Shan Tam. CMOS Voltage References: An Analytical and Practical Perspective. Wiley & Sons, Incorporated, John, 2012.

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Kok, Chi-Wah, and Wing-Shan Tam. CMOS Voltage References: An Analytical and Practical Perspective. Wiley & Sons, Incorporated, John, 2012.

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Book chapters on the topic "CMOS Voltage Reference"

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Zhou, Qianneng, Hongjuan Li, Li Wang, Qi Li, and Qiulin Zhang. "A Resistor-Less CMOS Voltage Reference." In Advances in Mechanical and Electronic Engineering, 103–7. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-31528-2_17.

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Saidulu, Bellamkonda, Arun Manoharan, Bellamkonda Bhavani, and Jameer Basha Sk. "An Improved CMOS Voltage Bandgap Reference Circuit." In Advances in Intelligent Systems and Computing, 621–29. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-7868-2_59.

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Madeira, Ricardo, and Nuno Paulino. "Design Methodology for an All CMOS Bandgap Voltage Reference Circuit." In IFIP Advances in Information and Communication Technology, 439–46. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-56077-9_43.

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Kulkarni, Priya Vinayak, and Rajashekhar B. Shettar. "A Design of Low Power Resistorless Sub-threshold CMOS Bandgap Voltage Reference." In Communications in Computer and Information Science, 288–300. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-5048-2_23.

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Sarangi, Santunu, Dhananjaya Tripathy, Subhra Sutapa Mahapatra, and Saroj Rout. "A Power- and Area-Efficient CMOS Bandgap Reference Circuit with an Integrated Voltage-Reference Branch." In Lecture Notes in Electrical Engineering, 144–54. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-4775-1_16.

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Yu, Jianhai, and Hui Guo. "Design of a 200-nW 0.8-V Voltage Reference Circuit in All-CMOS Technology." In Wireless and Satellite Systems, 120–30. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-19156-6_12.

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Rahali, Ahmed, Karim El Khadiri, Zakia Lakhliai, Hassan Qjidaa, and Ahmed Tahiri. "Design of a CMOS Bandgap Reference Voltage Using the OP AMP in 180 nm Process." In Digital Technologies and Applications, 1655–62. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-73882-2_150.

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Yuan, Fei. "Low-Power Precision Voltage References." In CMOS Circuits for Passive Wireless Microsystems, 117–72. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-7680-2_5.

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Piri, Amirreza. "The Improvement of Voltage Reference Below 1 V with Low Temperature Dependence and Resistant to Variations of Power Supply in CMOS Technology." In Lecture Notes in Electrical Engineering, 549–63. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-8672-4_41.

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Plassche, Rudy. "Voltage and current references." In CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, 477–84. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3768-4_10.

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Conference papers on the topic "CMOS Voltage Reference"

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Far, Ali. "A 400nW CMOS bandgap voltage reference." In 2013 International Conference on Electrical, Electronics and System Engineering (ICEESE). IEEE, 2013. http://dx.doi.org/10.1109/iceese.2013.6895035.

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Olivera, Fabian, and Antonio Petraglia. "Adjustable Output CMOS Voltage Reference Design." In 2020 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2020. http://dx.doi.org/10.1109/iscas45731.2020.9181000.

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Chao Feng, Jinhui Wang, Wei Wu, Ligang Hou, and Jianbo Kang. "CMOS 1.2V bandgap voltage reference design." In 2013 IEEE 10th International Conference on ASIC (ASICON 2013). IEEE, 2013. http://dx.doi.org/10.1109/asicon.2013.6812039.

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Ashrafi, S. F., S. M. Atarodi, and M. Chahardori. "New low voltage, high PSRR, CMOS bandgap voltage reference." In 2008 IEEE International SOC Conference (SOCC). IEEE, 2008. http://dx.doi.org/10.1109/socc.2008.4641542.

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de Carvalho Ferreira, Luis Henrique, and Tales Cleber Pimenta. "A CMOS voltage reference for ultra low-voltage applications." In 2005 12th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2005). IEEE, 2005. http://dx.doi.org/10.1109/icecs.2005.4633385.

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Zhang, Bolun, Xiaole Cui, Yifan Zhang, Chun Yang, Ying Xiao, and Xinnan Lin. "A 0.8V CMOS bandgap voltage reference design." In 2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC). IEEE, 2015. http://dx.doi.org/10.1109/edssc.2015.7285124.

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Harb, Shadi M., William R. Eisenstadt, and Robert M. Fox. "A sub-1V CMOS voltage reference generator." In 2011 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2011. http://dx.doi.org/10.1109/iscas.2011.5937712.

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Wadhwa, Sanjay K. "A low voltage CMOS bandgap reference circuit." In 2008 IEEE International Symposium on Circuits and Systems - ISCAS 2008. IEEE, 2008. http://dx.doi.org/10.1109/iscas.2008.4542012.

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Lourenco, Nuno, Luis Nero Alves, and Jose Luis Cura. "A multi-valued 350nm CMOS voltage reference." In 2012 19th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2012). IEEE, 2012. http://dx.doi.org/10.1109/icecs.2012.6463668.

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Kunming Cai, Jili Tao, and Qixin He. "Design of high precision CMOS voltage reference." In 2010 Second Pacific-Asia Conference on Circuits,Communications and System (PACCS). IEEE, 2010. http://dx.doi.org/10.1109/paccs.2010.5626970.

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