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Kevin, Tom. "Sub-1V Curvature Compensated Bandgap Reference." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2585.
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This thesis investigates the possibility of realizing bandgap reference crcuits for processes having sub-1V supply voltage. With the scaling of gate oxide thickness supply voltage is getting reduced. But the threshold voltage of transistors is not getting scaled at the same rate as that of the supply voltage. This makes it difficult to incorporate conventional designs of bandgap reference circuits to processeshaving near to 1V supply voltage. In the first part of the thesis a comprehensive study on existing low voltage bandgap reference circuits is done. Using these ideas a low-power, low-voltage bandgap reference circuit is designed in the second part of the thesis work.
The proposed bandgap reference circuit is capable of generating a reference voltage of 0.730V. The circuit is implemented in 0.18µm standard CMOS technology and operates with 0.9V supply voltage, consuming 5µA current. The circuit achieves 7 ppm/K of temperature coefficient with supply voltage range from 0.9 to 1.5V and temperature range from 0 to 60C.
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Colombo, Dalton Martini. "Bandgap voltage references in submicrometer CMOS technology." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2009. http://hdl.handle.net/10183/16136.
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Referências de tensão são blocos fundamentais em uma série de aplicações de sinais mistos e de rádio frequência, como por exemplo, conversores de dados, PLL's e conversores de potência. A implementação CMOS mais usada para referências de tensão é o circuito Bandgap devido sua alta previbilidade, e baixa dependência em relação à temperatura e tensão de alimentação. Este trabalho estuda aplicação de Referência de Tensão Bandgap. O princípio, as topologias tradicionalmente usadas para implementar este método e as limitações que essas arquiteturas sofrem são investigadas. Será também apresentada uma pesquisa das questões recentes envolvendo alta precisão, operação com baixa tensão de alimentação e baixa potência, e ruído de saída para as referências Bandgap fabricadas em tecnologias submicrométricas. Além disso, uma investigação abrangente do impacto causado pelo o processo da fabricação e do ruído no desempenho da referência é apresentada. Será mostrado que o ruído de saída pode limitar a precisão dos circuitos Bandgap e seus circuitos de ajuste. Para desenvolver nosso trabalho, três Referências Bandgap foram projetadas utilizando o processo IBM 7RF 0.18 micra com uma tensão de alimentação de 1.8V. Também foram projetados os leiautes desses circuitos para prover informações pósleiaute extraídos e resultados de simulação elétrica. Este trabalho provê uma discussão de algumas topologias e das práticas de projeto para referências Bandgap.A Voltage Reference is a pivotal block in several mixed-signal and radio-frequency applications, for instance, data converters, PLL's and power converters. The most used CMOS implementation for voltage references is the Bandgap circuit due to its highpredictability, and low dependence of the supply voltage and temperature of operation. This work studies the Bandgap Voltage References (BGR). The most relevant and the traditional topologies usually employed to implement Bandgap Voltage References are investigated, and the limitations of these architectures are discussed. A survey is also presented, discussing the most relevant issues and performance metrics for BGR, including, high-accuracy, low-voltage and low-power operation, as well as the output noise of Bandgap References fabricated in submicrometer technologies. Moreover, a comprehensive investigation on the impact of fabrication process effects and noise on the reference voltage is presented. It is shown that output noise can limit the accuracy of the BGR and trim circuits. To support and develop our work, three BGR´s were designed using the IBM 0.18 Micron 7RF process with a supply voltage of 1.8 V. The layouts of these circuits were also designed to provide post-extracted layout information and electrical simulation results. This work provides a comprehensive discussion on the structure and design practices for Bandgap References.
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Gupta, Vishal. "An accurate, trimless, high PSRR, low-voltage, CMOS bandgap reference IC." Diss., Available online, Georgia Institute of Technology, 2007, 2007. http://etd.gatech.edu/theses/available/etd-07052007-073154/.
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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.Ayazi, Farrokh, Committee Member ; Rincon-Mora, Gabriel, Committee Chair ; Bhatti, Pamela, Committee Member ; Leach, W. Marshall, Committee Member ; Morley, Thomas, Committee Member.
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Komark, Stina. "Design of an integrated voltage regulator." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1711.
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Many analog systems need a stable power supply voltage that does not vary with temperature and time in order to operate properly. In a battery operated system the battery voltage is not stable, e.g. it decreases with decreasing temperature and with ageing. In that case a voltage regulator must be used, that regulates the battery voltage and generates a stable supply voltage to power other circuitry.
In this thesis a voltage regulator to be used in a battery operated system has been designed which meets the given specification of stability and power capabilities. A voltage reference, which is a commonly used devise in analog circuits, was also designed. The role of a reference voltage in an electrical system is the same as for a tuning fork in a musical ensemble; to set a standard to which other voltages are compared.
A functionality to detect when the lifetime of the battery is about to run out was also developed.
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Kotrč, Václav. "Napěťové reference v bipolárním a CMOS procesu." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2015. http://www.nusl.cz/ntk/nusl-221111.
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This diploma thesis deals with precise design of Brokaw BandGap voltage reference comparing with MOS references. There is STEP BY STEP separation and analysis of proposed devices, using Monte Carlo analysis. There are also presented the methods for achieving a lower deviation of the output voltage for yielding device, which needs no trimming.
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Mattia, Neto Oscar Elisio. "NanoWatt resistorless CMOS voltage references for Sub-1 V applications." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/107131.
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Referências de tensão integradas sempre foram um bloco fundamental de qualquer sistema eletrônico e um importante tópico de pesquisa que tem sido estudado extensivamente nos últimos 50 anos. Uma tensão de referência é um circuito que provê uma tensão estável com baixa sensibilidade a variações em temperatura, alimentação, carga, características do processo de fabricação e tensões mecânicas de encapsulamento. Elas são normalmente implementadas através da soma ponderada de dois fenômenos físicos diferentes, com comportamentos em temperatura opostos. Normalmente, a tensão térmica, relacionada à constante de Boltzmann e à carga do elétron, fornece uma dependência positiva com temperatura, enquanto que a tensão base-emissor VBE de um transistor bipolar ou a tensão de limiar de um MOSFET fornece o termo complementar. Um bloco auxiliar é às vezes utilizado para fornecer as correntes de polarização do circuito, e outros blocos adicionais implementam a soma ponderada. A evolução da tecnologia de processos é o principal fator para aplicações em baixa tensão, enquanto que a emergência de dispositivos portáteis operados a bateria, circuitos biomédicos implantáveis e dispostivos de captura de energia do ambiente restringem cada circuito a consumir o mínimo possivel. Portanto, alimentações abaixo de 1 V e consumos na ordem de nanoWatts se tornaram características fundamentais de tais circuitos. Contudo, existem diversos desafios ao projetar referências de tensão de alta exatidão em processos CMOS modernos sob essas condições. As topologias tradicionais não são adequadas pois elas provêm uma referência de tensão acima de 1 V, e requerem resistências da ordem de G para atingir tão baixo consumo de potência, ocupando assim uma grande área de silício. Avanços recentes atingiram tais níveis de consumo de potência, porém com limitada exatidão, custosos procedimentos de calibração e grande área ocupada em silício. Nesta dissertação apresentam-se duas novas topologias de circuitos: uma tensão de junção bipolar com compensação de curvatura que não utiliza resistores e é auto-polarizada; e um circuito de referência bandgap sem resistores que opera abaixo de 1 V (também chamado de sub-bandgap). Ambos circuitos operam com consumo na ordem de nanoWatts e ocupam pequenas áreas de silício. Resultados de simulação para dois processos diferentes, 180 nm e 130 nm, e resultados experimentais de uma rodada de fabricação em 130 nm apresentam melhorias sobre tais limitações, mantendo as características desejadas de não conter resistores, ultra baixo consumo, baixa tensão de alimentação e áreas muito pequenas.Integrated voltage references have always been a fundamental block of any electronic system, and an important research topic that has been extensively studied in the past 50 years. A voltage reference is a circuit that provides a stable voltage with low sensitivity to variations in temperature, supply, load, process characteristics and packaging stresses. They are usually implemented through the weighted sum of two independent physical phenomena with opposite temperature dependencies. Usually the thermal voltage, related to the Boltzmann’s constant and the electron charge, provides a positive temperature dependence, while the silicon bandgap voltage or a MOSFET’s threshold voltage provide the complementary term. An auxiliary biasing block is sometimes necessary to provide the necessary currents for the circuit to work, and additional blocks implement the weighted sum. The scaling of process technologies is the main driving factor for low voltage operation, while the emergence of portable battery-operated, implantable biomedical and energy harvesting devices mandate that every circuit consume as little power as possible. Therefore, sub-1 V supplies and nanoWatt power have become key characteristics for these kind of circuits, but there are several challenges when designing high accuracy voltage references in modern CMOS technologies under these conditions. The traditional topologies are not suitable because they provide a reference voltage above 1 V, and to achieve such power consumption levels would require G resistances, that occupy a huge silicon area. Recent advances have achieved these levels of power consumption but with limited accuracy, expensive calibration procedures and large silicon area.
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Castellanos, Juan José Carrillo. "Projeto de uma fonte de tensão de referência CMOS usando programação geométrica." Universidade de São Paulo, 2010. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-01032011-120430/.
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Nesta dissertação é apresentada a aplicação da programação geométrica no projeto de uma fonte de tensão de referência de baixa tensão de alimentação que pode ser integrada em tecnologias padrões CMOS. Também são apresentados os resultados experimentais de um projeto da fonte de bandgap feito por um método de projeto convencional, cuja experiência motivou e ajudou ao desenvolvimento da formulação do programa geométrico proposta neste trabalho. O programa geométrico desenvolvido nesta dissertação otimiza o desempenho da fonte de bandgap e agiliza seu tempo de projeto. As expressões matemáticas que descrevem o funcionamento e as principais especificações da fonte de bandgap foram geradas e adaptadas ao formato de um programa geométrico. A compensação da temperatura, o PSRR, o consumo de corrente, a área, a tensão de saída e a sua variação por causa da tensão de offset do OTA, e a estabilidade são as principais especificações deste tipo de fonte de tensão de referência e fazem parte do programa geométrico apresentado neste trabalho. Um exemplo do projeto usando o programa geométrico formulado neste trabalho, mostra a possibilidade de projetar a fonte de bandgap em alguns minutos com erros baixos entre os resultados do programa geométrico e de simulação.This work presents the application of geometric programming in the design of a CMOS low-voltage bandgap voltage reference source. Test results of a bandgap voltage reference designed via a conventional method are showed, this design experience motivated and helped to formulate the geometric program developed in this work. The geometric program developed in this work optimizes the bandgap source performance and speeds up the design time. The mathematical expressions that describe the bandgap source functioning and specifications were developed and adapted in the geometric program format. The temperature compensation, the PSRR, the current consumption, the area, the output voltage and its variations under the operational tranconductance amplifier offset voltage, and the stability are the main specifications of this type of bandgap reference source and they are included into the geometric program presented in this work. An example of the design using the geometric program formulated in this work, shows the possibility of designing the bandgap source in a few minutes with low errors between the geometric program results and the simulation results.
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Zimouche, Hakim. "Capteur de vision CMOS à réponse insensible aux variations de température." Phd thesis, Université de Grenoble, 2011. http://tel.archives-ouvertes.fr/tel-00656381.
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Les capteurs d'images CMOS sont de plus en plus utilisés dans le domaine industriel : la surveillance, la défense, le médical, etc. Dans ces domaines, les capteurs d'images CMOS sont exposés potentiellement à de grandes variations de température. Les capteurs d?images CMOS, comme tous les circuits analogiques, sont très sensibles aux variations de température, ce qui limite leurs applications. Jusqu'à présent, aucune solution intégrée pour contrer ce problème n'a été proposée. Afin de remédier à ce défaut, nous étudions, dans cette thèse, les effets de la température sur les deux types d'imageurs les plus connus. Plusieurs structures de compensation sont proposées. Elles reprennent globalement les trois méthodes existantes et jamais appliquées aux capteurs d'images. La première méthode utilise une entrée au niveau du pixel qui sera modulée en fonction de l'évolution de la température. La deuxième méthode utilise la technique ZTC (Zero Température Coefficient). La troisième méthode est inspirée de la méthode de la tension de référence bandgap. Dans tous les cas, nous réduisons de manière très intéressante l'effet de la température et nous obtenons une bonne stabilité en température de -30 à 125°C. Toutes les solutions proposées préservent le fonctionnement initial de l'imageur. Elles n'impactent également pas ou peu la surface du pixel
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Chan, Yiu Fai. "A new curvature-compensation technique for bandgap voltage reference." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape17/PQDD_0003/MQ28924.pdf.
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Holman, William Timothy. "A low noise CMOS voltage reference." Diss., Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/14968.
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Herbst, Steven (Steven G. ). "A low-noise bandgap voltage reference employing dynamic element matching." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/77071.
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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 109).
Bandgap voltages references are widely used in IC design, but are sensitive to low-frequency noise and component mismatch. This thesis describes the design and testing of a new IC voltage reference that targets these issues through three dynamic element matching (DEM) subsystems. The first is a chopper OTA, and the second two are component rotation schemes: one to exchange the positions of two critical resistors, and the second to cycle through all BJTs, periodically selecting each to participate as the "1" transistor of the N:1 bandgap ratio. Practical designs that address the various switching issues typically associated with DEM, such as glitch and clock drift, are described. Analytic expressions for the effects of noise and mismatch throughout the bandgap reference are derived, along with expressions for calculating the improvement that can be achieved by DEM. A test chip was implemented in a 0.25[mu]m BiCMOS process; with its three DEM subsystems enabled it is shown to achieve a 20x 1/f noise improvement and a 34x mismatch error improvement.
by Steven Herbst.
M.Eng.
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Digvadekar, Ashish A. "A sub 1 V bandgap reference circuit /." Online version of thesis, 2005. https://ritdml.rit.edu/dspace/handle/1850/2595.
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Silva, João Gonçalo Clemente da. "Project of a bandgap voltage reference and a temperature sensor for "energy harvest" systems." Master's thesis, Faculdade de Ciências e Tecnologia, 2013. http://hdl.handle.net/10362/11330.
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Dissertação para obtenção do Grau de Mestre em
Engenharia Electrotécnica e ComputadoresThe objective of this thesis is to study the behaviour of a bandgap voltage reference and develop it in order to be more efficient than the existing ones. In this case having applicability in energy harvest, the main approach for this circuit is to reduce the power dissipation and at the same time guarantee a stable of the reference voltage. This can be achieved through the utilization of MOS transistors which can work with a lower voltage then bipolar transistors. The reference voltage circuit present in this thesis can work with a supply voltage as low as 500 mV. In energy harvest systems besides the need to work with extremely low voltages, the sensitivity of the signals is very high, to temperature variation. So it was also important to work with an extended ranges of temperature. For this work it was also developed a temperature sensor so that it has applicability in various fields. The sensor works by currents generated by the bandgap voltage reference, having similar results to a dual slope integrating analogue-to-digital converter, although its operation and logic are quite different. The proposed solution is to implement a reference voltage generator powered by a voltage source of 500 mV, with a consumption of about 7 W. Having a temperature coefficient slightly below 74 ppm/ C and a temperature sensor with linearity quite satisfactory.
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Chaput, Simon. "Convertisseur DC-DC CMOS haut voltage pour actuateurs MEMS/MOEMS électrostatiques." Mémoire, Université de Sherbrooke, 2013. http://hdl.handle.net/11143/8063.
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La demande pour des appareils portables multifonctionnels encourage les manufacturiers à intégrer des microsystèmes électromécaniques (MEMS) ou optoélectromécaniques (MOEMS) à leurs produits pour réaliser de nouvelles fonctions ; les pico projecteurs constituent un excellent exemple. Or, dans le but d'utiliser ce type de composants, des tensions de polarisation variant entre 100 V et 300 V sont parfois nécessaires. La génération de ces tensions à partir de la pile de l'appareil exige des convertisseurs continu-continu (DC-DC) miniatures procurant un gain de tension de l'ordre de 100. C'est dans ce contexte général que ce projet réalisé pour Teledyne DALSA, un manufacturier de MEMS et concepteur de circuits intégrés haut voltage, a été réalisé. En intégrant ce circuit à ses circuits de contrôle de MEMS, Teledyne DALSA sera ainsi en mesure de proposer des systèmes plus complets à ses clients. Ce mémoire présente la conception d'un convertisseur DC-DC dans la technologie CO8G CMOS/DMOS haut voltage de Teledyne DALSA. Pour que la solution développée soit assez flexible, le circuit permet un ajustement de la tension de sortie entre 100 V et 300 V pour une puissance de sortie inférieure ou égale à 210 mW à partir d'une tension de batterie entre 2,7 V et 5,5 V. Afin de permettre une longue autonomie des appareils portables, ce projet vise une efficacité de transfert d'énergie de 70 % à la puissance de sortie typique de 75 mW à 220 V. De plus, la solution développée doit être la plus petite possible. À partir de l'état de l'art des circuits de gestion de l'alimentation, ce mémoire présente une conception haut niveau du circuit basée sur des raisonnements et calculs mathématiques simples. Bâtissant sur ces concepts, ce travail détaille la conception des composants de puissance, du circuit de puissance et du contrôleur nécessaire à la réalisation de ce projet. Bien que certaines difficultés, notamment le niveau moyen de l'oscillation de la tension de sortie de 1,6 V, ne permettent pas d'utiliser dès maintenant le circuit développé dans une application commerciale, la solution proposée démontre une amélioration entre 15 % et 43 % de l'efficacité de conversion par rapport au circuit flyback actuel de Teledyne DALSA. De plus, la solution proposée intègre un transistor de puissance 78 % plus petit que les transistors standards disponibles dans la technologie CO8G. Étant donnée l'innovation du circuit présenté au niveau des composants de puissance, du circuit de puissance et du contrôleur, ces résultats de l'implémentation initiale laissent envisager un bon potentiel pour cette architecture après une révision.
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Souza, Flávio Queiroz de [UNESP]. "Projeto de uma referência de tensão com baixa susceptibilidade a interferência eletromagnética (EMI)." Universidade Estadual Paulista (UNESP), 2011. http://hdl.handle.net/11449/87063.
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Referências de tensão integradas com baixa sensibilidade à temperatura, tensão de a- limentação e eventos transitórios são componentes críticos na maioria dos circuitos integra- dos. Neste trabalho, além das restrições costumeiras, foi adicionada a preocupação com a in- terferência eletromagnética a qual vem ganhando muita importância devido a crescente polui- ção eletromagnética no ambiente. Assim, neste trabalho, propõe-se o projeto de uma referên- cia de tensão tipo bandgap com baixa susceptibilidade a interferência eletromagnética (EMI). O projeto deste circuito baseia-se na soma de duas correntes (referência de tensão baseada em corrente), uma com coeficiente complementar a temperatura absoluta (CTAT) e outra com coeficiente proporcional à temperatura absoluta (PTAT), aplicada sobre um resistor. Neste projeto, a susceptibilidade a interferência eletromagnética de uma referência de tensão band- gap é estudada por meio de simulação. Projetada para ser fabricada com a tecnologia CMOS 0,35 μm da AMS (Autriamicrosystems), a referência forneceu uma tensão de referência está- vel de 1,354 V em sua saída operando normalmente na faixa de temperatura de -40 a 150oC. Quando submetido à EMI, o circuito exibiu apenas 24,7 mV (quando filtros capacitivos são incluído) de offset induzido, para um sinal de interferência variando de 150 kHz a 1 GHz
Integrated voltage references with low sensitivity to temperature, supply voltage and transient events are critical requirements in the most of integrated circuits. In this work, be- sides the usual restrictions, was added to concern with electromagnetic interference which is gaining much importance due to increasing electromagnetic pollution on the environment. So, in this work, proposes the design of a bandgap voltage reference with low susceptibility to electromagnetic interference (EMI) is proposed. The design of the circuit is based on the sum of two currents (current-based voltage reference), one with coefficient complementary to ab- solute temperature (CTAT) and the other with coefficient proportional to absolute temperature (PTAT) into a resistor. In this work, the susceptibility to electromagnetic interference in a bandgap voltage reference is evaluated by simulations. Designed to be implemented in AMS (Autriamicrosystems) 0,35 μm CMOS process, the reference provides a stable voltage refer- ence equal to 1,354 V in the output working properly in the temperature range of -40 to 150oC. When EMI is injected, the circuit exhibits only 24,7 mV (when capacitive filters are included) of induced offset, for an interference signal varying in the frequency range of 150 kHz to 1 GHz
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Souza, Flávio Queiroz de. "Projeto de uma referência de tensão com baixa susceptibilidade a interferência eletromagnética (EMI) /." Ilha Solteira : [s.n.], 2011. http://hdl.handle.net/11449/87063.
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Orientador: Nobuo OkiBanca: Cláudio Kitano
Banca: Márcio Barbosa Lucks
Resumo: Referências de tensão integradas com baixa sensibilidade à temperatura, tensão de a- limentação e eventos transitórios são componentes críticos na maioria dos circuitos integra- dos. Neste trabalho, além das restrições costumeiras, foi adicionada a preocupação com a in- terferência eletromagnética a qual vem ganhando muita importância devido a crescente polui- ção eletromagnética no ambiente. Assim, neste trabalho, propõe-se o projeto de uma referên- cia de tensão tipo bandgap com baixa susceptibilidade a interferência eletromagnética (EMI). O projeto deste circuito baseia-se na soma de duas correntes (referência de tensão baseada em corrente), uma com coeficiente complementar a temperatura absoluta (CTAT) e outra com coeficiente proporcional à temperatura absoluta (PTAT), aplicada sobre um resistor. Neste projeto, a susceptibilidade a interferência eletromagnética de uma referência de tensão band- gap é estudada por meio de simulação. Projetada para ser fabricada com a tecnologia CMOS 0,35 μm da AMS (Autriamicrosystems), a referência forneceu uma tensão de referência está- vel de 1,354 V em sua saída operando normalmente na faixa de temperatura de -40 a 150oC. Quando submetido à EMI, o circuito exibiu apenas 24,7 mV (quando filtros capacitivos são incluído) de offset induzido, para um sinal de interferência variando de 150 kHz a 1 GHz
Abstract: Integrated voltage references with low sensitivity to temperature, supply voltage and transient events are critical requirements in the most of integrated circuits. In this work, be- sides the usual restrictions, was added to concern with electromagnetic interference which is gaining much importance due to increasing electromagnetic pollution on the environment. So, in this work, proposes the design of a bandgap voltage reference with low susceptibility to electromagnetic interference (EMI) is proposed. The design of the circuit is based on the sum of two currents (current-based voltage reference), one with coefficient complementary to ab- solute temperature (CTAT) and the other with coefficient proportional to absolute temperature (PTAT) into a resistor. In this work, the susceptibility to electromagnetic interference in a bandgap voltage reference is evaluated by simulations. Designed to be implemented in AMS (Autriamicrosystems) 0,35 μm CMOS process, the reference provides a stable voltage refer- ence equal to 1,354 V in the output working properly in the temperature range of -40 to 150oC. When EMI is injected, the circuit exhibits only 24,7 mV (when capacitive filters are included) of induced offset, for an interference signal varying in the frequency range of 150 kHz to 1 GHz
Mestre
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Kacafírek, Jiří. "Návrh přesné napěťové reference v ACMOS procesu." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2010. http://www.nusl.cz/ntk/nusl-218682.
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In this thesis the principle of voltage reference especially bangap reference is described. Below are described two circuits of this type designed in ACMOS process. There is handmade evaluation of error analysis to identify main error contributors and also monte-carlo simulation. Also statistical analysis is made on the circuit. Results of all methods are compared. Error of reference voltage is compared for both circuits. Circuit with bigger error is optimized to achieve a better precision. Obtained results showed a good agreement of all methods, which evidences importance of hand error evaluation.
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Caicedo, Jhon Alexander Gomez. "CMOS low-power threshold voltage monitors circuits and applications." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2016. http://hdl.handle.net/10183/144080.
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Um monitor de tensão de limiar (VT0) é um circuito que, idealmente, entrega o valor do VT0 como uma tensão na saída, para uma determinada faixa de temperatura, sem a necessidade de polarização externa, configurações paramétricas, ajuste de curvas ou qualquer cálculo subsequente. Estes circuitos podem ser usados em sensores de temperatura, referências de tensão e corrente, dosímetros de radiação e outras aplicações, uma vez que a dependência do VT0 nas condições de operação é um aspecto bem modelado. Além disso, estes circuitos podem ser utilizados para monitoramento de processos de fabricação e para compensação da variabilidade do processo, uma vez que o VT0 é um parâmetro chave para o comportamento do transistor e sua modelagem. Nesta tese, são apresentadas três novas topologias de circuitos, duas são monitores de VT0 NMOS e a terceira é um monitor de VT0 PMOS. As três estruturas são topologias de circuito auto-polarizadas que não utilizam resistências, e apresentam alta rejeição a variações na alimentação, baixa sensibilidade de Linea, e permitem a extração direta da tensão de limiar para grandes intervalos de temperatura e de tensão de alimentação, com pequeno erro. Sua metodologia de projeto é baseada no modelo unificado controlado por corrente (UICM), um modelo MOSFET que é contínuo, desde o nível de inversão fraca a forte e para as regiões de operação de triodo e saturação. Os circuitos ocupam uma pequena área de silício, consomem apenas dezenas de nanowatts, e podem ser implementados em qualquer processo padrão CMOS digital, uma vez que só utilizam transistores MOS (não precisa de nenhum resistor). Os monitores de VT0 são utilizados em diferentes aplicações, a fim de investigar a sua funcionalidade e comportamento como parte de um sistema. As aplicações variam de uma tensão de referência, que apresenta um desempenho comparável ao estado da arte, para uma configuração que permite obter uma menor variabilidade com processo na saída de um circuito auto-polarizado que gera um tensão CTAT. Além disso, explorando a capacidade de funcionar como um gerador de corrente específica (ISQ) que os monitores de VT0 aqui apresentados oferecem, introduz-se um novo circuito auto-polarizado que gera um tensão CTAT, que é menos sensível a variações de processo, e pode ser usado em referências de tensão band-gap.A threshold voltage (VT0) monitor is a circuit that ideally delivers the estimated VT0 value as a voltage at its output, for a given temperature range, without external biases, parametric setups, curve fitting or any subsequent calculation. It can be used in temperature sensors, voltage and current references, radiation dosimeters and other applications since the MOSFET VT0 dependence on the operation conditions is a very well modeled aspect. Also, it can be used for fabrication process monitoring and process variability compensation, since VT0 is a key parameter for the transistor behavior and modeling. In this thesis, we present three novel circuit topologies, two of them being NMOS VT0 monitors and the last one being a PMOS VT0 monitor. The three structures are resistorless self-biased circuit topologies that present high power supply rejection, low line sensitivity, and allow the direct extraction of the threshold voltage for wide temperature and power supply voltage ranges, with small error. Its design methodology is based on the Unified Current Control Model (UICM), a MOSFET model that is continuous from weak to strong inversion and from triode to saturation regions. The circuits occupy small silicon area, consume just tens of nanoWatts, and can be implemented in any standard digital CMOS process, since they only use MOS transistors (does not need any resistor). The VT0 monitors are used in different applications in order to prove their functionality, and behavior as part of a system. The applications vary from a reference voltage, that presents performance comparable with state-of-the-art works, to a configuration that allows to obtain a lower process variability, in the output of a self-biased circuit that generates a complementary to the absolute temperature (CTAT) voltage. In addition, exploiting the ability to operate as an specific current (ISQ) generator, that the VT0 monitors presented here offer, we introduced a new self-biased circuit that produces a CTAT voltage and is less sensitive to process variations, and can be used in band-gap voltage references.
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Bubla, Jiří. "Band Gap - přesná napěťová reference." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-217808.
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This diploma thesis is specialized on a design of a high accuracy voltage reference Bandgap. A very low temperature coefficient and output voltage approx. 1,205V are the main features of this circuit. The paper contains a derivation of the Bandgap principle, examples of realizations of the circuits and methods of compensation temperature dependence and manufacture process, design of Brokaw and Gilbert reference, design of a testchip and measurement results.
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Ishibe, Eder Issao. "Projeto de uma fonte de tensão de referência." Universidade de São Paulo, 2014. http://www.teses.usp.br/teses/disponiveis/18/18155/tde-24072014-165540/.
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Neste trabalho é apresentado o projeto de uma fonte de tensão de referência, um circuito capaz de prover uma tensão invariante com a temperatura, a tensão de alimentação e o processo de fabricação. São apresentadas: as equações de funcionamento, os passos para a elaboração da uma topologia final, o dimensionamento dos parâmetros de projeto com o uso de algoritmos metaheurísticos, o desenho do layout e os resultados e análises finais. O projeto emprega a tecnologia CMOS de 0,35 μm com quatro camadas de metal da Austria Micro Systems, em que os VTH0\'s dos transistores NMOS e PMOS, modelo típico, são, respectivamente, 0,5 V e -0,7 V. O circuito de fonte de referência é do tipo bandgap e faz a soma ponderada de correntes proporcionais a temperatura para atingir uma tensão de referência. Obteve-se um circuito típico com 0,5 V de tensão de referência, coeficiente de temperatura de 15 ppm/ºC em intervalo de temperatura de -10 a 90ºC em 1,0 V de tensão de alimentação, regulação de linha de 263 ppm/V em um intervalo de variação de 1,0 V a 2,5 V em 27ºC, 2,7 μA de corrente consumida e área de 0,11 mm². A introdução de um bloco de ajuste de coeficiente de temperatura, com ajuste digital, permite que mais que 90% dos circuitos produzidos tenham um coeficiente de temperatura de até 30 ppm/ºC. As medidas realizadas no trabalho são provenientes de simulações elétricas realizadas com o ELDO e modelos BSIM3v3.In this work is presented a design of a reference voltage source, circuits capable to provide an invariant voltage regardless of the temperature, power supply and fabrication process. It\'s presented: the operation equations, the steps to elaborate a final topology, the project parameter sizing using a metaheuristic algorithm, the drawing of the layout, and the final results and its analysis. The design employs an AMS-CMOS 0.35 μm technology with four metal levels, whose NMOS and PMOS VTH0\'s for a typical circuit is 0.5 V and -0.7 V. The reference voltage circuit is bandgap and performs a weighted summation of proportional temperature currents to achieve the voltage reference. A typical circuit was obtained with 0.5 V reference voltage, 15 ppm/ºC temperature coefficient in the temperature range of -10 to 90ºC under 1.0 V power supply, 263 ppm/V line regulation in the range of 1.0 V to 2.5 V under 27ºC, 2.7 μA power consumption in a 0.11 mm² area. For a projected circuit its also possible to ensure a temperate coefficient under 30 ppm/ºC, for more than 95% of the produced circuits, employing an adjustment block which ought to be digitally calibrated for each circuit.
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Colombo, Dalton Martini. "Design of analog integrated circuits aiming characterization of radiation and noise." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/133731.
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Esta tese de doutorado trata de dois desafios que projetistas de circuitos integrados analógicos enfrentam quando estimando a confiabilidade de transistores fabricados em modernos processos CMOS: radiação e ruído flicker. Em relação a radiação, o foco desde trabalho é a Dose Total Ionizante (TID): acumulação de dose ionizante (elétrons e prótons) durante um longo período de tempo nas camadas isolantes dos dispositivos, então resultando na degradação dos parâmetros elétricos (por exemplo, a tensão de limiar e as correntes de fuga). Este trabalho apresenta um caso de estudo composto por circuitos referência tensões de baseados na tensão de bandgap e na tensão de limiar dos transistores. Esses circuitos foram fabricados em uma tecnologia comercial CMOS de 130 nm. Um chip contendo os circuitos foi irradiado usando raio gama de uma fonte de cobalto (60 Co), e o impacto dos efeitos da radiação até uma dose de 490 krad nas tensões de saída é apresentado. Foi verificado que o impacto da radiação foi similar ou até mesmo mais severo que os efeitos causados pelo processo de fabricação para a maior parte dos circuitos projetados. Para as referências baseadas na tensão de bandgap implementadas com transistores de óxido fino e grosso, a variação na tensão de saída causada pela radiação foi de 5.5% e 15%, respectivamente. Para as referências baseadas na tensão de limiar, a variação da tensão de saída foi de 2% a 15% dependendo da topologia do circuito. Em relação ao ruído, o foco desta tese é no ruído flicker do transitor MOS quando este está em operação ciclo-estacionária. Nesta condição, a tensão no terminal da porta está constantemente variando durante a operação e o ruído flicker se torna uma função da tensão porta-fonte e não é precisamente estimado pelos tradicionais modelos de ruído flicker dos transistores MOS. Esta tese apresenta um caso de estudo composto por osciladores de tensão (topologia baseada em anel e no tanque LC) projetados em processos 45 e 130 nm. A frequência de oscilação e sua dependência em relação à polarização do substrato dos transistores foi investigada. Considerando o oscilador em anel, a média da variação da frequência de oscilação causada pela variação da tensão de alimentação e da polarização do substrato foi 495 kHz/mV e 81 kHz/mV, respectivamente. A média da frequência de oscilação é de 103,4 MHz e a média do jitter medido para 4 amostras é de 7.6 ps. Para o tanque LC, a frequência de oscilação medida é de 2,419 GHz e sua variação considerando 1 V de variação na tensão de substrato foi de aproximadamente 0,4 %.This thesis is focused on two challenges faced by analog integrated circuit designers when predicting the reliability of transistors implemented in modern CMOS processes: radiation and noise. Regarding radiation, the concern of this work is the Total Ionizing Dose (TID): accumulation of ionizing dose deposited (electrons and protons) over a long time in insulators leading to degradation of electrical parameters of transistors (e.g. threshold voltage and leakage). This work presents a case-study composed by bandgap-based and threshold voltagebased voltage reference circuits implemented in a commercial 130 nm CMOS process. A chip containing the designed circuits was irradiated through γ-ray Cobalt source (60 Co) and the impact of TID effects up to 490 krad on the output voltages is presented. It was found that the impact of radiation on the output voltage accuracy was similar or more severe than the variation caused by the process variability for most of the case-study circuits. For the bandgap-based reference implemented using thin-oxide and thick-oxide transistors, TID effects result in a variation of the output voltage of 5.5 % and 12%, respectively. For the threshold voltage references, the output variation was between 2% and 15% depending on the circuit topology. Regarding noise, the concern of this work is the transistor flicker noise under cyclostationary operation, that is, when the voltage at transistor gate terminal is constantly varying over time. Under these conditions, the flicker noise becomes a function of VGS; and its is not accurately predicted by traditional transistor flicker noise models. This thesis presents a case-study composed by voltage oscillators (inverter-based ring and LC-tank topologies) implemented in 45 and 130 nm CMOS processes. The oscillation frequency and its dependency on the bulk bias were investigated. Considering the ring-oscillator, the average oscillation frequency variation caused by supply voltage and bulk bias variation are 495 kHz/mV and 81 kHz/mV, respectively. The average oscillation frequency is 103.4 MHz for a supply voltage of 700 mV, and the measured averaged period jitter for 4 measured samples is 7.6 ps. For the LC-tank, the measured oscillation frequency was 2.419 GHz and the total frequency variation considering 1 V of bulk bias voltage was only ~ 0.4 %.
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Mácha, Petr. "Návrh převodníku DA s plně diferenčním výstupem v technologii CMOS." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2017. http://www.nusl.cz/ntk/nusl-316964.
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This diploma thesis deals with the design of eight-bit digital to analog coverter with fully differential outputs in technology I3T25 of ON Semiconductor company. The work contains the description of basic structures and characteristics of digital to analog converters. The main focus of the work is to design a converter and auxiliary circuits at the transistor level. The functionality of designed circuits is verified by simulation environment Cadence.
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Miri, Lavasani Seyed Hossein. "Design and phase-noise modeling of temperature-compensated high frequency MEMS-CMOS reference oscillators." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/41096.
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Frequency reference oscillator is a critical component of modern radio transceivers. Currently, most reference oscillators are based on low-frequency quartz crystals that are inherently bulky and incompatible with standard micro-fabrication processes. Moreover, their frequency limitation (<200MHz) requires large up-conversion ratio in multigigahertz frequency synthesizers, which in turn, degrades the phase-noise. Recent advances in MEMS technology have made realization of high-frequency on-chip low phase-noise MEMS oscillators possible.
Although significant research has been directed toward replacing quartz crystal oscillators with integrated micromechanical oscillators, their phase-noise performance is not well modeled. In addition, little attention has been paid to developing electronic frequency tuning techniques to compensate for temperature/process variation and improve the absolute frequency accuracy.
The objective of this dissertation was to realize high-frequency temperature-compensated high-frequency (>100MHz) micromechanical oscillators and study their phase-noise performance. To this end, low-power low-noise CMOS transimpedance amplifiers (TIA) that employ novel gain and bandwidth enhancement techniques are interfaced with high frequency (>100MHz) micromechanical resonators. The oscillation frequency is varied by a tuning network that uses frequency tuning enhancement techniques to increase the tuning range with minimal effect on the phase-noise performance. Taking advantage of extended frequency tuning range, and on-chip temperature-compensation circuitry is embedded with the sustaining circuitry to electronically temperature-compensate the oscillator. Finally, detailed study of the phase-noise in micromechanical oscillators is performed and analytical phase-noise models are derived.
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Nissinen, I. (Ilkka). "CMOS time-to-digital converter structures for the integrated receiver of a pulsed time-of-flight laser rangefinder." Doctoral thesis, Oulun yliopisto, 2011. http://urn.fi/urn:isbn:9789514295478.
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Abstract The aim of this thesis was to develop time-to-digital converters (TDC) for the integrated receiver of a pulsed time-of-flight (TOF) laser rangefinder aiming at cm-level accuracy over an input range of 10 m – 15 m. A simple structure, a high integration level and low power consumption are the desired features for such a TDC. From the pulsed TOF laser rangefinder point of view an integrated receiver consisting of both the TDC and the receiver channel on the same die offers the possibility of manufacturing these laser rangefinders with a high integration level and at a low price to fulfil the needs of mass industrial markets. The heart of the TDC is a CMOS ring oscillator, the clock frequency of which is used to calculate the full clock cycles between timing signals, the positions of the timing signals inside the clock period being determined by storing the state of the phase of the ring oscillator for each timing signal. This will improve the resolution of the TDC. Also, additional delay lines are used to generate multiple timing signals, each having a time difference of a fraction of that of the ring oscillator. This will further improve the resolution of the whole TDC. To achieve stable results regardless of temperature and supply voltage variations, the TDC is locked to an on-chip reference voltage, or the resolution of the TDC is calibrated before the actual time interval measurement. The systematic walk error in the receiver channel caused by amplitude variation in the received pulse is compensated for by the TDC measuring the slew rate of the received pulse. This time domain compensation method is not affected by the low supply voltage range of modern CMOS technologies. Three TDC prototypes were tested. A single-shot precision standard deviation of 16 ps (2.4 mm) and a power consumption of 5.3 mW/channel were achieved at best over an input range of 100 ns (15 m). The temperature drifts of an on-chip voltage reference-locked TDC and a TDC based on the calibration method were 90 ppm/°C and 0.27 ps/°C, respectively. The results also showed that a pulsed TOF laser rangefinder with cm-level accuracy over a 0 – 15 m input range can be realized using the integrated receiver with the time domain walk error compensation described hereTiivistelmä Väitöskirjatyön tavoitteena oli kehittää aika-digitaalimuunninrakenteita valopulssin kulkuajan mittaukseen perustuvan lasertutkan integroituun vastaanottimeen. Tavoitteena oli saavuttaa senttimetriluokan tarkkuus 10 m – 15 m mittausalueella koko lasertutkan osalta. Aika-digitaalimuuntimelta vaaditaan yksinkertaista rakennetta, korkeaa integroimisastetta ja matalaa tehonkulutusta. Integroitu vastaanotin sisältää sekä aika-digitaalimuuntimen että vastaanotinkanavan ja tarjoaa mahdollisuuden korkeasti integroidun lasertutkan valmistukseen halvalla teollisuuden massamarkkinoiden tarpeisiin. Aika-digitaalimuuntimen ytimenä toimii monivaiheinen CMOS-rengasoskillaattori. Aika-digitaalimuunnos perustuu rengasoskillaattorin täysien kellojaksojen laskentaan laskurilla ajoitussignaalien välillä. Lisäksi rengasoskillaatorin jokaisesta vaiheesta otetaan näyte ajoitussignaaleilla niiden paikkojen määrittämiseksi kellojakson sisällä, jolloin aika-digitaalimuuntimen erottelutarkkuutta saadaan parannettua. Erottelutarkkuutta parannetaan lisää viivästämällä ajoitussignaaleja viive-elementeillä ja muodostamalla näin useita erillisiä ajoitussignaaleja, joiden väliset viive-erot ovat murto-osa rengasoskillaattorin viive-elementin viiveestä. Aika-digitaalimuunnin stabiloidaan käyttöjännite- ja lämpötilavaihteluja vastaan lukitsemalla se integroidun piirin sisäiseen jännitereferenssiin, tai sen erottelutarkkuus määritetään ennen varsinaista aikavälinmittausta erillisellä kalibrointimittauksella. Vastaanotetun valopulssin amplitudivaihtelun aiheuttama systemaattinen ajoitusvirhe integroidussa vastaanotinkanavassa kompensoidaan mittaamalla vastaanotetun valopulssin nousunopeus aika-digitaalimuuntimella. Tällainen aikatasoon perustuva kompensointimetodi on myös suorituskykyinen nykyisissä matalakäyttöjännitteisissä CMOS-teknologioissa. Työssä valmistettiin ja testattiin kolme aika-digitaalimuunninprototyyppiä. Muuntimien kertamittaustarkkuuden keskihajonta oli parhaimmillaan 16 ps (2,4 mm) ja tehonkulutus alle 5,3 mW/kanava mittausetäisyyden olessa alle 100 ns (15 m). Sisäiseen jännitereferenssiin lukitun aika-digitaalimuuntimen lämpötilariippuvuudeksi mitattiin 90 ppm/°C ja kalibrointimenetelmällä saavutettiin 0,27 ps/°C lämpötilariipuvuus. Työssä saavutetut tulokset osoittavat lisäksi, että valopulssin kulkuajan mittaukseen perustuvalla lasertutkalla on saavutettavissa senttimetriluokan tarkkuus 0 – 15 m mittausalueella käyttämällä tässä työssä esitettyä integroitua vastaanotinta ja aikatason ajoitusvirhekompensointia
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Toledo, Pedro Filipe Leite Correia de. "Modelamento e análise do efeito de coeficiente nulo de temperatura (ZTC) do Mosfet para aplicações análogicas de baixa sensibilidade têrmica." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/140814.
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A contínua miniaturização das tecnologias CMOS oferece maior capacidade de integração e, consequentemente, as variações de temperatura dentro de uma pastilha de silício têm se apresentado cada vez mais agressivas. Ademais, dependendo da aplicação, a temperatura ambiente a qual o CHIP está inserido pode variar. Dessa maneira, procedimentos para diminuir o impacto dessas variações no desempenho do circuito são imprescindíveis. Tais métodos devem ser incluídos em ambos fluxos de projeto CMOS, analógico e digital, de maneira que o desempenho do sistema se mantenha estável quando a temperatura oscilar. A ideia principal desta dissertação é propor uma metodologia de projeto CMOS analógico que possibilite circuitos com baixa dependência térmica. Como base fundamental desta metodologia, o efeito de coeficiente térmico nulo no ponto de polarização da corrente de dreno (ZTC) e da transcondutância (GZTC) do MOSFET são analisados e modelados. Tal modelamento é responsável por entregar ao projetista analógico um conjunto de equações que esclarecem como a temperatura influencia o comportamento do transistor e, portanto, o comportamento do circuito. Essas condições especiais de polarização são analisadas usando um modelo de MOSFET que é contínuo da inversão fraca para forte. Além disso, é mostrado que as duas condições ocorrem em inversão moderada para forte em qualquer processo CMOS. Algumas aplicações são projetadas usando a metodologia proposta: duas referências de corrente baseadas em ZTC, duas referências de tensão baseadas em ZTC, e quatro circuitos gm-C polarizados em GZTC. A primeira referência de corrente é uma Corrente de Referência CMOS Auto-Polarizada (ZSBCR), que gera uma referência de 5uA. Projetada em CMOS 180 nm, a referência opera com uma tensão de alimentação de 1.4 à 1.8 V, ocupando uma área em torno de 0:010mm2. Segundo as simulações, o circuito apresenta um coeficiente de temperatura efetivo (TCeff ) de 15 ppm/oC para -45 à +85 oC e uma sensibilidade à variação de processo de = = 4:5% incluindo efeitos de variabilidade dos tipos processo e descasamento local. A sensibilidade de linha encontrada nas simulações é de 1%=V . A segunda referência de corrente proposta é uma Corrente de Referência Sem Resistor Auto-Polarizada com Capacitor Chaveado (ZSCCR). O circuito é projetado também em 180 nm, resultando em uma corrente de referência de 5.88 A, para uma tensão de alimentação de 1.8 V, e ocupando uma área de 0:010mm2. Resultados de simulações mostram um TCeff de 60 ppm/oC para um intervalo de temperatura de -45 à +85 oC e um consumo de potência de 63 W. A primeira referência de tensão proposta é uma Referência de Tensão resistente à pertubações eletromagnéticas contendo apenas MOSFETs (EMIVR), a qual gera um valor de referência de 395 mV. O circuito é projetado no processo CMOS 130 nm, ocupando em torno de 0.0075 mm2 de área de silício, e consumindo apenas 10.3 W. Simulações pós-leiaute apresentam um TCeff de 146 ppm/oC, para um intervalo de temperatura de 55 à +125oC. Uma fonte EMI de 4 dBm (1 Vpp de amplitude) aplicada na alimentação do circuito, de acordo com o padrão Direct Power Injection (DPI), resulta em um máximo de desvio DC e ondulação Pico-à-Pico de -1.7 % e 35.8m Vpp, respectivamente. A segunda referência de tensão é uma Tensão de Referência baseada em diodo Schottky com 0.5V de alimentação (SBVR). Ela gera três saídas, cada uma utilizando MOSFETs com diferentes tensões de limiar (standard-VT , low-VT , e zero-VT ). Todos disponíveis no processo adotado CMOS 130 nm. Este projeto resulta em três diferentes voltages de referências: 312, 237, e 51 mV, apresentando um TCeff de 214, 372, e 953 ppm/oC no intervalo de temperatura de -55 à 125oC, respectivamente. O circuito ocupa em torno de 0.014 mm2, consumindo um total de 5.9 W. Por último, circuitos gm-C são projetados usando o conceito GZTC: um emulador de resistor, um inversor de impedância, um filtro de primeira ordem e um filtro de segunda ordem. Os circuitos também são simulados no processo CMOS 130 nm, resultando em uma melhora na estabilidade térmica dos seus principais parâmetros, indo de 27 à 53 ppm/°C.Continuing scaling of Complementary Metal-Oxide-Semiconductor (CMOS) technologies brings more integration and consequently temperature variation has become more aggressive into a single die. Besides, depending on the application, room ambient temperature may also vary. Therefore, procedures to decrease thermal dependencies of eletronic circuit performances become an important issue to include in both digital and analog Integrated Circuits (IC) design flow. The main purpose of this thesis is to present a design methodology for a typical CMOS Analog design flow to make circuits as insensitivity as possible to temperature variation. MOSFET Zero Temperature Coefficient (ZTC) and Transconductance Zero Temperature Coefficient (GZTC) bias points are modeled to support it. These are used as reference to deliver a set of equations that explains to analog designers how temperature will change transistor operation and hence the analog circuit behavior. The special bias conditions are analyzed using a MOSFET model that is continuous from weak to strong inversion, and both are proven to occur always from moderate to strong inversion operation in any CMOS fabrication process. Some circuits are designed using proposed methodology: two new ZTC-based current references, two new ZTC-based voltage references and four classical Gm-C circuits biased at GZTC bias point (or defined here as GZTC-C filters). The first current reference is a Self-biased CMOS Current Reference (ZSBCR), which generates a current reference of 5 A. It is designed in an 180 nm process, operating with a supply voltage from 1.4V to 1.8 V and occupying around 0:010mm2 of silicon area. From circuit simulations the reference shows an effective temperature coefficient (TCeff ) of 15 ppm/oC from 45 to +85oC, and a fabrication process sensitivity of = = 4:5%, including average process and local mismatch. Simulated power supply sensitivity is estimated around 1%/V. The second proposed current reference is a Resistorless Self-Biased ZTC Switched Capacitor Current Reference (ZSCCR). It is also designed in an 180 nm process, resulting a reference current of 5.88 A under a supply voltage of 1.8 V, and occupying a silicon area around 0:010mm2. Results from circuit simulation show an TCeff of 60 ppm/oC from -45 to +85 oC and a power consumption of 63 W. The first proposed voltage reference is an EMI Resisting MOSFET-Only Voltage Reference (EMIVR), which generates a voltage reference of 395 mV. The circuit is designed in a 130 nm process, occupying around 0.0075 mm2 of silicon area while consuming just 10.3 W. Post-layout simulations present a TCeff of 146 ppm/oC, for a temperature range from 55 to +125oC. An EMI source of 4 dBm (1 Vpp amplitude) injected into the power supply of circuit, according to Direct Power Injection (DPI) specification results in a maximum DC Shift and Peak-to-Peak ripple of -1.7 % and 35.8m Vpp, respectively. The second proposed voltage reference is a 0.5V Schottky-based Voltage Reference (SBVR). It provides three voltage reference outputs, each one utilizing different threshold voltage MOSFETs (standard-VT , low-VT , and zero-VT ), all available in adopted 130 nm CMOS process. This design results in three different and very low reference voltages: 312, 237, and 51 mV, presenting a TCeff of 214, 372, and 953 ppm/oC in a temperature range from -55 to 125oC, respectively. It occupies around 0.014 mm2 of silicon area for a total power consumption of 5.9 W. Lastly, a few example Gm-C circuits are designed using GZTC technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits are simulated in a 130 nm CMOS commercial process, resulting improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/°C.
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Piccin, Yohan. "Durcissement par conception d'ASIC analogiques." Thesis, Bordeaux, 2014. http://www.theses.fr/2014BORD0145/document.
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Les travaux de cette thèse sont axés sur le durcissement à la dose cumulée des circuits analogiques associés aux systèmes électroniques embarqués sur des véhicules spatiaux, satellites ou sondes. Ces types de circuits sont réputés pour être relativement sensibles à la dose cumulée, parfois dès quelques krad, souvent en raison de l’intégration d’éléments bipolaires. Les nouvelles technologies CMOS montrent par leur intégration de plus en plus poussée, un durcissement naturel à cette dose. L’approche de durcissement proposée ici, repose sur un durcissement par la conception d’une technologie commerciale « full CMOS » du fondeur ST Microelectronics, appelée HCMOS9A. Cette approche permet d’assurer la portabilité des méthodes de durcissement proposées d’une technologie à une autre et de rendre ainsi accessible les nouvelles technologies aux systèmes spatiaux. De plus, cette approche de durcissement permet de faire face aux coûts croissants de développement et d’accès aux technologies durcies. Une première technique de durcissement à la dose cumulée est appliquée à une tension de référence « full CMOS ». Elle ne fait intervenir ni jonction p-n parasites ni précautions delay out particulières mais la soustraction de deux tensions de seuil qui annulent leurs effets à la dose cumulée entre elles. Si les technologies commerciales avancées sont de plus en plus utilisées pour des applications spécialement durcies, ces dernières exhibent en contrepartie de plus grands offsets que les technologies bipolaires. Cela peut affecter les performances des systèmes. La seconde technique étudiée : l’auto zéro, est une solution efficace pour réduire les dérives complexes dues entre autres à la température, de l’offset d’entrée des amplificateurs opérationnels. Le but ici est de prouver que cette technique peut tout aussi bien contrebalancer les dérives de l’offset dues à la dose cumuléeThe purpose of this thesis work is to investigate circuit design techniques to improve the robustness to Total Ionizing Dose (TID) of analog circuits within electronic systems embedded in space probes, satellites and vehicles. Such circuits often contain bipolartransistor components which are quite sensitive to cumulated radiation dose. However highly integrated CMOS technology has been shown to exhibit better natural TDI hardening.The approach proposed here is a hardening by design using a full CMOS semiconductor technology commercially available from ST Microelectronics calledHCMOS9A. The proposed generic hardening design methods will be seen to be compatibleand applicable to other existing or future process technologies. Furthermore this approach addresses the issue of ever-increasing development cost and access to hardened technologies.The first TID hardening technique proposed is applied to a full-CMOS voltage reference. This technique does not involve p-n junctions nor any particular layout precaution but instead is based on the subtraction of two different threshold voltages which allows the cancellation of TDI effects. While the use of advanced commercial CMOS technologies for specific radiation hardened applications is becoming more common, these technologies suffer from larger inputoffs et voltage drift than their bipolar transistor counterparts, which can impact system performance. The second technique studied is that of auto-zeroing, which is an efficient method to reduce the complex offset voltage drift mechanisms of operational amplifiers due to temperature. The purpose here is to prove that this technique can also cancel input offset voltage drift due to TID.Index term : hardening, cumulated dose, CMOS technology, voltage reference,operational amplifier
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Chandernagor, Lucie. "Etude, conception et réalisation d’un récepteur d’activation RF ultra basse consommation pour l’internet des objets." Thesis, Limoges, 2016. http://www.theses.fr/2016LIMO0126/document.
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Grâce au confort d’utilisation qu’elles procurent, les technologies sans fil se retrouvent aujourd’hui dans un vaste panel d’applications. Ainsi le nombre d’éléments de transmission/réception radio se multiplie. Aujourd’hui pour réduire les consommations des éléments radio, il faut les rendre davantage efficaces notamment pour la partie réception. En effet, pour les communications asynchrones, les récepteurs consomment inutilement de l’énergie à attendre qu’une transmission soit faite. Dans l’objectif de réduire ce gaspillage d’énergie, des nouveaux standards ont vu le jour tel que le Zigbee et le Bluetooth Low Energy. Les performances en consommation procurées par ces deux standards résident sur leur fonction périodique à très faible rapport cyclique. Une nouvelle solution émergente pour réduire drastiquement la consommation des récepteurs en les rendant plus efficaces est l’utilisation de récepteur d’activation. Les récepteurs d’activation ou récepteur de réveil sont des récepteurs simples ce qui leur permet d’atteindre une ultra basse consommation uniquement en charge de guetter l’arrivée d’une trame et de réveiller le récepteur principal, placé en veille au préalable, pour traitement de cette dernière. Le récepteur d’activation proposé ici a été réalisé dans la technologie CMOS 160 nm de NXP. Il offre une sensibilité de -54 dBm, pour une consommation moyenne de 35 μA, prodiguant une portée de 70m à 433,92 MHz pour une puissance de 10 dBm émis. Ce récepteur ASK se distingue des autres récepteurs d’activation par le système de calibration breveté avec ajustement automatique la tension de référence requise pour la démodulation. Ce système rend le circuit robuste au problème d’offset DC et ne consomme aucun courant lorsque le circuit est en écoute. Le récepteur d’activation reconnaît un code de Manchester de 24 bits à 25 kbps, programmable grâce à une interface SPIWireless technologies are now widespread due to the easiness of use they provide. Consequently, the number of radio devices increases. Despite of the efforts to reduce radio circuits power consumption as they are more and more numerous, now they must achieve ultra-low power consumption. Today, radio devices are made more efficient to reduce their power consumption especially for the receiving part. Indeed, for asynchronous communication, a lot of energy is wasted by the receiver waiting for a transmission. In order to avoid this waste, new standards have been created such as Zigbee and Bluetooth Low Energy. Due to periodic operation with ultra-low duty cycle, they provide ultra-low power consumption. Another solution to drastically reduce the power consumption has emerged, wake-up receiver. Wake-up receivers are based in simple architecture to provide ultra-low power consumption, they are only in charge to wait for a frame and when it occurs, wake-up the main receiver put in standby mode before that. The proposed wake-up receiver has been designed in NXP CMOS technology 160 μm. It provides a-54 dBm sensitivity, consuming 35 μA which allows a 70m range considering a 10 dBm emitter at 433,92 MHz. This wake-up receiver operates with ASK modulation, compared to others it provides a smart patented calibration system to get the necessary reference voltage for demodulation. This mechanism provide DC offset robustness and does not drain any current while the wake-up receiver is operating. To wake up the main receiver a 24 bits programmable Manchester code is required. This code at 25 kbps is programmable by the use of an SPI interface
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Cardoso, Adilson Silva. "Design and characterization of BiCMOS mixed-signal circuits and devices for extreme environment applications." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/53099.
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State-of-the-art SiGe BiCMOS technologies leverage the maturity of deep-submicron silicon CMOS processing with bandgap-engineered SiGe HBTs in a single platform that is suitable for a wide variety of high performance and highly-integrated applications (e.g., system-on-chip (SOC), system-in-package (SiP)). Due to their bandgap-engineered base, SiGe HBTs are also naturally suited for cryogenic electronics and have the potential to replace the costly de facto technologies of choice (e.g., Gallium-Arsenide (GaAs) and Indium-Phosphide (InP)) in many cryogenic applications such as radio astronomy. This work investigates the response of mixed-signal circuits (both RF and analog circuits) when operating in extreme environments, in particular, at cryogenic temperatures and in radiation-rich environments. The ultimate goal of this work is to attempt to fill the existing gap in knowledge on the cryogenic and radiation response (both single event transients (SETs) and total ionization dose (TID)) of specific RF and analog circuit blocks (i.e., RF switches and voltage references). The design approach for different RF switch topologies and voltage references circuits are presented. Standalone Field Effect Transistors (FET) and SiGe HBTs test structures were also characterized and the results are provided to aid in the analysis and understanding of the underlying mechanisms that impact the circuits' response. Radiation mitigation strategies to counterbalance the damaging effects are investigated. A comprehensive study on the impact of cryogenic temperatures on the RF linearity of SiGe HBTs fabricated in a new 4th-generation, 90 nm SiGe BiCMOS technology is also presented.
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Yang, Julian, and 楊宙穎. "CMOS Temperature Sensor and Bandgap Voltage Reference." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/64563h.
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碩士國立交通大學
電子物理系所
92
A temperature sensing system with digital output consists of a front part and a rear part. The front part includes temperature sensor and bandgap voltage reference. The rear part is an analog to digital converter (ADC). In CMOS technology, the BJT device is used as the basic temperature sensor. The base-emitter voltage (VEB) can be approximated as a linear function of temperature. By using it, temperature sensor and bandgap voltage reference can be accomplished. The simulation of the front part using a standard TSMC 0.25um 1P5M CMOS process is presented in the thesis. The designed PTAT (Proportional To Absolute Temperature) circuit has an output voltage in proportion to absolute temperature with 3.6mV / ℃. The reference voltage (Vref) is 1.21V with an effective temperature coefficient of 8.3 ppm/℃ from -25℃~125℃. Further more, A new type of bandgap voltage reference, in the form of , is proposed. We expand VEB(T) into Taylor series. After second-order compensation with one scaling factor a1=1 and a2 =-0.79, we will get a third-order temperature dependency of bandgap voltage reference. With current mode topology, the circuits design achieves a second-order compensation of VEB. It is simulated with the models of standard TSMC 0.18um 1P6M process. From simulation, the output voltage is 255mV with an effective temperature coefficient of 7.8 ppm/℃ for the temperature range -40℃~125℃. Total current consumption is about 408uA and power consumption is about 0.73mW at 25℃ for this proposed circuit.
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Murugeshappa, Ravi Gourapura. "A low-voltage, low-power CMOS bandgap reference." 2010. http://hdl.handle.net/2152/9162.
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Bandgap reference circuits are used in a host of analog, digital, and mixed-signal systems to establish an accurate voltage reference for the entire IC. The most used CMOS implementation for voltage references is the bandgap circuit due to its high predictability, and low dependence of the supply voltage and temperature of operation. This work studies a CMOS implementation of a resistor-less bandgap reference, which consumes low power. The most relevant and traditional approaches usually employed to implement bandgap voltage references are investigated. The impact of process, power-supply, load and temperature variations has been analyzed and simulated. The functionality of critical components of the circuit has been verified through chip implementation.text
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吳榮田. "Standard CMOS Low Operating Voltage Linear Type Bandgap Reference Voltage Generator." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/35770322350884476361.
Full textAbstract:
碩士國立臺灣大學
電機工程學研究所
90
For many modern analog circuits, it is very important to generate a power supply voltage and temperature independent reference voltage to improve the performance of circuits such as accuracy, reliability, yield rate and so on. In the past the linear type CMOS bandgap reference voltage generator was chosen as a reliable reference voltage source for many years because of its working very well. But the traditional linear type CMOS bandgap reference voltage generator cannot work properly when the power supply voltage is lower than 2V. Due to the progress of CMOS process and the application of ICs, the power supply voltage of many ICs has to be reduced less than 2V in the future. A novel architecture of current summation type linear CMOS bandgap reference voltage generator is proposed here to afford a reliable bandgap reference voltage generating circuit that can operate at 1.3V power supply perfectly.
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Lee, Chia-Yu, and 李佳祐. "A Low-Voltage Low-Temperature-Coefficient CMOS Bandgap Voltage Reference Generator." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/60462464118919911604.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
94
Voltage references play an important role in modern integrated circuits systems. They are widely apdopted in many integrated circuits, such as A/D or D/A converters, power-management system, operational amplifiers, and linear regulators. They are used for defining input/output voltage range, baising current source of differential pairs, and providing a comparison reference for comparators. A precision voltage reference must be, inherently, well-defined and insensitive to temperature, power supply and load variations. The objective of this thesis is to design a bandgap voltage reference with input voltage 1.8V to 3.3V and output voltage around 1.2V. The bandgap voltage reference is intended for using in low dropout linear regulators (LDO). In order to reduce the supply voltage, the voltage reference is using low voltage operational amplifers in place of using conservative cascade current mirror. In addition, this thesis designs a 1-V bandgap voltage reference with temperature compensation to suit the current of low supply voltage. During design and analysis stages, the HSPICE is used for the simulation, modification and verification of the circuit.
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黃全興. "CMOS circuit design for low reference voltage using bandgap." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/49468291675147213413.
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碩士國立中興大學
電機工程學系
91
Reference voltage generators are widely used in many applications from analog circuit to mixed-signal circuits such as ADC, DAC, DRAM and flash memories. These structures are required to provide a stable reference voltage with a low sensitivity to temperature and supply voltage. One of the most popular architectures is the band-gap reference. Due to the need of battery-operated systems for portability, low output reference voltage, low supply voltages and low power consumption will be the trends in the future VLSI products. Two new band-gap reference circuits operated at low supply voltages using 0.18m CMOS technology are presented in this thesis. These two circuits are designed by vertically parasitical BJTs in CMOS technology. The chip area of the new BGR circuit is small. The deviation of Vref is less than 12mV for the temperature ranging from —45 oC to 90 oC.
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GAO, QI-ZHANG, and 高啟章. "Curvature-compensated CMOS bandgap voltage reference-systematic analysis and design." Thesis, 1989. http://ndltd.ncl.edu.tw/handle/45027103366796013327.
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Caylor, Sam D. "A Standard CMOS Compatible Bandgap Voltage Reference with Post-Process Digitally Tunable Temperature Coefficient." 2007. http://trace.tennessee.edu/utk_gradthes/344.
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An essential element of most robust analog/mixed-signal systems is a stable and precise bandgap voltage reference (BGR). CMOS compatible BGR circuits are generally limited by variability in output drift over temperature due to process variations. In this work a CMOS BGR is developed that provides simple, digitally-controlled post-process (i.e., post fabrication) trimming. The trimming is achieved through MOSFET switches used to adjust a current gain factor for the thermal voltage referenced current within the BGR circuit. This current is proportional to absolute temperature (PTAT). The PTAT current is injected into a series connected resistor and diode to ultimately provide an output voltage. The output voltage's temperature coefficient is correlated to the current gain factor applied to the internally generated PTAT current. Thus, the BGR circuit's temperature coefficient (and therefore drift) is adjusted or tuned using a digital input word to control switch settings and therefore the PTAT current. By providing post-process trimming, chip-to-chip and wafer-to-wafter variations can be minimized through simple digitally controlled tuning. This trimming capability also extends the BGR to broad temperature range applications. A complete CMOS-compatible post-process trimmable BGR implementation is described and measurement results are provided. Design considerations to enhance the circuit's tolerance to radiation induced single-event transients are also addressed.
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Caylor, Sam D. "A standard CMOS compatibles bandgap voltage reference with post-process digitally tunable temperature coefficient." 2008. http://etd.utk.edu/2008/CaylorSam.pdf.
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QIN, XU-YUAN, and 泰旭沅. "The design of CMOS bandgap voltage reference and capacitor-ratio-independent algorithmic analog-to-digital converter." Thesis, 1989. http://ndltd.ncl.edu.tw/handle/08997420346634447895.
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Cheng, Chin-Hung, and 鄭欽鴻. "Bandgap Reference Voltage Generator." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/10794634026978236467.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
92
Precision voltage reference plays an important role in modern integrated circuits systems. It can produce a stable reference voltage insensitive to the variations of supply voltage and temperature. Voltage references are widely adopted in many integrated circuits, such as A/D or D/A converters, operational amplifiers, and linear regulators. They are used for defining input/output voltage range, biasing current source of differential pairs, and providing a comparison reference for comparators, etc. The objective of this thesis is to design a bandgap reference voltage generator with input voltage 3V to 6V and output voltage around 1.25V. This reference voltage is intended for using in low dropout linear regulators (LDO). A pre-regulator circuit feeds the bandgap circuit with a regulated 2V to lower the supply voltage sensitivity. A new bandgap circuit topology is also presented. The final bandgap reference with supply voltage sensitivity less than 0.3 mV/V, and temperature coefficient around 7 ppm/℃, and power consumption lower than 100μW is achieved.
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Hsu, Kang-Yu, and 徐康禹. "Current Mode Bandgap Voltage Reference." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/xxdacb.
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碩士逢甲大學
電機工程所
90
The objective of this thesis is to design a bandgap voltage reference that can be operated in the range from 3.3V to 5V. The main work is to design a circuit that utilizes a PTAT (proportional to absolute temperature) to compensate the negative temperature coefficient resulting from BJT. The ordinary bandgap voltage reference requires an operational amplifier to stabilize the output voltage. As a result, the circuit will consequently consume considerable area and power dissipation. To circumvent these problems, we propose a current mode bandgap voltage reference, which will not only decrease the temperature effect, but also significantly reduce the power consumption. The proposed current mode bandgap voltage reference can regulate a stabilized output voltage and maintain an excellent resistance to other external variables. Moreover, the output voltage is adjustable by external resistors. Many capability of this design has shown to be superior to those using operational amplifier as feedback. Our circuit is fabricated bt UMC 0.5μm double-poly triple-metal N-well CMOS process.
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Chia, Jr-Yung, and 賈志勇. "Micro Power Low Voltage Bandgap Reference." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/09338594754044322158.
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碩士中原大學
電子工程研究所
94
Abstract Three micro power low voltage bandgap references are presented. These complete designs were simulated and laid out in a standard digital 0.18-µm 1P6M 1.8V CMOS process and operated at 1.5V power supply. A micro power folded cascode operational transconductance amplifier is also presented for these micro power bandgap references. A micro power bandgap voltage reference uses a micro power amplifier to keep a balance condition, and provides a 1.2086V 2.3mV bandgap voltage, a temperature coefficient of 48.7 ppm/℃ over a temperature range from 0 to 60℃ from a measured statistics. The operated chips of this reference consume a mean power dissipation of 43.1µW. Another micro power low bandgap voltage reference uses independent circuits of biasing and start-up in internal amplifier to obtain more reliability, and provides a 603.9mV 1.8mV bandgap voltage, a temperature coefficient of 72.8 ppm/℃ over a temperature range from 0 to 60℃ from a measured statistics. The measured chips can be operated a minimum supply voltage of sub-1V and consume a mean power dissipation of 49.1µW. Moreover, a micro power bandgap current reference utilized a compensated technology of two branch current was presented in this thesis. In a block circuit with a feedback noise issue, the improved bandgap current reference is able to restrain noise feedback and keep current supply stably. In this design, the reference output current is 300µA within a temperature coefficient of 16 ppm/℃.
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Liu, Chzung-Tai, and 劉宗泰. "The study of low voltage bandgap voltage reference circuit." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/37524136168903290293.
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CHANG, CHIH-TIEN, and 張志田. "CMOS Micropower Bandgap Reference, Time Reference and Temperature Sensor." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/17718187721340808673.
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碩士國立臺灣大學
電機工程學系研究所
86
There are three topics in this paper : CMOS micropower bandgap reference, time reference and temperature sensor. The CMOS micropower bandgap referenc e mainly utilizes the traditional concepts of bandgap reference, replaces the original PTAT ( Proportional To Absolute Temperature ) part formed by BJT pair with CMOS devices operating in the weak inversion region. Also uses the verti cal pnp BJT formed by CMOS process. Hoping that under micropower, the circuit could output a reference voltage which is stable suffering from the limiting t emperature variation. In this topics, we design a bandgap reference which oper ates under 1.5V, single battery, consumes power less than 0.5uW and suffers te mperature varying from -40℃to 100℃. However, the test results is not so good that the 3rd chip is under designing. Different to the 1st topic, the CMOS time reference utilizes the CMOS lateral pnp BJT to design currents and volta ges relating to temperature variation and uses these to compensate the current reference. By this current reference, we could design a one-shot circuit to f orm a pulse not varying with different temperature, a time reference. In this topics, we design a current reference and a time reference which operate under 3V power supply and suffer temperature variation from -40℃to 100℃. Although the current reference''s output is not so good, we have a 1.5uS time reference which and varies in 10% error. This is because the voltage reference and curr ent reference vary together. Finally, with the experiences of designing cir cuits relating to temperature, we utilize a current reference and a current up with temperature up and 1st-order delta-sigma ADC to design a temperature sen sor which operates under 3V power supply and suffers temperature variation fro m -40℃to 100℃and a bandgap reference. After testing, the current ratio of se nsing part is sensitive to temperature varying but the function of ADC is not so good that the temperature sensor has errors up to 20℃.The bandgap referenc e has a 77ppm/℃temperature coefficient.
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Chang, Ting-Wei, and 張庭瑋. "CMOS current reference and voltage reference design." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/53278481139150247466.
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碩士北台科學技術學院
機電整合研究所
94
This paper presents some new circuits including CMOS circuit reference and voltage reference. The architecture of the current references is produced not only by adding a positive supply voltage coefficient current reference and a negative supply voltage coefficient current reference to cancel out the supply voltage variations but also by adding a positive temperature coefficient current reference and a negative temperature coefficient current reference to cancel out the temperature variation. About the negative supply voltage coefficient current reference, we can product it by subtracting two current references with different positive supply voltage coefficient. This paper also presents a sub-1v voltage reference, which is different from the traditional bandgap reference. The main architecture of the voltage reference is composed of a positive temperature coefficient voltage reference and a negative temperature coefficient voltage reference. At first, by putting two different bias voltage of the bipolar junction transistors into the differential pair and adjusting the transistor size, we can obtain a voltage reference with a positive temperature coefficient; Secondly, by putting a ground voltage and a bias voltage of the bipolar junction transistors into the differential pair and adjusting the transistor size, we can obtain a voltage reference with a negative temperature coefficient. Finally, by putting the positive coefficient voltage reference and the negative temperature coefficient voltage reference into the differential pair and adjusting the transistor size, we can obtain a voltage reference with less sensitive to temperature variation.
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Luo, Jing-Yu, and 羅景煜. "Low Power Low Voltage Temperature-Compensation Bandgap Reference Circuit." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/63932569067195146542.
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碩士國立聯合大學
電子工程學系碩士班
95
Reference circuits are the basic building blocks in many analog and digital applications such as A/D and D/A converter, flash memory circuits, and many other circuits. The objective of reference generation is to establish a dc voltage or current that is independent of the supply and fabrication process and has a well-defined behavior with temperature. The properties of reference circuit will not the same with the different demand for characteristics. In this thesis, we will be aimed at the requirement that low power, low voltage and provide with temperature-compensation technique to design this reference circuit. Furthermore, the requirement of low power, low voltage and provide with temperature-compensation technique is especially application in the batter-operated mobile products, such as cellular phones, PDAs, camera recorders, and laptops. In this thesis, these three structures of 「A Low Output Voltage CMOS Bandgap Reference」, 「A Low Supply Voltage Temperature-Compensation CMOS Subbandgap Reference with Two Averaging Circuitry」 and 「A Low Supply Voltage CMOS Subbandgap Reference Using MOSFET Temperature-Compensation technique」 are proposed and implemented. The first and second structures are used of the bipolar transistor and the feedback of differential amplifier to achieve the requirement of temperature-compensation. On the basis of concept for the first and second structures, a new structure of bandgap reference is supported in third structure which difference between first and second structures. The third structure is used of the bias circuit to generate a positive temperature coefficient current and used of a negative temperature coefficient active load to achieve the requirement of temperature-compensation. In this structure, the low supply voltage, low power and low sensitivity with temperature is possibly implemented. This circuit will be implemented in standard TSMC CMOS 0.18um process.
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Liao, Jia-Zheng, and 廖家正. "Design of A CMOS Reference Voltage." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/3h6nk8.
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碩士國立虎尾科技大學
電子工程系碩士班
101
In this thesis, a CMOS differential-mode reference voltage circuit has been proposed. By properly using the positive and negative temperature coefficient parameters, a zero temperature-coefficient can be achieved. The proposed circuits are based on the traditional bandgap voltage reference circuit architecture with an additional current mirror and a proportional-to-absolute-temperature current source which is composed of current mirrors. As compared with the existed differential-mode reference voltage circuit, the proposed circuit does not need an operational amplifier, therefore it benefits from simpler circuit architecture, less chip area, and less power consumption. Besides the detailed design principle, the HSPICE and LAKER simulation program with 0.35-um and 0.18-um process parameters have been used to perform the pre-layout and post-layout simulation. According to the post-layout simulation results, as the supply voltages is 3.3V, the differential-mode output voltage reference circuit shows that, as the temperature varies from -20oC to 120oC, the corresponding output voltage changes only 1.3mV(0.225%), the corresponding power dissipation is 2.354mW and the temperature-coefficient is 16.11 ppm/˚C. In addition, if a transistor and a resistor are removed from the proposed differential-mode output voltage reference circuit, a single-ended mode reference voltage with zero temperature coefficient can be obtained. According to the post-layout simulation results, when the supply voltages is 2.8V, and as the temperature varies from -20oC to 120oC, the corresponding output voltage changes only 2.01mV(0.387%), the corresponding power dissipation is 1.412mW and the temperature-coefficient is 27.79 ppm/˚C. All the simulation results are consistent with the theoretic analysis. The proposed circuits can be applied to different analog circuits.
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Chiang, Tzung-Yin, and 江宗殷. "Temperature-compensated CMOS voltage reference circuit." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/07003708814603618036.
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碩士國立清華大學
工程與系統科學系
93
Reference circuits have been studying for many years. Following the vigorous development of portable electronic products, integrated circuits with low voltage and small area have become the core part of the recent research. Parasitic vertical bipolar junction transistors are commonly used in CMOS voltage reference circuits for a better stability. Recently, MOS reference circuits have been used to replace BJT ones in order to reduce the chip area and supply voltage. Whether BJT or MOS is utilized, the problem that resistances parallelizing on either side of BJT or MOS generally occupy quite large ratio of chip area under the consideration of power consumption and loading parasitic capacitances of op-amp still exists. Another problem worthy of our concern is that spurious signals coming from the supply voltage cannot be adequately rejected and may couple into the circuit to degrade output signal in high frequency applications. This thesis aims to improve the above problems and proposes a novel voltage reference circuit. A current mirror is designed for temperature compensation and large resistors are defeasible for reduction chip area. Besides, it has been implemented by a 0.18 μm CMOS process with a chip area of 0.023 mm2. Simulation shows that the variation of temperature coefficient is from 59.5 to 63.8 ppm/℃ under the temperature range from -40 to 100 ℃ and a supply voltage variation from 1.2 to 1.98 V. The power noise rejection ratio is -70 dB at 10 kHz with 1.2V supply voltage. In summary, the thesis adopts a current mirror to achieve low-temperature-drift reference voltage and abandons large resistances on design consideration. With this approach, power noise rejection ration is reduced.
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Hsu, Chao-Hung, and 許肇宏. "A 1.5 ppm/℃ Wide-Temperature-Range CMOS Bandgap Reference Circuit." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/51807608514703549352.
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碩士國立彰化師範大學
電子工程學系
103
In this thesis, the designed circuit is based on the structure of first-order linear temperature compensation bandgap voltage reference circuit, and the circuit generates the current with nonlinear temperature term for curve compensation by using BJT’s current relationship with temperature, IPTAT and ICTAT. Finally, the circuit generates the bandgap reference voltage source which has wide-temperature operation range and low temperature coefficient. The TSMC 0.18 μm 1P6M CMOS models are used in the HSPICE simulation, and Virtuoso is used to implement the circuit layout. The pre-layout and post-layout simulation results are, when supply voltage VDD is 1.5 V and the operation temperature range is from -40 ℃ to 150 ℃. The average value of output reference voltage is 864.84 mV and 864.87 mV, the temperature coefficient is about 1.5 ppm/℃ and 2.3 ppm/℃, the power consumption is about 213.91 μW and 226.07 μW, and the Power Supply Rejection Ratio (PSRR) is about 58 dB and 42 dB at 10 kHz. The measured results of the chip are, when supply voltage VDD is 1.5 V and the operation temperature range is from -40 ℃ to 150 ℃. The temperature coefficient is about 30 ppm/℃, the power consumption is about 220 μW, and the average value of output reference voltage is 875.75 mV
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Gao, Jing-Zhi, and 高靖智. "Active Phased Array Receiver and Low-Supply-Voltage Bandgap Reference." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/y942dm.
Full text
49
Wang, Wei-Shin, and 王惟昕. "Fully-MOSFET Bandgap Voltage Reference Circuit with Self-cascade Architecture." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/vhax89.
Full textAbstract:
碩士國立彰化師範大學
電子工程學系
107
This thesis presents a fully-MOSFET band-gap voltage reference circuit with low temperature coefficient. The circuit consists of a generator of PTAT, a generator of CTAT and a current source. The generator of PTAT utilize the self-cascade MOSFETs to generate the PTAT voltage, and the generator of CTAT is a MOSFET gate to source voltage, this voltage is a CTAT voltage when the MOSFET is operated in sub-threshold region. We use TSMC 0.18 μm CMOS technology to design the circuit in this thesis. The pre-simulation results are when VDD is at 1.8 V and temperature is ranging from -25 °C to 110 °C, the output voltage is 895 mV, the temperature coefficient is 9.7 ppm/°C, the power consumption is 280.9 nW, and the PSRR is -41.7 dB. Under the same condition, the post-simulation results are as follow: the output voltage is 881 mV, the temperature coefficient is 33 ppm/°C, the power consumption is 239.5 nW, and the PSRR is -41 dB.
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Jian, Zih-Hao, and 簡子豪. "The Resistorless Bandgap Voltage Reference Circuit Based on Piecewise Compensation." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/75033211528052212694.
Full textAbstract:
碩士國立彰化師範大學
電子工程學系
104
This thesis presents a band-gap voltage reference circuit with low temperature coefficient. The circuit consists of a resistor-less first-order band-gap voltage reference circuit and a resistor-less second-order circuit. The first-order band-gap voltage reference circuit consists of generator of PTAT, generator of CTAT and start-up circuit. The generator of PTAT is composed of two pairs of current mirrors and two MOS diodes, and two MOS diodes with different channel width and same channel length generate the bias current. While, the circuit of CTAT consists of one MOSFET, working as an active load, four pairs of current mirrors, and three MOSFET operating in sub-threshold region. Use current subtraction technique to generate the bias current of CTAT. The start-up circuit has two MOSFET and a MOS capacitance, and the start-up circuit destroys the degeneration bias point, so the circuit can work properly. The start-up circuit in this study uses the charge and discharge of MOS capacitance to change the bias condition of the start-up circuit, so the circuit can maintain in operation region. The second-order circuit is trans-linear circuit in this thesis, which consists of an OPA, four BJTs and five MOSFETs. The circuit generates nonlinear compensation current, which is square to absolute temperature, and a current mirror adjusts this compensation current. Combine first order and second order, we obtain a band-gap voltage reference with low temperature sensitivity. The circuit in this thesis is designed by TSMC 0.18 μm CMOS technology. The pre-simulation results, when VDD is at 1.8V and temperature is ranging from -40℃ to 125℃, are the temperature coefficient is 30 ppm/℃, the power consumption is 496 µW, and PSRR is -32dB. Under the same condition, the post-simulation results are as follow: temperature coefficient is 16.75 ppm/℃, the power consumption is 560 µW, and PSRR is -36dB. The measurement results are as follow: temperature coefficient is 118.72 ppm/℃, the power consumption is 504 µW, and PSRR is -27dB.