Dissertations / Theses: 'CMOS Voltage Reference'

1

Holman, William Timothy. "A low noise CMOS voltage reference." Diss., Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/14968.

Full text

APA, Harvard, Vancouver, ISO, and other styles

2

Komark, Stina. "Design of an integrated voltage regulator." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1711.

Full text

Abstract:

Many analog systems need a stable power supply voltage that does not vary with temperature and time in order to operate properly. In a battery operated system the battery voltage is not stable, e.g. it decreases with decreasing temperature and with ageing. In that case a voltage regulator must be used, that regulates the battery voltage and generates a stable supply voltage to power other circuitry.

In this thesis a voltage regulator to be used in a battery operated system has been designed which meets the given specification of stability and power capabilities. A voltage reference, which is a commonly used devise in analog circuits, was also designed. The role of a reference voltage in an electrical system is the same as for a tuning fork in a musical ensemble; to set a standard to which other voltages are compared.

A functionality to detect when the lifetime of the battery is about to run out was also developed.

APA, Harvard, Vancouver, ISO, and other styles

3

Kotrč, Václav. "Napěťové reference v bipolárním a CMOS procesu." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2015. http://www.nusl.cz/ntk/nusl-221111.

Full text

Abstract:

This diploma thesis deals with precise design of Brokaw BandGap voltage reference comparing with MOS references. There is STEP BY STEP separation and analysis of proposed devices, using Monte Carlo analysis. There are also presented the methods for achieving a lower deviation of the output voltage for yielding device, which needs no trimming.

APA, Harvard, Vancouver, ISO, and other styles

4

Gupta, Vishal. "An accurate, trimless, high PSRR, low-voltage, CMOS bandgap reference IC." Diss., Available online, Georgia Institute of Technology, 2007, 2007. http://etd.gatech.edu/theses/available/etd-07052007-073154/.

Full text

Abstract:

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.
Ayazi, Farrokh, Committee Member ; Rincon-Mora, Gabriel, Committee Chair ; Bhatti, Pamela, Committee Member ; Leach, W. Marshall, Committee Member ; Morley, Thomas, Committee Member.

APA, Harvard, Vancouver, ISO, and other styles

5

Kevin, Tom. "Sub-1V Curvature Compensated Bandgap Reference." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2585.

Full text

Abstract:

This thesis investigates the possibility of realizing bandgap reference crcuits for processes having sub-1V supply voltage. With the scaling of gate oxide thickness supply voltage is getting reduced. But the threshold voltage of transistors is not getting scaled at the same rate as that of the supply voltage. This makes it difficult to incorporate conventional designs of bandgap reference circuits to processeshaving near to 1V supply voltage. In the first part of the thesis a comprehensive study on existing low voltage bandgap reference circuits is done. Using these ideas a low-power, low-voltage bandgap reference circuit is designed in the second part of the thesis work.

The proposed bandgap reference circuit is capable of generating a reference voltage of 0.730V. The circuit is implemented in 0.18µm standard CMOS technology and operates with 0.9V supply voltage, consuming 5µA current. The circuit achieves 7 ppm/K of temperature coefficient with supply voltage range from 0.9 to 1.5V and temperature range from 0 to 60C.

APA, Harvard, Vancouver, ISO, and other styles

6

Mattia, Neto Oscar Elisio. "NanoWatt resistorless CMOS voltage references for Sub-1 V applications." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/107131.

Full text

Abstract:

Referências de tensão integradas sempre foram um bloco fundamental de qualquer sistema eletrônico e um importante tópico de pesquisa que tem sido estudado extensivamente nos últimos 50 anos. Uma tensão de referência é um circuito que provê uma tensão estável com baixa sensibilidade a variações em temperatura, alimentação, carga, características do processo de fabricação e tensões mecânicas de encapsulamento. Elas são normalmente implementadas através da soma ponderada de dois fenômenos físicos diferentes, com comportamentos em temperatura opostos. Normalmente, a tensão térmica, relacionada à constante de Boltzmann e à carga do elétron, fornece uma dependência positiva com temperatura, enquanto que a tensão base-emissor VBE de um transistor bipolar ou a tensão de limiar de um MOSFET fornece o termo complementar. Um bloco auxiliar é às vezes utilizado para fornecer as correntes de polarização do circuito, e outros blocos adicionais implementam a soma ponderada. A evolução da tecnologia de processos é o principal fator para aplicações em baixa tensão, enquanto que a emergência de dispositivos portáteis operados a bateria, circuitos biomédicos implantáveis e dispostivos de captura de energia do ambiente restringem cada circuito a consumir o mínimo possivel. Portanto, alimentações abaixo de 1 V e consumos na ordem de nanoWatts se tornaram características fundamentais de tais circuitos. Contudo, existem diversos desafios ao projetar referências de tensão de alta exatidão em processos CMOS modernos sob essas condições. As topologias tradicionais não são adequadas pois elas provêm uma referência de tensão acima de 1 V, e requerem resistências da ordem de G para atingir tão baixo consumo de potência, ocupando assim uma grande área de silício. Avanços recentes atingiram tais níveis de consumo de potência, porém com limitada exatidão, custosos procedimentos de calibração e grande área ocupada em silício. Nesta dissertação apresentam-se duas novas topologias de circuitos: uma tensão de junção bipolar com compensação de curvatura que não utiliza resistores e é auto-polarizada; e um circuito de referência bandgap sem resistores que opera abaixo de 1 V (também chamado de sub-bandgap). Ambos circuitos operam com consumo na ordem de nanoWatts e ocupam pequenas áreas de silício. Resultados de simulação para dois processos diferentes, 180 nm e 130 nm, e resultados experimentais de uma rodada de fabricação em 130 nm apresentam melhorias sobre tais limitações, mantendo as características desejadas de não conter resistores, ultra baixo consumo, baixa tensão de alimentação e áreas muito pequenas.
Integrated voltage references have always been a fundamental block of any electronic system, and an important research topic that has been extensively studied in the past 50 years. A voltage reference is a circuit that provides a stable voltage with low sensitivity to variations in temperature, supply, load, process characteristics and packaging stresses. They are usually implemented through the weighted sum of two independent physical phenomena with opposite temperature dependencies. Usually the thermal voltage, related to the Boltzmann’s constant and the electron charge, provides a positive temperature dependence, while the silicon bandgap voltage or a MOSFET’s threshold voltage provide the complementary term. An auxiliary biasing block is sometimes necessary to provide the necessary currents for the circuit to work, and additional blocks implement the weighted sum. The scaling of process technologies is the main driving factor for low voltage operation, while the emergence of portable battery-operated, implantable biomedical and energy harvesting devices mandate that every circuit consume as little power as possible. Therefore, sub-1 V supplies and nanoWatt power have become key characteristics for these kind of circuits, but there are several challenges when designing high accuracy voltage references in modern CMOS technologies under these conditions. The traditional topologies are not suitable because they provide a reference voltage above 1 V, and to achieve such power consumption levels would require G resistances, that occupy a huge silicon area. Recent advances have achieved these levels of power consumption but with limited accuracy, expensive calibration procedures and large silicon area.

APA, Harvard, Vancouver, ISO, and other styles

7

Caicedo, Jhon Alexander Gomez. "CMOS low-power threshold voltage monitors circuits and applications." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2016. http://hdl.handle.net/10183/144080.

Full text

Abstract:

Um monitor de tensão de limiar (VT0) é um circuito que, idealmente, entrega o valor do VT0 como uma tensão na saída, para uma determinada faixa de temperatura, sem a necessidade de polarização externa, configurações paramétricas, ajuste de curvas ou qualquer cálculo subsequente. Estes circuitos podem ser usados em sensores de temperatura, referências de tensão e corrente, dosímetros de radiação e outras aplicações, uma vez que a dependência do VT0 nas condições de operação é um aspecto bem modelado. Além disso, estes circuitos podem ser utilizados para monitoramento de processos de fabricação e para compensação da variabilidade do processo, uma vez que o VT0 é um parâmetro chave para o comportamento do transistor e sua modelagem. Nesta tese, são apresentadas três novas topologias de circuitos, duas são monitores de VT0 NMOS e a terceira é um monitor de VT0 PMOS. As três estruturas são topologias de circuito auto-polarizadas que não utilizam resistências, e apresentam alta rejeição a variações na alimentação, baixa sensibilidade de Linea, e permitem a extração direta da tensão de limiar para grandes intervalos de temperatura e de tensão de alimentação, com pequeno erro. Sua metodologia de projeto é baseada no modelo unificado controlado por corrente (UICM), um modelo MOSFET que é contínuo, desde o nível de inversão fraca a forte e para as regiões de operação de triodo e saturação. Os circuitos ocupam uma pequena área de silício, consomem apenas dezenas de nanowatts, e podem ser implementados em qualquer processo padrão CMOS digital, uma vez que só utilizam transistores MOS (não precisa de nenhum resistor). Os monitores de VT0 são utilizados em diferentes aplicações, a fim de investigar a sua funcionalidade e comportamento como parte de um sistema. As aplicações variam de uma tensão de referência, que apresenta um desempenho comparável ao estado da arte, para uma configuração que permite obter uma menor variabilidade com processo na saída de um circuito auto-polarizado que gera um tensão CTAT. Além disso, explorando a capacidade de funcionar como um gerador de corrente específica (ISQ) que os monitores de VT0 aqui apresentados oferecem, introduz-se um novo circuito auto-polarizado que gera um tensão CTAT, que é menos sensível a variações de processo, e pode ser usado em referências de tensão band-gap.
A threshold voltage (VT0) monitor is a circuit that ideally delivers the estimated VT0 value as a voltage at its output, for a given temperature range, without external biases, parametric setups, curve fitting or any subsequent calculation. It can be used in temperature sensors, voltage and current references, radiation dosimeters and other applications since the MOSFET VT0 dependence on the operation conditions is a very well modeled aspect. Also, it can be used for fabrication process monitoring and process variability compensation, since VT0 is a key parameter for the transistor behavior and modeling. In this thesis, we present three novel circuit topologies, two of them being NMOS VT0 monitors and the last one being a PMOS VT0 monitor. The three structures are resistorless self-biased circuit topologies that present high power supply rejection, low line sensitivity, and allow the direct extraction of the threshold voltage for wide temperature and power supply voltage ranges, with small error. Its design methodology is based on the Unified Current Control Model (UICM), a MOSFET model that is continuous from weak to strong inversion and from triode to saturation regions. The circuits occupy small silicon area, consume just tens of nanoWatts, and can be implemented in any standard digital CMOS process, since they only use MOS transistors (does not need any resistor). The VT0 monitors are used in different applications in order to prove their functionality, and behavior as part of a system. The applications vary from a reference voltage, that presents performance comparable with state-of-the-art works, to a configuration that allows to obtain a lower process variability, in the output of a self-biased circuit that generates a complementary to the absolute temperature (CTAT) voltage. In addition, exploiting the ability to operate as an specific current (ISQ) generator, that the VT0 monitors presented here offer, we introduced a new self-biased circuit that produces a CTAT voltage and is less sensitive to process variations, and can be used in band-gap voltage references.

APA, Harvard, Vancouver, ISO, and other styles

8

Ishibe, Eder Issao. "Projeto de uma fonte de tensão de referência." Universidade de São Paulo, 2014. http://www.teses.usp.br/teses/disponiveis/18/18155/tde-24072014-165540/.

Full text

Abstract:

Neste trabalho é apresentado o projeto de uma fonte de tensão de referência, um circuito capaz de prover uma tensão invariante com a temperatura, a tensão de alimentação e o processo de fabricação. São apresentadas: as equações de funcionamento, os passos para a elaboração da uma topologia final, o dimensionamento dos parâmetros de projeto com o uso de algoritmos metaheurísticos, o desenho do layout e os resultados e análises finais. O projeto emprega a tecnologia CMOS de 0,35 μm com quatro camadas de metal da Austria Micro Systems, em que os VTH0\'s dos transistores NMOS e PMOS, modelo típico, são, respectivamente, 0,5 V e -0,7 V. O circuito de fonte de referência é do tipo bandgap e faz a soma ponderada de correntes proporcionais a temperatura para atingir uma tensão de referência. Obteve-se um circuito típico com 0,5 V de tensão de referência, coeficiente de temperatura de 15 ppm/ºC em intervalo de temperatura de -10 a 90ºC em 1,0 V de tensão de alimentação, regulação de linha de 263 ppm/V em um intervalo de variação de 1,0 V a 2,5 V em 27ºC, 2,7 μA de corrente consumida e área de 0,11 mm². A introdução de um bloco de ajuste de coeficiente de temperatura, com ajuste digital, permite que mais que 90% dos circuitos produzidos tenham um coeficiente de temperatura de até 30 ppm/ºC. As medidas realizadas no trabalho são provenientes de simulações elétricas realizadas com o ELDO e modelos BSIM3v3.
In this work is presented a design of a reference voltage source, circuits capable to provide an invariant voltage regardless of the temperature, power supply and fabrication process. It\'s presented: the operation equations, the steps to elaborate a final topology, the project parameter sizing using a metaheuristic algorithm, the drawing of the layout, and the final results and its analysis. The design employs an AMS-CMOS 0.35 μm technology with four metal levels, whose NMOS and PMOS VTH0\'s for a typical circuit is 0.5 V and -0.7 V. The reference voltage circuit is bandgap and performs a weighted summation of proportional temperature currents to achieve the voltage reference. A typical circuit was obtained with 0.5 V reference voltage, 15 ppm/ºC temperature coefficient in the temperature range of -10 to 90ºC under 1.0 V power supply, 263 ppm/V line regulation in the range of 1.0 V to 2.5 V under 27ºC, 2.7 μA power consumption in a 0.11 mm² area. For a projected circuit its also possible to ensure a temperate coefficient under 30 ppm/ºC, for more than 95% of the produced circuits, employing an adjustment block which ought to be digitally calibrated for each circuit.

APA, Harvard, Vancouver, ISO, and other styles

9

Mácha, Petr. "Návrh převodníku DA s plně diferenčním výstupem v technologii CMOS." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2017. http://www.nusl.cz/ntk/nusl-316964.

Full text

Abstract:

This diploma thesis deals with the design of eight-bit digital to analog coverter with fully differential outputs in technology I3T25 of ON Semiconductor company. The work contains the description of basic structures and characteristics of digital to analog converters. The main focus of the work is to design a converter and auxiliary circuits at the transistor level. The functionality of designed circuits is verified by simulation environment Cadence.

APA, Harvard, Vancouver, ISO, and other styles

10

Miri, Lavasani Seyed Hossein. "Design and phase-noise modeling of temperature-compensated high frequency MEMS-CMOS reference oscillators." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/41096.

Full text

Abstract:

Frequency reference oscillator is a critical component of modern radio transceivers. Currently, most reference oscillators are based on low-frequency quartz crystals that are inherently bulky and incompatible with standard micro-fabrication processes. Moreover, their frequency limitation (<200MHz) requires large up-conversion ratio in multigigahertz frequency synthesizers, which in turn, degrades the phase-noise. Recent advances in MEMS technology have made realization of high-frequency on-chip low phase-noise MEMS oscillators possible. Although significant research has been directed toward replacing quartz crystal oscillators with integrated micromechanical oscillators, their phase-noise performance is not well modeled. In addition, little attention has been paid to developing electronic frequency tuning techniques to compensate for temperature/process variation and improve the absolute frequency accuracy. The objective of this dissertation was to realize high-frequency temperature-compensated high-frequency (>100MHz) micromechanical oscillators and study their phase-noise performance. To this end, low-power low-noise CMOS transimpedance amplifiers (TIA) that employ novel gain and bandwidth enhancement techniques are interfaced with high frequency (>100MHz) micromechanical resonators. The oscillation frequency is varied by a tuning network that uses frequency tuning enhancement techniques to increase the tuning range with minimal effect on the phase-noise performance. Taking advantage of extended frequency tuning range, and on-chip temperature-compensation circuitry is embedded with the sustaining circuitry to electronically temperature-compensate the oscillator. Finally, detailed study of the phase-noise in micromechanical oscillators is performed and analytical phase-noise models are derived.

APA, Harvard, Vancouver, ISO, and other styles

11

Castellanos, Juan José Carrillo. "Projeto de uma fonte de tensão de referência CMOS usando programação geométrica." Universidade de São Paulo, 2010. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-01032011-120430/.

Full text

Abstract:

Nesta dissertação é apresentada a aplicação da programação geométrica no projeto de uma fonte de tensão de referência de baixa tensão de alimentação que pode ser integrada em tecnologias padrões CMOS. Também são apresentados os resultados experimentais de um projeto da fonte de bandgap feito por um método de projeto convencional, cuja experiência motivou e ajudou ao desenvolvimento da formulação do programa geométrico proposta neste trabalho. O programa geométrico desenvolvido nesta dissertação otimiza o desempenho da fonte de bandgap e agiliza seu tempo de projeto. As expressões matemáticas que descrevem o funcionamento e as principais especificações da fonte de bandgap foram geradas e adaptadas ao formato de um programa geométrico. A compensação da temperatura, o PSRR, o consumo de corrente, a área, a tensão de saída e a sua variação por causa da tensão de offset do OTA, e a estabilidade são as principais especificações deste tipo de fonte de tensão de referência e fazem parte do programa geométrico apresentado neste trabalho. Um exemplo do projeto usando o programa geométrico formulado neste trabalho, mostra a possibilidade de projetar a fonte de bandgap em alguns minutos com erros baixos entre os resultados do programa geométrico e de simulação.
This work presents the application of geometric programming in the design of a CMOS low-voltage bandgap voltage reference source. Test results of a bandgap voltage reference designed via a conventional method are showed, this design experience motivated and helped to formulate the geometric program developed in this work. The geometric program developed in this work optimizes the bandgap source performance and speeds up the design time. The mathematical expressions that describe the bandgap source functioning and specifications were developed and adapted in the geometric program format. The temperature compensation, the PSRR, the current consumption, the area, the output voltage and its variations under the operational tranconductance amplifier offset voltage, and the stability are the main specifications of this type of bandgap reference source and they are included into the geometric program presented in this work. An example of the design using the geometric program formulated in this work, shows the possibility of designing the bandgap source in a few minutes with low errors between the geometric program results and the simulation results.

APA, Harvard, Vancouver, ISO, and other styles

12

Nissinen, I. (Ilkka). "CMOS time-to-digital converter structures for the integrated receiver of a pulsed time-of-flight laser rangefinder." Doctoral thesis, Oulun yliopisto, 2011. http://urn.fi/urn:isbn:9789514295478.

Full text

Abstract:

Abstract The aim of this thesis was to develop time-to-digital converters (TDC) for the integrated receiver of a pulsed time-of-flight (TOF) laser rangefinder aiming at cm-level accuracy over an input range of 10 m – 15 m. A simple structure, a high integration level and low power consumption are the desired features for such a TDC. From the pulsed TOF laser rangefinder point of view an integrated receiver consisting of both the TDC and the receiver channel on the same die offers the possibility of manufacturing these laser rangefinders with a high integration level and at a low price to fulfil the needs of mass industrial markets. The heart of the TDC is a CMOS ring oscillator, the clock frequency of which is used to calculate the full clock cycles between timing signals, the positions of the timing signals inside the clock period being determined by storing the state of the phase of the ring oscillator for each timing signal. This will improve the resolution of the TDC. Also, additional delay lines are used to generate multiple timing signals, each having a time difference of a fraction of that of the ring oscillator. This will further improve the resolution of the whole TDC. To achieve stable results regardless of temperature and supply voltage variations, the TDC is locked to an on-chip reference voltage, or the resolution of the TDC is calibrated before the actual time interval measurement. The systematic walk error in the receiver channel caused by amplitude variation in the received pulse is compensated for by the TDC measuring the slew rate of the received pulse. This time domain compensation method is not affected by the low supply voltage range of modern CMOS technologies. Three TDC prototypes were tested. A single-shot precision standard deviation of 16 ps (2.4 mm) and a power consumption of 5.3 mW/channel were achieved at best over an input range of 100 ns (15 m). The temperature drifts of an on-chip voltage reference-locked TDC and a TDC based on the calibration method were 90 ppm/°C and 0.27 ps/°C, respectively. The results also showed that a pulsed TOF laser rangefinder with cm-level accuracy over a 0 – 15 m input range can be realized using the integrated receiver with the time domain walk error compensation described here
Tiivistelmä Väitöskirjatyön tavoitteena oli kehittää aika-digitaalimuunninrakenteita valopulssin kulkuajan mittaukseen perustuvan lasertutkan integroituun vastaanottimeen. Tavoitteena oli saavuttaa senttimetriluokan tarkkuus 10 m – 15 m mittausalueella koko lasertutkan osalta. Aika-digitaalimuuntimelta vaaditaan yksinkertaista rakennetta, korkeaa integroimisastetta ja matalaa tehonkulutusta. Integroitu vastaanotin sisältää sekä aika-digitaalimuuntimen että vastaanotinkanavan ja tarjoaa mahdollisuuden korkeasti integroidun lasertutkan valmistukseen halvalla teollisuuden massamarkkinoiden tarpeisiin. Aika-digitaalimuuntimen ytimenä toimii monivaiheinen CMOS-rengasoskillaattori. Aika-digitaalimuunnos perustuu rengasoskillaattorin täysien kellojaksojen laskentaan laskurilla ajoitussignaalien välillä. Lisäksi rengasoskillaatorin jokaisesta vaiheesta otetaan näyte ajoitussignaaleilla niiden paikkojen määrittämiseksi kellojakson sisällä, jolloin aika-digitaalimuuntimen erottelutarkkuutta saadaan parannettua. Erottelutarkkuutta parannetaan lisää viivästämällä ajoitussignaaleja viive-elementeillä ja muodostamalla näin useita erillisiä ajoitussignaaleja, joiden väliset viive-erot ovat murto-osa rengasoskillaattorin viive-elementin viiveestä. Aika-digitaalimuunnin stabiloidaan käyttöjännite- ja lämpötilavaihteluja vastaan lukitsemalla se integroidun piirin sisäiseen jännitereferenssiin, tai sen erottelutarkkuus määritetään ennen varsinaista aikavälinmittausta erillisellä kalibrointimittauksella. Vastaanotetun valopulssin amplitudivaihtelun aiheuttama systemaattinen ajoitusvirhe integroidussa vastaanotinkanavassa kompensoidaan mittaamalla vastaanotetun valopulssin nousunopeus aika-digitaalimuuntimella. Tällainen aikatasoon perustuva kompensointimetodi on myös suorituskykyinen nykyisissä matalakäyttöjännitteisissä CMOS-teknologioissa. Työssä valmistettiin ja testattiin kolme aika-digitaalimuunninprototyyppiä. Muuntimien kertamittaustarkkuuden keskihajonta oli parhaimmillaan 16 ps (2,4 mm) ja tehonkulutus alle 5,3 mW/kanava mittausetäisyyden olessa alle 100 ns (15 m). Sisäiseen jännitereferenssiin lukitun aika-digitaalimuuntimen lämpötilariippuvuudeksi mitattiin 90 ppm/°C ja kalibrointimenetelmällä saavutettiin 0,27 ps/°C lämpötilariipuvuus. Työssä saavutetut tulokset osoittavat lisäksi, että valopulssin kulkuajan mittaukseen perustuvalla lasertutkalla on saavutettavissa senttimetriluokan tarkkuus 0 – 15 m mittausalueella käyttämällä tässä työssä esitettyä integroitua vastaanotinta ja aikatason ajoitusvirhekompensointia

APA, Harvard, Vancouver, ISO, and other styles

13

Toledo, Pedro Filipe Leite Correia de. "Modelamento e análise do efeito de coeficiente nulo de temperatura (ZTC) do Mosfet para aplicações análogicas de baixa sensibilidade têrmica." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/140814.

Full text

Abstract:

A contínua miniaturização das tecnologias CMOS oferece maior capacidade de integração e, consequentemente, as variações de temperatura dentro de uma pastilha de silício têm se apresentado cada vez mais agressivas. Ademais, dependendo da aplicação, a temperatura ambiente a qual o CHIP está inserido pode variar. Dessa maneira, procedimentos para diminuir o impacto dessas variações no desempenho do circuito são imprescindíveis. Tais métodos devem ser incluídos em ambos fluxos de projeto CMOS, analógico e digital, de maneira que o desempenho do sistema se mantenha estável quando a temperatura oscilar. A ideia principal desta dissertação é propor uma metodologia de projeto CMOS analógico que possibilite circuitos com baixa dependência térmica. Como base fundamental desta metodologia, o efeito de coeficiente térmico nulo no ponto de polarização da corrente de dreno (ZTC) e da transcondutância (GZTC) do MOSFET são analisados e modelados. Tal modelamento é responsável por entregar ao projetista analógico um conjunto de equações que esclarecem como a temperatura influencia o comportamento do transistor e, portanto, o comportamento do circuito. Essas condições especiais de polarização são analisadas usando um modelo de MOSFET que é contínuo da inversão fraca para forte. Além disso, é mostrado que as duas condições ocorrem em inversão moderada para forte em qualquer processo CMOS. Algumas aplicações são projetadas usando a metodologia proposta: duas referências de corrente baseadas em ZTC, duas referências de tensão baseadas em ZTC, e quatro circuitos gm-C polarizados em GZTC. A primeira referência de corrente é uma Corrente de Referência CMOS Auto-Polarizada (ZSBCR), que gera uma referência de 5uA. Projetada em CMOS 180 nm, a referência opera com uma tensão de alimentação de 1.4 à 1.8 V, ocupando uma área em torno de 0:010mm2. Segundo as simulações, o circuito apresenta um coeficiente de temperatura efetivo (TCeff ) de 15 ppm/oC para -45 à +85 oC e uma sensibilidade à variação de processo de = = 4:5% incluindo efeitos de variabilidade dos tipos processo e descasamento local. A sensibilidade de linha encontrada nas simulações é de 1%=V . A segunda referência de corrente proposta é uma Corrente de Referência Sem Resistor Auto-Polarizada com Capacitor Chaveado (ZSCCR). O circuito é projetado também em 180 nm, resultando em uma corrente de referência de 5.88 A, para uma tensão de alimentação de 1.8 V, e ocupando uma área de 0:010mm2. Resultados de simulações mostram um TCeff de 60 ppm/oC para um intervalo de temperatura de -45 à +85 oC e um consumo de potência de 63 W. A primeira referência de tensão proposta é uma Referência de Tensão resistente à pertubações eletromagnéticas contendo apenas MOSFETs (EMIVR), a qual gera um valor de referência de 395 mV. O circuito é projetado no processo CMOS 130 nm, ocupando em torno de 0.0075 mm2 de área de silício, e consumindo apenas 10.3 W. Simulações pós-leiaute apresentam um TCeff de 146 ppm/oC, para um intervalo de temperatura de 55 à +125oC. Uma fonte EMI de 4 dBm (1 Vpp de amplitude) aplicada na alimentação do circuito, de acordo com o padrão Direct Power Injection (DPI), resulta em um máximo de desvio DC e ondulação Pico-à-Pico de -1.7 % e 35.8m Vpp, respectivamente. A segunda referência de tensão é uma Tensão de Referência baseada em diodo Schottky com 0.5V de alimentação (SBVR). Ela gera três saídas, cada uma utilizando MOSFETs com diferentes tensões de limiar (standard-VT , low-VT , e zero-VT ). Todos disponíveis no processo adotado CMOS 130 nm. Este projeto resulta em três diferentes voltages de referências: 312, 237, e 51 mV, apresentando um TCeff de 214, 372, e 953 ppm/oC no intervalo de temperatura de -55 à 125oC, respectivamente. O circuito ocupa em torno de 0.014 mm2, consumindo um total de 5.9 W. Por último, circuitos gm-C são projetados usando o conceito GZTC: um emulador de resistor, um inversor de impedância, um filtro de primeira ordem e um filtro de segunda ordem. Os circuitos também são simulados no processo CMOS 130 nm, resultando em uma melhora na estabilidade térmica dos seus principais parâmetros, indo de 27 à 53 ppm/°C.
Continuing scaling of Complementary Metal-Oxide-Semiconductor (CMOS) technologies brings more integration and consequently temperature variation has become more aggressive into a single die. Besides, depending on the application, room ambient temperature may also vary. Therefore, procedures to decrease thermal dependencies of eletronic circuit performances become an important issue to include in both digital and analog Integrated Circuits (IC) design flow. The main purpose of this thesis is to present a design methodology for a typical CMOS Analog design flow to make circuits as insensitivity as possible to temperature variation. MOSFET Zero Temperature Coefficient (ZTC) and Transconductance Zero Temperature Coefficient (GZTC) bias points are modeled to support it. These are used as reference to deliver a set of equations that explains to analog designers how temperature will change transistor operation and hence the analog circuit behavior. The special bias conditions are analyzed using a MOSFET model that is continuous from weak to strong inversion, and both are proven to occur always from moderate to strong inversion operation in any CMOS fabrication process. Some circuits are designed using proposed methodology: two new ZTC-based current references, two new ZTC-based voltage references and four classical Gm-C circuits biased at GZTC bias point (or defined here as GZTC-C filters). The first current reference is a Self-biased CMOS Current Reference (ZSBCR), which generates a current reference of 5 A. It is designed in an 180 nm process, operating with a supply voltage from 1.4V to 1.8 V and occupying around 0:010mm2 of silicon area. From circuit simulations the reference shows an effective temperature coefficient (TCeff ) of 15 ppm/oC from 45 to +85oC, and a fabrication process sensitivity of = = 4:5%, including average process and local mismatch. Simulated power supply sensitivity is estimated around 1%/V. The second proposed current reference is a Resistorless Self-Biased ZTC Switched Capacitor Current Reference (ZSCCR). It is also designed in an 180 nm process, resulting a reference current of 5.88 A under a supply voltage of 1.8 V, and occupying a silicon area around 0:010mm2. Results from circuit simulation show an TCeff of 60 ppm/oC from -45 to +85 oC and a power consumption of 63 W. The first proposed voltage reference is an EMI Resisting MOSFET-Only Voltage Reference (EMIVR), which generates a voltage reference of 395 mV. The circuit is designed in a 130 nm process, occupying around 0.0075 mm2 of silicon area while consuming just 10.3 W. Post-layout simulations present a TCeff of 146 ppm/oC, for a temperature range from 55 to +125oC. An EMI source of 4 dBm (1 Vpp amplitude) injected into the power supply of circuit, according to Direct Power Injection (DPI) specification results in a maximum DC Shift and Peak-to-Peak ripple of -1.7 % and 35.8m Vpp, respectively. The second proposed voltage reference is a 0.5V Schottky-based Voltage Reference (SBVR). It provides three voltage reference outputs, each one utilizing different threshold voltage MOSFETs (standard-VT , low-VT , and zero-VT ), all available in adopted 130 nm CMOS process. This design results in three different and very low reference voltages: 312, 237, and 51 mV, presenting a TCeff of 214, 372, and 953 ppm/oC in a temperature range from -55 to 125oC, respectively. It occupies around 0.014 mm2 of silicon area for a total power consumption of 5.9 W. Lastly, a few example Gm-C circuits are designed using GZTC technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits are simulated in a 130 nm CMOS commercial process, resulting improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/°C.

APA, Harvard, Vancouver, ISO, and other styles

14

Piccin, Yohan. "Durcissement par conception d'ASIC analogiques." Thesis, Bordeaux, 2014. http://www.theses.fr/2014BORD0145/document.

Full text

Abstract:

Les travaux de cette thèse sont axés sur le durcissement à la dose cumulée des circuits analogiques associés aux systèmes électroniques embarqués sur des véhicules spatiaux, satellites ou sondes. Ces types de circuits sont réputés pour être relativement sensibles à la dose cumulée, parfois dès quelques krad, souvent en raison de l’intégration d’éléments bipolaires. Les nouvelles technologies CMOS montrent par leur intégration de plus en plus poussée, un durcissement naturel à cette dose. L’approche de durcissement proposée ici, repose sur un durcissement par la conception d’une technologie commerciale « full CMOS » du fondeur ST Microelectronics, appelée HCMOS9A. Cette approche permet d’assurer la portabilité des méthodes de durcissement proposées d’une technologie à une autre et de rendre ainsi accessible les nouvelles technologies aux systèmes spatiaux. De plus, cette approche de durcissement permet de faire face aux coûts croissants de développement et d’accès aux technologies durcies. Une première technique de durcissement à la dose cumulée est appliquée à une tension de référence « full CMOS ». Elle ne fait intervenir ni jonction p-n parasites ni précautions delay out particulières mais la soustraction de deux tensions de seuil qui annulent leurs effets à la dose cumulée entre elles. Si les technologies commerciales avancées sont de plus en plus utilisées pour des applications spécialement durcies, ces dernières exhibent en contrepartie de plus grands offsets que les technologies bipolaires. Cela peut affecter les performances des systèmes. La seconde technique étudiée : l’auto zéro, est une solution efficace pour réduire les dérives complexes dues entre autres à la température, de l’offset d’entrée des amplificateurs opérationnels. Le but ici est de prouver que cette technique peut tout aussi bien contrebalancer les dérives de l’offset dues à la dose cumulée
The purpose of this thesis work is to investigate circuit design techniques to improve the robustness to Total Ionizing Dose (TID) of analog circuits within electronic systems embedded in space probes, satellites and vehicles. Such circuits often contain bipolartransistor components which are quite sensitive to cumulated radiation dose. However highly integrated CMOS technology has been shown to exhibit better natural TDI hardening.The approach proposed here is a hardening by design using a full CMOS semiconductor technology commercially available from ST Microelectronics calledHCMOS9A. The proposed generic hardening design methods will be seen to be compatibleand applicable to other existing or future process technologies. Furthermore this approach addresses the issue of ever-increasing development cost and access to hardened technologies.The first TID hardening technique proposed is applied to a full-CMOS voltage reference. This technique does not involve p-n junctions nor any particular layout precaution but instead is based on the subtraction of two different threshold voltages which allows the cancellation of TDI effects. While the use of advanced commercial CMOS technologies for specific radiation hardened applications is becoming more common, these technologies suffer from larger inputoffs et voltage drift than their bipolar transistor counterparts, which can impact system performance. The second technique studied is that of auto-zeroing, which is an efficient method to reduce the complex offset voltage drift mechanisms of operational amplifiers due to temperature. The purpose here is to prove that this technique can also cancel input offset voltage drift due to TID.Index term : hardening, cumulated dose, CMOS technology, voltage reference,operational amplifier

APA, Harvard, Vancouver, ISO, and other styles

15

Chandernagor, Lucie. "Etude, conception et réalisation d’un récepteur d’activation RF ultra basse consommation pour l’internet des objets." Thesis, Limoges, 2016. http://www.theses.fr/2016LIMO0126/document.

Full text

Abstract:

Grâce au confort d’utilisation qu’elles procurent, les technologies sans fil se retrouvent aujourd’hui dans un vaste panel d’applications. Ainsi le nombre d’éléments de transmission/réception radio se multiplie. Aujourd’hui pour réduire les consommations des éléments radio, il faut les rendre davantage efficaces notamment pour la partie réception. En effet, pour les communications asynchrones, les récepteurs consomment inutilement de l’énergie à attendre qu’une transmission soit faite. Dans l’objectif de réduire ce gaspillage d’énergie, des nouveaux standards ont vu le jour tel que le Zigbee et le Bluetooth Low Energy. Les performances en consommation procurées par ces deux standards résident sur leur fonction périodique à très faible rapport cyclique. Une nouvelle solution émergente pour réduire drastiquement la consommation des récepteurs en les rendant plus efficaces est l’utilisation de récepteur d’activation. Les récepteurs d’activation ou récepteur de réveil sont des récepteurs simples ce qui leur permet d’atteindre une ultra basse consommation uniquement en charge de guetter l’arrivée d’une trame et de réveiller le récepteur principal, placé en veille au préalable, pour traitement de cette dernière. Le récepteur d’activation proposé ici a été réalisé dans la technologie CMOS 160 nm de NXP. Il offre une sensibilité de -54 dBm, pour une consommation moyenne de 35 μA, prodiguant une portée de 70m à 433,92 MHz pour une puissance de 10 dBm émis. Ce récepteur ASK se distingue des autres récepteurs d’activation par le système de calibration breveté avec ajustement automatique la tension de référence requise pour la démodulation. Ce système rend le circuit robuste au problème d’offset DC et ne consomme aucun courant lorsque le circuit est en écoute. Le récepteur d’activation reconnaît un code de Manchester de 24 bits à 25 kbps, programmable grâce à une interface SPI
Wireless technologies are now widespread due to the easiness of use they provide. Consequently, the number of radio devices increases. Despite of the efforts to reduce radio circuits power consumption as they are more and more numerous, now they must achieve ultra-low power consumption. Today, radio devices are made more efficient to reduce their power consumption especially for the receiving part. Indeed, for asynchronous communication, a lot of energy is wasted by the receiver waiting for a transmission. In order to avoid this waste, new standards have been created such as Zigbee and Bluetooth Low Energy. Due to periodic operation with ultra-low duty cycle, they provide ultra-low power consumption. Another solution to drastically reduce the power consumption has emerged, wake-up receiver. Wake-up receivers are based in simple architecture to provide ultra-low power consumption, they are only in charge to wait for a frame and when it occurs, wake-up the main receiver put in standby mode before that. The proposed wake-up receiver has been designed in NXP CMOS technology 160 μm. It provides a-54 dBm sensitivity, consuming 35 μA which allows a 70m range considering a 10 dBm emitter at 433,92 MHz. This wake-up receiver operates with ASK modulation, compared to others it provides a smart patented calibration system to get the necessary reference voltage for demodulation. This mechanism provide DC offset robustness and does not drain any current while the wake-up receiver is operating. To wake up the main receiver a 24 bits programmable Manchester code is required. This code at 25 kbps is programmable by the use of an SPI interface

APA, Harvard, Vancouver, ISO, and other styles

16

Colombo, Dalton Martini. "Bandgap voltage references in submicrometer CMOS technology." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2009. http://hdl.handle.net/10183/16136.

Full text

Abstract:

Referências de tensão são blocos fundamentais em uma série de aplicações de sinais mistos e de rádio frequência, como por exemplo, conversores de dados, PLL's e conversores de potência. A implementação CMOS mais usada para referências de tensão é o circuito Bandgap devido sua alta previbilidade, e baixa dependência em relação à temperatura e tensão de alimentação. Este trabalho estuda aplicação de Referência de Tensão Bandgap. O princípio, as topologias tradicionalmente usadas para implementar este método e as limitações que essas arquiteturas sofrem são investigadas. Será também apresentada uma pesquisa das questões recentes envolvendo alta precisão, operação com baixa tensão de alimentação e baixa potência, e ruído de saída para as referências Bandgap fabricadas em tecnologias submicrométricas. Além disso, uma investigação abrangente do impacto causado pelo o processo da fabricação e do ruído no desempenho da referência é apresentada. Será mostrado que o ruído de saída pode limitar a precisão dos circuitos Bandgap e seus circuitos de ajuste. Para desenvolver nosso trabalho, três Referências Bandgap foram projetadas utilizando o processo IBM 7RF 0.18 micra com uma tensão de alimentação de 1.8V. Também foram projetados os leiautes desses circuitos para prover informações pósleiaute extraídos e resultados de simulação elétrica. Este trabalho provê uma discussão de algumas topologias e das práticas de projeto para referências Bandgap.
A Voltage Reference is a pivotal block in several mixed-signal and radio-frequency applications, for instance, data converters, PLL's and power converters. The most used CMOS implementation for voltage references is the Bandgap circuit due to its highpredictability, and low dependence of the supply voltage and temperature of operation. This work studies the Bandgap Voltage References (BGR). The most relevant and the traditional topologies usually employed to implement Bandgap Voltage References are investigated, and the limitations of these architectures are discussed. A survey is also presented, discussing the most relevant issues and performance metrics for BGR, including, high-accuracy, low-voltage and low-power operation, as well as the output noise of Bandgap References fabricated in submicrometer technologies. Moreover, a comprehensive investigation on the impact of fabrication process effects and noise on the reference voltage is presented. It is shown that output noise can limit the accuracy of the BGR and trim circuits. To support and develop our work, three BGR´s were designed using the IBM 0.18 Micron 7RF process with a supply voltage of 1.8 V. The layouts of these circuits were also designed to provide post-extracted layout information and electrical simulation results. This work provides a comprehensive discussion on the structure and design practices for Bandgap References.

APA, Harvard, Vancouver, ISO, and other styles

17

Zimouche, Hakim. "Capteur de vision CMOS à réponse insensible aux variations de température." Phd thesis, Université de Grenoble, 2011. http://tel.archives-ouvertes.fr/tel-00656381.

Full text

Abstract:

Les capteurs d'images CMOS sont de plus en plus utilisés dans le domaine industriel : la surveillance, la défense, le médical, etc. Dans ces domaines, les capteurs d'images CMOS sont exposés potentiellement à de grandes variations de température. Les capteurs d?images CMOS, comme tous les circuits analogiques, sont très sensibles aux variations de température, ce qui limite leurs applications. Jusqu'à présent, aucune solution intégrée pour contrer ce problème n'a été proposée. Afin de remédier à ce défaut, nous étudions, dans cette thèse, les effets de la température sur les deux types d'imageurs les plus connus. Plusieurs structures de compensation sont proposées. Elles reprennent globalement les trois méthodes existantes et jamais appliquées aux capteurs d'images. La première méthode utilise une entrée au niveau du pixel qui sera modulée en fonction de l'évolution de la température. La deuxième méthode utilise la technique ZTC (Zero Température Coefficient). La troisième méthode est inspirée de la méthode de la tension de référence bandgap. Dans tous les cas, nous réduisons de manière très intéressante l'effet de la température et nous obtenons une bonne stabilité en température de -30 à 125°C. Toutes les solutions proposées préservent le fonctionnement initial de l'imageur. Elles n'impactent également pas ou peu la surface du pixel

APA, Harvard, Vancouver, ISO, and other styles

18

Parker, Kevin. "An on-chip trimming technique for CMOS voltage references." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp04/mq20686.pdf.

Full text

APA, Harvard, Vancouver, ISO, and other styles

19

Sassi, Mariela Mayumi Franchini Sasaki. "Projeto de fontes de tensão de referência através de metaheurísticas." Universidade de São Paulo, 2013. http://www.teses.usp.br/teses/disponiveis/18/18155/tde-26082013-134021/.

Full text

Abstract:

Geradores de referência, ou fontes de tensão de referência, são largamente empregados na composição de diversos circuitos eletrônicos, pois são responsáveis por gerar e manter uma tensão constante para o restante do circuito. Como se trata de um circuito analógico e que possui diversas condições a serem atendidas (baixo coeficiente de temperatura, baixa tensão de alimentação, baixa regulação de linha, dentre outras), sua complexidade é alta e isso se reflete no tempo/dificuldade de um projeto. Com a finalidade de aumentar a qualidade do circuito e diminuir o tempo de projeto, foi estudado o projeto de fontes de tensão de referência através da aplicação de metaheurísticas, que são métodos de otimização utilizados em problemas que não possuem solução analítica. As metaheurísticas aplicadas foram: algoritmos genéticos, simulated annealing e pattern search, todos disponíveis em uma toolbox de otimização do Matlab. A fonte projetada, utilizando uma topologia proposta neste trabalho, fornece uma tensão de referência de 0,302 V em 300 K a uma tensão mínima de operação de 1,01 V. O coeficiente de temperatura, no intervalo de -10°C a 90°C, é de 19 ppm/°C a 1,01 V e a regulação de linha, com tensão de alimentação no intervalo de 1,01 V a 2,5 V, é de 81 ppm/V a 300 K. O consumo de potência é de 4,2 \'mü\'W, também em 300 K e a 1,01 V e a área é de 0,061 \'MM POT.2\'. Como resultado, mostrou-se a eficiência da utilização destes métodos no dimensionamento de elementos do circuito escolhido e foi obtida uma fonte de tensão de referência que atende aos critérios estabelecidos e é superior quanto ao critério de regulação de linha, quando comparada a outras fontes da literatura. Neste trabalho, foi utilizada a tecnologia CMOS de 0,35 \'mü\'m da Austria Micro Systems (AMS).
Voltage references are widely employed to compose electronic circuits, since they are responsible for generating and maintaining a constant voltage to the rest of the circuit. As it is an analog circuit and it has several conditions to fulfill (low temperature coefficient, low supply voltage, low line regulation, among others), its complexity is high, which reflects at the time/difficulties of a design. In order to increase the quality of the circuit and to minimize the design time, it was studied voltage references design using metaheuristics, which are optimization methods used in problems with no analytical solution. The applied metaheuristics were: genetic algorithms, simulated annealing and pattern search, they are all available in an optimization toolbox at Matlab. The designed voltage reference, applying a topology proposed in this work, provides a reference voltage of 0.302 V at 300 K at a minimum supply voltage of 1.01 V. The temperature coefficient, from -10°C to 90°C, is 19 ppm/°C at 1.01 V and the line regulation, using a supply voltage from 1.01 V to 2.5 V, is 81 ppm/V at 300 K. The power consumption is 4.2 W also at 300 K and 1.01 V and the area is 0.061 \'MM POT.2\'. As a result, it was shown that those methods are efficient in sizing the devices of the chosen topology and it was obtained a voltage reference that fulfills all established criteria and that is superior at the line regulation criterion, when compared to other voltage reference of the literature. In this work, the 0.35-\'mü\'m CMOS technology provided by Austria Micro Systems (AMS) was used.

APA, Harvard, Vancouver, ISO, and other styles

20

Andersson, Martin. "Konstruktion av förstärkare och insamplingssteg till en PSAADC i 0.25 um CMOS." Thesis, Linköping University, Department of Electrical Engineering, 2002. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1132.

Full text

Abstract:

The aim and goal of this work has been to design and implement a voltage reference network for a 12-bit PSAADC, Parallell Successive Analog to Digital Converter. A chip containing the design has been sent away for fabrication. Because of the long processing time, no measurement data are presented. The main specifications for the voltage reference generator is to generate stable reference voltages with low noise and a good PSRR. Efforts has also been made to minimize the power consumption.

APA, Harvard, Vancouver, ISO, and other styles

21

Zeloufi, Mohamed. "Développement d’un convertisseur analogique-numérique innovant dans le cadre des projets d’amélioration des systèmes d’acquisition de l’expérience ATLAS au LHC." Thesis, Université Grenoble Alpes (ComUE), 2016. http://www.theses.fr/2016GREAT115.

Full text

Abstract:

À l’horizon 2024, l’expérience ATLAS prévoit de fonctionner à des luminosités 10 fois supérieures à la configuration actuelle. Par conséquent, l’électronique actuelle de lecture ne correspondra pas aux conditions de ces luminosités. Dans ces conditions, une nouvelle électronique devra être conçue. Cette mise à niveau est rendue nécessaire aussi par les dommages causés par les radiations et le vieillissement. Une nouvelle carte frontale va être intégrée dans l’électronique de lecture du calorimètre LAr. Un élément essentiel de cette carte est le Convertisseur Analogique-Numérique (CAN) présentant une résolution de 12bits pour une fréquence d’échantillonnage de 40MS/s, ainsi qu’une résistance aux irradiations. Compte tenu du grand nombre des voies, ce CAN doit remplir des critères sévères sur la consommation et la surface. Le but de cette thèse est de concevoir un CAN innovant qui peut répondre à ces spécifications. Une architecture à approximations successives (SAR) a été choisie pour concevoir notre CAN. Cette architecture bénéficie d’une basse consommation de puissance et d’une grande compatibilité avec les nouvelles technologies CMOS. Cependant, le SAR souffre de certaines limitations liées principalement aux erreurs de décisions et aux erreurs d’appariement des capacités du CNA. Deux prototypes de CAN-SAR 12bits ont été modélisés en Matlab afin d’évaluer leur robustesse. Ensuite les conceptions ont été réalisées dans une technologie CMOS 130nm d’IBM validée par la collaboration ATLAS pour sa tenue aux irradiations. Les deux prototypes intègrent un algorithme d’approximations avec redondance en 14 étapes de conversion, qui permet de tolérer des marges d’erreurs de décisions et d’ajouter une calibration numérique des effets des erreurs d’appariement des capacités. La partie logique de nos CAN est très simplifiée pour minimiser les retards de génération des commandes et la consommation d’énergie. Cette logique exécute un algorithme monotone de commutation des capacités du CNA permettant une économie de 70% de la consommation dynamique par rapport à un algorithme de commutation classique. Grâce à cet algorithme, une réduction de capacité totale est aussi obtenue : 50% en comparant notre premier prototype à un seul segment avec une architecture classique. Pour accentuer encore plus le gain en termes de surface et de consommation, un second prototype a été réalisé en introduisant un CNA à deux segments. Cela a abouti à un gain supplémentaire d’un facteur 7,64 sur la surface occupée, un facteur de 12 en termes de capacité totale, et un facteur de 1,58 en termes de consommation. Les deux CAN consomment respectivement une puissance de ~10,3mW et ~6,5mW, et ils occupent respectivement une surface de ~2,63mm2 et ~0,344mm2.Afin d’améliorer leurs performances, un algorithme de correction numérique des erreurs d’appariement des capacités a été utilisé. Des buffers de tensions de référence ont étés conçus spécialement pour permettre la charge/décharge des capacités du convertisseur en hautes fréquences et avec une grande précision. En simulations électriques, les deux prototypes atteignent un ENOB supérieur à 11bits tout en fonctionnant à la vitesse de 40MS/s. Leurs erreurs d’INL simulés sont respectivement +1,14/-1,1LSB et +1,66/-1,72LSB.Les résultats de tests préliminaires du premier prototype présentent des performances similaires à celles d’un CAN commercial de référence sur notre carte de tests. Après la correction, ce prototype atteint un ENOB de 10,5bits et un INL de +1/-2,18LSB. Cependant suite à une panne de carte de tests, les résultats de mesures du deuxième prototype sont moins précis. Dans ces circonstances, ce dernier atteint un ENOB de 9,77bits et un INL de +7,61/-1,26LSB. En outre la carte de tests actuelle limite la vitesse de fonctionnement à ~9MS/s. Pour cela une autre carte améliorée a été conçue afin d’atteindre un meilleur ENOB, et la vitesse souhaitée. Les nouvelles mesures vont être publiées dans le futur
By 2024, the ATLAS experiment plan to operate at luminosities 10 times the current configuration. Therefore, many readout electronics must be upgraded. This upgrade is rendered necessary also by the damage caused by years of total radiations’ effect and devices aging. A new Front-End Board (FEB) will be designed for the LAr calorimeter readout electronics. A key device of this board is a radiation hard Analog-to-Digital Converter (ADC) featuring a resolution of 12bits at 40MS/s sampling rate. Following the large number of readout channels, this ADC device must display low power consumption and also a low area to easy a multichannel design.The goal of this thesis is to design an innovative ADC that can deal with these specifications. A Successive Approximation architecture (SAR) has been selected to design our ADC. This architecture has a low power consumption and many recent works has shown his high compatibility with modern CMOS scaling technologies. However, the SAR has some limitations related to decision errors and mismatches in capacitors array.Using Matlab software, we have created the models for two prototypes of 12bits SAR-ADC which are then used to study carefully their limitations, to evaluate their robustness and how it could be improved in digital domain.Then the designs were made in an IBM 130nm CMOS technology that was validated by the ATLAS collaboration for its radiation hardness. The prototypes use a redundant search algorithm with 14 conversion steps allowing some margins with comparator’s decision errors and opening the way to a digital calibration to compensate the capacitors mismatching effects. The digital part of our ADCs is very simplified to reduce the commands generation delays and saving some dynamic power consumption. This logic follows a monotonic switching algorithm which saves about70% of dynamic power consumption compared to the conventional switching algorithm. Using this algorithm, 50% of the total capacitance reduction is achieved when one compare our first prototype using a one segment capacitive DAC with a classic SAR architecture. To boost even more our results in terms of area and consumption, a second prototype was made by introducing a two segments DAC array. This resulted in many additional benefits: Compared to the first prototype, the area used is reduced in a ratio of 7,6, the total equivalent capacitance is divided by a factor 12, and finally the power consumption in improved by a factor 1,58. The ADCs respectively consume a power of ~10,3mW and ~6,5mW, and they respectively occupy an area of ~2,63mm2 and ~0,344mm2.A foreground digital calibration algorithm has been used to compensate the capacitors mismatching effects. A high frequency open loop reference voltages buffers have been designed to allow the high speed and high accuracy charge/discharge of the DAC capacitors array.Following electrical simulations, both prototypes reach an ENOB better than 11bits while operating at the speed of 40MS/s. The INL from the simulations were respectively +1.14/-1.1LSB and +1.66/-1.72LSB.The preliminary testing results of the first prototype are very close to that of a commercial 12bits ADC on our testing board. After calibration, we measured an ENOB of 10,5bits and an INL of +1/-2,18LSB. However, due to a testing board failure, the testing results of the second prototype are less accurate. In these circumstances, the latter reached an ENOB of 9,77bits and an INL of +7,61/-1,26LSB. Furthermore the current testing board limits the operating speed to ~9MS/s. Another improved board was designed to achieve a better ENOB at the targeted 40MS/s speed. The new testing results will be published in the future

APA, Harvard, Vancouver, ISO, and other styles

22

Chang, Ting-Wei, and 張庭瑋. "CMOS current reference and voltage reference design." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/53278481139150247466.

Full text

Abstract:

碩士
北台科學技術學院
機電整合研究所
94
This paper presents some new circuits including CMOS circuit reference and voltage reference. The architecture of the current references is produced not only by adding a positive supply voltage coefficient current reference and a negative supply voltage coefficient current reference to cancel out the supply voltage variations but also by adding a positive temperature coefficient current reference and a negative temperature coefficient current reference to cancel out the temperature variation. About the negative supply voltage coefficient current reference, we can product it by subtracting two current references with different positive supply voltage coefficient. This paper also presents a sub-1v voltage reference, which is different from the traditional bandgap reference. The main architecture of the voltage reference is composed of a positive temperature coefficient voltage reference and a negative temperature coefficient voltage reference. At first, by putting two different bias voltage of the bipolar junction transistors into the differential pair and adjusting the transistor size, we can obtain a voltage reference with a positive temperature coefficient; Secondly, by putting a ground voltage and a bias voltage of the bipolar junction transistors into the differential pair and adjusting the transistor size, we can obtain a voltage reference with a negative temperature coefficient. Finally, by putting the positive coefficient voltage reference and the negative temperature coefficient voltage reference into the differential pair and adjusting the transistor size, we can obtain a voltage reference with less sensitive to temperature variation.

APA, Harvard, Vancouver, ISO, and other styles

23

Liao, Jia-Zheng, and 廖家正. "Design of A CMOS Reference Voltage." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/3h6nk8.

Full text

Abstract:

碩士
國立虎尾科技大學
電子工程系碩士班
101
In this thesis, a CMOS differential-mode reference voltage circuit has been proposed. By properly using the positive and negative temperature coefficient parameters, a zero temperature-coefficient can be achieved. The proposed circuits are based on the traditional bandgap voltage reference circuit architecture with an additional current mirror and a proportional-to-absolute-temperature current source which is composed of current mirrors. As compared with the existed differential-mode reference voltage circuit, the proposed circuit does not need an operational amplifier, therefore it benefits from simpler circuit architecture, less chip area, and less power consumption. Besides the detailed design principle, the HSPICE and LAKER simulation program with 0.35-um and 0.18-um process parameters have been used to perform the pre-layout and post-layout simulation. According to the post-layout simulation results, as the supply voltages is 3.3V, the differential-mode output voltage reference circuit shows that, as the temperature varies from -20oC to 120oC, the corresponding output voltage changes only 1.3mV(0.225%), the corresponding power dissipation is 2.354mW and the temperature-coefficient is 16.11 ppm/˚C. In addition, if a transistor and a resistor are removed from the proposed differential-mode output voltage reference circuit, a single-ended mode reference voltage with zero temperature coefficient can be obtained. According to the post-layout simulation results, when the supply voltages is 2.8V, and as the temperature varies from -20oC to 120oC, the corresponding output voltage changes only 2.01mV(0.387%), the corresponding power dissipation is 1.412mW and the temperature-coefficient is 27.79 ppm/˚C. All the simulation results are consistent with the theoretic analysis. The proposed circuits can be applied to different analog circuits.

APA, Harvard, Vancouver, ISO, and other styles

24

Chiang, Tzung-Yin, and 江宗殷. "Temperature-compensated CMOS voltage reference circuit." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/07003708814603618036.

Full text

Abstract:

碩士
國立清華大學
工程與系統科學系
93
Reference circuits have been studying for many years. Following the vigorous development of portable electronic products, integrated circuits with low voltage and small area have become the core part of the recent research. Parasitic vertical bipolar junction transistors are commonly used in CMOS voltage reference circuits for a better stability. Recently, MOS reference circuits have been used to replace BJT ones in order to reduce the chip area and supply voltage. Whether BJT or MOS is utilized, the problem that resistances parallelizing on either side of BJT or MOS generally occupy quite large ratio of chip area under the consideration of power consumption and loading parasitic capacitances of op-amp still exists. Another problem worthy of our concern is that spurious signals coming from the supply voltage cannot be adequately rejected and may couple into the circuit to degrade output signal in high frequency applications. This thesis aims to improve the above problems and proposes a novel voltage reference circuit. A current mirror is designed for temperature compensation and large resistors are defeasible for reduction chip area. Besides, it has been implemented by a 0.18 μm CMOS process with a chip area of 0.023 mm2. Simulation shows that the variation of temperature coefficient is from 59.5 to 63.8 ppm/℃ under the temperature range from -40 to 100 ℃ and a supply voltage variation from 1.2 to 1.98 V. The power noise rejection ratio is -70 dB at 10 kHz with 1.2V supply voltage. In summary, the thesis adopts a current mirror to achieve low-temperature-drift reference voltage and abandons large resistances on design consideration. With this approach, power noise rejection ration is reduced.

APA, Harvard, Vancouver, ISO, and other styles

25

Cai, Bo-Rong, and 蔡柏戎. "Design And application Of CMOS Reference Voltage." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/4r55n9.

Full text

Abstract:

碩士
國立虎尾科技大學
電子工程系碩士班
102
In this thesis, a differential-mode reference voltage circuit with cascode architecture has been proposed. The design principle is using both the positive and the negative temperature coefficient parameters in BJT to compensate each other, and then a zero temperature coefficient output reference voltage can be achieved. Circuit simulations has used two different circuit architectures to realize the reference voltage, and both the advantages and disadvantages have been discussed. As compared with the existed differential mode reference voltage circuits, the proposed circuits benefits from simpler circuit architecture, less chip area, and also they don''t need any operational amplifier . Detailed design principle has been disclosed in this thesis, also the HSPICE and LAKER simulation programs with 0.35-μm process parameters have been used to perform the pre-layout and post-layout simulation. The supply voltages of the proposed circuits are 3.3V and 5V, respectively. The test temperature ranges from -20°C to 120°C. According to the simulation results, the double-cascode architecture can enhance the PSRR. When the supply voltage is 3.3V and the temperature is 25°C, the output voltage of the proposed cascode architecture reference voltage circuit is 426.2mv, the maximum output voltage variation is 1.37mv, the power dissipation is 0.5149mW, and the corresponding PSRR is -27.52dB. As the supply voltage is 5V and the temperature is 25°C, the output voltage of the proposed double-cascode architecture reference voltage circuit is 500.27mv, the maximum output voltage variation is only 1.0236mv, the power dissipation is 0.96502mW, and the corresponding PSRR is -45dB. All the simulation results are consistent with the theoretic analysis. The proposed circuits can be applied to vehicle electronic devices design and other digital and analog circuits.

APA, Harvard, Vancouver, ISO, and other styles

26

Wang, Bo-Lun, and 王柏倫. "Design of CMOS Low-Power Reference Voltage." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/zwuwk7.

Full text

Abstract:

碩士
國立虎尾科技大學
電子工程系碩士班
105
In this thesis, three Low-Power CMOS Reference Voltage circuits have been presented. The first circuit is with single-ended output voltage, and the second and third circuit provides multiple output voltages. In the proposed circuits, MOS transistors are biased to operate in the weak inversion region to achieve the low-power consumption characteristics. Appropriate combination of the positive and the negative temperature coefficients of the voltages, the zero-temperature coefficient reference voltage can be achieved. As compared with the existed circuits, the proposed circuits benefits from its low power consumption, simple structure, and less wafer area. In this thesis, both the pre/post layout simulation and measurement results with 0.18m and 0.35m process parameters are given to show the validity of the proposed circuits. The proposed circuits can be applied to embedded medical instruments and portable electronic devices.

APA, Harvard, Vancouver, ISO, and other styles

27

Yang, Julian, and 楊宙穎. "CMOS Temperature Sensor and Bandgap Voltage Reference." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/64563h.

Full text

Abstract:

碩士
國立交通大學
電子物理系所
92
A temperature sensing system with digital output consists of a front part and a rear part. The front part includes temperature sensor and bandgap voltage reference. The rear part is an analog to digital converter (ADC). In CMOS technology, the BJT device is used as the basic temperature sensor. The base-emitter voltage (VEB) can be approximated as a linear function of temperature. By using it, temperature sensor and bandgap voltage reference can be accomplished. The simulation of the front part using a standard TSMC 0.25um 1P5M CMOS process is presented in the thesis. The designed PTAT (Proportional To Absolute Temperature) circuit has an output voltage in proportion to absolute temperature with 3.6mV / ℃. The reference voltage (Vref) is 1.21V with an effective temperature coefficient of 8.3 ppm/℃ from -25℃~125℃. Further more, A new type of bandgap voltage reference, in the form of , is proposed. We expand VEB(T) into Taylor series. After second-order compensation with one scaling factor a1=1 and a2 =-0.79, we will get a third-order temperature dependency of bandgap voltage reference. With current mode topology, the circuits design achieves a second-order compensation of VEB. It is simulated with the models of standard TSMC 0.18um 1P6M process. From simulation, the output voltage is 255mV with an effective temperature coefficient of 7.8 ppm/℃ for the temperature range -40℃~125℃. Total current consumption is about 408uA and power consumption is about 0.73mW at 25℃ for this proposed circuit.

APA, Harvard, Vancouver, ISO, and other styles

28

吳榮田. "Standard CMOS Low Operating Voltage Linear Type Bandgap Reference Voltage Generator." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/35770322350884476361.

Full text

Abstract:

碩士
國立臺灣大學
電機工程學研究所
90
For many modern analog circuits, it is very important to generate a power supply voltage and temperature independent reference voltage to improve the performance of circuits such as accuracy, reliability, yield rate and so on. In the past the linear type CMOS bandgap reference voltage generator was chosen as a reliable reference voltage source for many years because of its working very well. But the traditional linear type CMOS bandgap reference voltage generator cannot work properly when the power supply voltage is lower than 2V. Due to the progress of CMOS process and the application of ICs, the power supply voltage of many ICs has to be reduced less than 2V in the future. A novel architecture of current summation type linear CMOS bandgap reference voltage generator is proposed here to afford a reliable bandgap reference voltage generating circuit that can operate at 1.3V power supply perfectly.

APA, Harvard, Vancouver, ISO, and other styles

29

Lee, Chia-Yu, and 李佳祐. "A Low-Voltage Low-Temperature-Coefficient CMOS Bandgap Voltage Reference Generator." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/60462464118919911604.

Full text

Abstract:

碩士
國立臺灣大學
電子工程學研究所
94
Voltage references play an important role in modern integrated circuits systems. They are widely apdopted in many integrated circuits, such as A/D or D/A converters, power-management system, operational amplifiers, and linear regulators. They are used for defining input/output voltage range, baising current source of differential pairs, and providing a comparison reference for comparators. A precision voltage reference must be, inherently, well-defined and insensitive to temperature, power supply and load variations. The objective of this thesis is to design a bandgap voltage reference with input voltage 1.8V to 3.3V and output voltage around 1.2V. The bandgap voltage reference is intended for using in low dropout linear regulators (LDO). In order to reduce the supply voltage, the voltage reference is using low voltage operational amplifers in place of using conservative cascade current mirror. In addition, this thesis designs a 1-V bandgap voltage reference with temperature compensation to suit the current of low supply voltage. During design and analysis stages, the HSPICE is used for the simulation, modification and verification of the circuit.

APA, Harvard, Vancouver, ISO, and other styles

30

Murugeshappa, Ravi Gourapura. "A low-voltage, low-power CMOS bandgap reference." 2010. http://hdl.handle.net/2152/9162.

Full text

Abstract:

Bandgap reference circuits are used in a host of analog, digital, and mixed-signal systems to establish an accurate voltage reference for the entire IC. The most used CMOS implementation for voltage references is the bandgap circuit due to its high predictability, and low dependence of the supply voltage and temperature of operation. This work studies a CMOS implementation of a resistor-less bandgap reference, which consumes low power. The most relevant and traditional approaches usually employed to implement bandgap voltage references are investigated. The impact of process, power-supply, load and temperature variations has been analyzed and simulated. The functionality of critical components of the circuit has been verified through chip implementation.
text

APA, Harvard, Vancouver, ISO, and other styles

31

Brewer, Jerry. "High temperature SOI CMOS band-gap voltage reference." 2004. http://digital.library.okstate.edu/etd/umi-okstate-1188.pdf.

Full text

APA, Harvard, Vancouver, ISO, and other styles

32

Pai, Chia-Hung, and 白佳弘. "The curvature compensated Resistorless CMOS Voltage Reference Circuit." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/39164561216972109620.

Full text

Abstract:

碩士
國立彰化師範大學
電子工程學系
103
This thesis shows a CMOS bandgap reference without resistors, which is an application of PMOS voltage divider. The circuit is operated in 1.8 V. A translinear circuit is used to generate a second-order temperature compensation current, and this current component combined with reference current can decrease output reference voltage temperature coefficient further. The chip is fabricated with TSMC 0.18 µm CMOS technology. The TSMC 0.18 µm 1P6M CMOS models are used in the circuit simulation, and the post-layout simulation results show that: when the supply voltage VDD is 1.8 V and the temperature range is from -40 ℃ to 150 ℃, the average value of output voltage reference is about 484.8 mV, the deviation value is about 2.85 mV, the temperature coefficient is about 31.4 ppm/℃, the power consumption is about 448.9 µW. A 25 dB PSRR has been achieved up to 300 kHz. The measurement result when the supply voltage VDD is 1.8 V and the temperature range is from -40 ℃ to 150 ℃, the average value of output voltage reference is about 444.1 mV, the deviation value is about 57.5 mV, the power consumption is about 344.5 µW, and 20 dB PSRR has been achieved up to 300 kHz.

APA, Harvard, Vancouver, ISO, and other styles

33

黃全興. "CMOS circuit design for low reference voltage using bandgap." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/49468291675147213413.

Full text

Abstract:

碩士
國立中興大學
電機工程學系
91
Reference voltage generators are widely used in many applications from analog circuit to mixed-signal circuits such as ADC, DAC, DRAM and flash memories. These structures are required to provide a stable reference voltage with a low sensitivity to temperature and supply voltage. One of the most popular architectures is the band-gap reference. Due to the need of battery-operated systems for portability, low output reference voltage, low supply voltages and low power consumption will be the trends in the future VLSI products. Two new band-gap reference circuits operated at low supply voltages using 0.18m CMOS technology are presented in this thesis. These two circuits are designed by vertically parasitical BJTs in CMOS technology. The chip area of the new BGR circuit is small. The deviation of Vref is less than 12mV for the temperature ranging from —45 oC to 90 oC.

APA, Harvard, Vancouver, ISO, and other styles

34

TSENG, BO-WEI, and 曾柏崴. "CMOS Differential Output Reference Voltage Design for Practical Applications." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/qemgc8.

Full text

Abstract:

碩士
國立虎尾科技大學
電子工程系碩士班
106
In this thesis, three different kinds of CMOS differential output reference voltage circuits have been proposed. The design principle is properly combine the positive temperature-coefficient and negative temperature-coefficient parameters to achieve a zero temperature-coefficient voltage. Both the positive and negative temperature-coefficients are obtained from the characteristics of the BJT and MOSFET biased in weak-inversion region. As compared with the present existed circuits, all the proposed reference voltage circuits do not use any operational amplifier in the design, and also do not need to perform the second order nonlinear compensation to the negative temperature-coefficient generation circuits, therefore they benefit from simpler circuit structure, smaller chip area and lower power consumption. In addition to the detailed design principle disclosed in this thesis, the proposed circuits have been simulated by HSPICE simulation program with a 0.18μm process parameters. Besides, after the layout of the proposed reference voltage circuits has been finished, all the proposed circuits have been taped-out. The simulation results show that, when the power supply voltage is 1.5V and 2.2V, respectively, the temperature ranges from -20°C to 120°C, the average output voltage of the first proposed circuit is about 734mV, the maximum output voltage variation is 14.39mV, the power dissipation is 0.288mW, the temperature coefficient is about 140ppm/°C. The average output voltage of the second proposed circuit the is about 730mV, the maximum output voltage variation is 30.673mV, the power dissipation is 0.122mW, and the temperature coefficient is about 300ppm/°C. Finally, the average output voltage of the last proposed circuit is about 763mV, the maximum output voltage variation is 29.143mV, the power dissipation is 0.117mW, and the temperature coefficient is about 272.64ppm/°C. The simulation results are consistent with theoretical analysis, it also confirm the validity of the design principles. The proposed CMOS differential output reference voltage circuits are expected to be used in the design of analog integrated circuits and other practical applications.

APA, Harvard, Vancouver, ISO, and other styles

35

Chang, Dern-kan, and 張登堪. "Design of Low-Voltage CMOS Voltage Reference Circuits Based on Sub-threshold Characteristics." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/99526991345794192669.

Full text

Abstract:

碩士
國立中興大學
電機工程學系所
95
The conventional band-gap reference voltage circuits usually require high supply voltage. To comply with the trend of low voltage operations, many people have tried to use the sub-threshold characteristics to generate the reference voltage. However, they may suffer from larger corner variations or larger chip area due to the resistors in the circuits. This thesis introduces two voltage reference circuits to alleviate these problems. The first voltage reference circuit is presented for generating a constant reference voltage of 278mV using sub-threshold characteristics of 0.18um CMOS technology at supply voltages from 0.8V to 2.6V with a total current of 3.6 uA. The threshold voltage variation due to process corner variation is minimized by a threshold voltage tracking technique between the normal and high threshold NMOS transistors. In the mean time, channel-length modulation effect is also compensated. The proposed circuit on the chip area of 0.04mm 2 achieves the total reference voltage variation of 2.5mV for various process corners and temperature variation from -20 degree C to 120 degree C. The second voltage reference without the resistor providing a constant voltage reference of 101mV was realized in 0.18um CMOS technology at supply voltage from 0.9V to 2.6V with a total current of 7.4uA. There are two NMOS transistors used as resistors. The resistance ratio can be compensated to cancel temperature variation effects to achieve a nearly constant voltage reference. For temperatures from -10 degree C to 110 degree C, it has a variation about 2mV with different process corners, in chip area of 0.0122mm 2.

APA, Harvard, Vancouver, ISO, and other styles

36

GAO, QI-ZHANG, and 高啟章. "Curvature-compensated CMOS bandgap voltage reference-systematic analysis and design." Thesis, 1989. http://ndltd.ncl.edu.tw/handle/45027103366796013327.

Full text

APA, Harvard, Vancouver, ISO, and other styles

37

Hsieh, Mark, and 謝禎輝. "Low Voltage Sub-Bangdap Voltage Reference Circuit Design in Deep Sub-Micron CMOS Process Technology." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/46841885088193297013.

Full text

Abstract:

碩士
國立交通大學
電機資訊學院碩士在職專班
94
This thesis proposed a design of 1-V sub-bandgap voltage reference generator circuit. It is suitable for battery-based System-On-Chip applications. The goal of this design is to realize a simple, low cost, low voltage, and low power consumption sub-bandgap voltage reference generator and it can be easy to use for portable equipments. This chip was fabricated using TSMC 90nm CMOS logic process technology provided by Taiwan semiconductor manufacturing company. Whole chip includes a low voltage operational amplifier, current source, and a sub-bandgap core voltage generator circuit. The measured results show that the sub-bandgap voltage reference generator can be operated at 1-V power supply, but the output reference voltage will vary with power supply. To improve the circuit performance, the low voltage operational amplifier, the current mirror and low voltage start up circuit are re-designed, in additional with a DC bias circuit. The simulation result shows the VDDmin can achieve 0.8V with 60ppm/�aC in new circuit. The power dissipation is 44�巰 with 1-V power supply.

APA, Harvard, Vancouver, ISO, and other styles

38

Wang, Suo-Wei, and 王碩瑋. "Analysis And Design Of CMOS Voltage Reference Circuits In Subthreshold Operations For Ultra Low Supply Voltages." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/25225230950184341638.

Full text

Abstract:

碩士
長庚大學
電子工程研究所
95
For a conventional Bandgap voltage reference circuit, the output voltage (Vref) is the BJT base-emitter junction voltage (VBE) plus the thermal voltage VT(KT/q) multiplied by a constant. Therefore, its value is about 1.25V, which limits a low supply voltage operation below 1V. Moreover, low voltage Bandgap voltage reference circuits are limted to the threshold voltages of BJT and MOS (VBE=0.7V,VTH=0.5V by TSMC 0.18um process), therefore they can not work under 0.5V. This thesis proposes a CMOS voltage reference circuit, which can successfully operate with sub-0.5V supply voltage.In the proposed circuit,the major structure is a Widlar current mirror. All transistors are biased in subthreshold region and VGS in subthreshold region decreases with the temperature. By combining positive and negative temperature coefficient voltages and large resistances, the reference voltage independent of the temperature can be obtained. Based on post-layout simulations(VDD=0.5V,Vref=242mV), the variation of the reference voltage is about 1.25mV(57.85ppm) in the temperature range from -40 to 120°C. There are only 5 transistors and 4 resistors in the CMOS voltage reference circuit structure. And the lowest working voltage is 0.45V.

APA, Harvard, Vancouver, ISO, and other styles

39

Caylor, Sam D. "A Standard CMOS Compatible Bandgap Voltage Reference with Post-Process Digitally Tunable Temperature Coefficient." 2007. http://trace.tennessee.edu/utk_gradthes/344.

Full text

Abstract:

An essential element of most robust analog/mixed-signal systems is a stable and precise bandgap voltage reference (BGR). CMOS compatible BGR circuits are generally limited by variability in output drift over temperature due to process variations. In this work a CMOS BGR is developed that provides simple, digitally-controlled post-process (i.e., post fabrication) trimming. The trimming is achieved through MOSFET switches used to adjust a current gain factor for the thermal voltage referenced current within the BGR circuit. This current is proportional to absolute temperature (PTAT). The PTAT current is injected into a series connected resistor and diode to ultimately provide an output voltage. The output voltage's temperature coefficient is correlated to the current gain factor applied to the internally generated PTAT current. Thus, the BGR circuit's temperature coefficient (and therefore drift) is adjusted or tuned using a digital input word to control switch settings and therefore the PTAT current. By providing post-process trimming, chip-to-chip and wafer-to-wafter variations can be minimized through simple digitally controlled tuning. This trimming capability also extends the BGR to broad temperature range applications. A complete CMOS-compatible post-process trimmable BGR implementation is described and measurement results are provided. Design considerations to enhance the circuit's tolerance to radiation induced single-event transients are also addressed.

APA, Harvard, Vancouver, ISO, and other styles

40

Caylor, Sam D. "A standard CMOS compatibles bandgap voltage reference with post-process digitally tunable temperature coefficient." 2008. http://etd.utk.edu/2008/CaylorSam.pdf.

Full text

APA, Harvard, Vancouver, ISO, and other styles

41

Guerra, Duarte Miguel Ribeiro. "Advanced Electrical Characterization of Oxide TFTs Design of a Temperature Compensated Voltage Reference." Master's thesis, 2016. http://hdl.handle.net/10362/20682.

Full text

Abstract:

Any electronic device, regardless of its function, needs a reference voltage source that feeds reliably, i.e., which generates a constant voltage, upstream and regardless of external environmental conditions, such as temperature. Since such a characteristic negatively influences the behavior of the devices, whose base elements are transistors, it is essential to design a circuit that provides a voltage which is invariant over a temperature range. In this work is designed a circuit that is responsible for generating a reference voltage using only thin film transistors or TFTs, on glass substrate. However, in order to validate the concept used in the mentioned transistors, it is also dimensioned and simulated the proposed circuit in 130 nm CMOS technology, where the respective results are expected to be comparative between the two technologies. For CMOS technology, for a nominal reference voltage of 124,0 mV, Cadence simulation reveals ±2,2 ppm/ºC temperature coefficient, between -20 °C and 100 °C. The power consumptions are and 1,434 mW and 4,566 mW for both CMOS and IGZO-TFT technologies, respectively.

APA, Harvard, Vancouver, ISO, and other styles

42

Lai, Yan-Jiun, and 賴彥均. "A 4.2nW and 18ppm/°C Temperature Coefficient Leakage-based Square Root Compensation (LSRC) CMOS Voltage Reference." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/m6k978.

Full text

Abstract:

碩士
國立交通大學
電控工程研究所
107
With rapid development of the application for the Internet of Everything (IoE), many portable products pursue smaller volume and increase more multimedia-functions. Therefore, the battery need to provide more energy to the system. However, the size of battery in portable products is still small cause by the size of portable products. Thus, battery endurance and cooling system can drastically extend battery life and become a new selling point of portable products. Ultra-low-power (ULP) Internet-of-Everything (IoE) become the main research direction of energy management. ULP IoE electronics need to aggressively reduce the power consumption through the use of dynamic voltage scaling (DVS) technique, sleeping mode, idle mode, off mode, etc. ULP IoE electronics require active power down to tens of micro-watts by using some power management techniques. At the same time, ultra-low voltage reference circuits need to be less than a few tens of nano-watts. So ULP voltage reference circuit becomes more important. Although high mobility (µ) and low threshold voltage (Vth) lead to high driving capability in scaling down advanced technologies owing to decreasing doping concentration (NA), the stabilization of voltage reference circuit is critically influenced. Thus, CMOS-based voltage reference suffer from a trade-off between power dissipation and temperature coefficient (TC) due to the limited order of compensation in an advanced process which features a low supplied voltage (1~1.2V).Therefore, this thesis proposes leakage-based square root compensation (LSRC) technique to shape the PTAT curve to reach both low TC and low power simultaneously. On the other hand, the architecture provides an extensible order of compensation which is independent of voltage headroom. The two LSRC branches voltage reference implemented in 40nm CMOS process achieves a within-wafer σ/μ of 0.204 and a TC of 18ppm/°C with a power consumption of 4.2nW.

APA, Harvard, Vancouver, ISO, and other styles

43

Ho, Kuan-Lin, and 何冠霖. "Design of an All-CMOS Low-temperature-drift Voltage Reference with Assisted-one-temperature-point Trim." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/13480674592624333210.

Full text

Abstract:

碩士
國立臺灣大學
電子工程學研究所
103
Voltage reference (VR) is required in integrated circuits for providing a stable voltage, which is ideally immune to temperature, supply and process variations. It undoubtedly plays a crucial role in analog circuit applications. This thesis proposes an all-CMOS voltage reference with assisted-one-temperature -point trim in a 40-nm CMOS technology that is functional from 0.8-V supply. Conventionally, BJT-based references are commonly used, but a BJT consumes at least 0.75V headroom. Thus, they are not suitable for advanced technologies because of supply scaling. Previously solutions include BJT-free designs, but they exhibit worse temperature characteristics, or complex trimming methodology is demanded to achieve a reasonable temperature coefficient (TC). In this work, one-temperature-point trim on bias makes MOS exhibit better temperature characteristics. Thus, an all-MOS circuit topology featuring low temperature drift can be achieved with simple trimming procedures. The chip is fabricated in a TSMC 40-nm CMOS technology. It works down to a supply of 0.8 V and occupies 0.049 mm2. Total 8 samples was measured from -10˚C to 100 ˚C. Measurement results show that the average TC is about 30 ppm/˚C and 3σ spread is only 0.14 %. Also, PSR of -48 dB at a low frequency is attained, and line sensitivity (LS) is below 1.8 %/V.

APA, Harvard, Vancouver, ISO, and other styles

44

QIN, XU-YUAN, and 泰旭沅. "The design of CMOS bandgap voltage reference and capacitor-ratio-independent algorithmic analog-to-digital converter." Thesis, 1989. http://ndltd.ncl.edu.tw/handle/08997420346634447895.

Full text

APA, Harvard, Vancouver, ISO, and other styles

45

Wu, Chien-Cheng, and 吳健誠. "A Pure CMOS Voltage Reference Circuit with Temperature Drift Calibration and an Improved Capacitor-Free Low Dropout Regulator." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/72194768076763555209.

Full text

Abstract:

碩士
國立中興大學
電機工程學系所
98
In recent years, integrated circuit technology becomes more sophisticated, so more and more portable electronic products appear in our daily lives. The portable products require small sizes, nice looking, and multi-functions. Therefore, integrated circuits tend to very low power consumption. In applications of the reference voltage circuits, many circuits such as: D/A, A/D converters, voltage regulators, etc., require a reference voltage circuit to provide the accurate reference voltage effectively. In this paper, we propose a low-voltage, low-power pure CMOS voltage reference circuit on very small area with temperature drift calibration. This circuit was fabricated on area of 0.0076mm2 using TSMC 0.18μm CMOS process. The measurement results reveal that the power consumption is 74nW, with temperature coefficient of 6.7ppm/oC after calibration. The conventional LDO voltage regulators require a large external capacitor (a few μF) in order to maintain stability due to negative feedback. However, in the integrated circuits, even the nF capacitor occupies very large chip area, which is not cost effective. Another goal in this thesis is to design a linear regulator without external capacitors (cap-free LDO). The LDO utilizes a three-stage amplifier with nested Miller compensation. The circuit may be equivalent to a single pole circuit for stability. The proposed circuit was designed using TSMC 0.35μm CMOS process for the maximum load current of 150mA. The simulation results show that input voltages are 2.8V ~ 5V and 3.3V ~ 5V for the output voltage of 2.5V and 3.3V, respectively. The dropout voltage is 300mV, and the quiescent current is 96μA. For the worst case without external capacitors, the undershoot voltage is 220mV and the overshoot voltage is 206mV.

APA, Harvard, Vancouver, ISO, and other styles

46

Lin, Shin-Ta, and 林信太. "The Design and Implementation of an Ultra Low Power and Small Area CMOS Voltage Reference Based on MOSFET Operated in Weak Inversion Region." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/8492jn.

Full text

Abstract:

碩士
國立交通大學
電信工程系所
96
This thesis uses standard CMOS 0.18μm process technique to design and realize a stable voltage reference which does not change with temperature. In the recent years, battery-operated systems are used extensively. Along with this tendency, we demand low-power, small-area, and high performance when designing circuits. Many analog circuits need a stable voltage reference, so the thesis shows a low-power and small-area voltage reference to apply in battery-operated systems. Proposed circuits work in weak inverse region to replace the bipolar devices in conventional circuit and using proposed circuits realize CMOS voltage reference which does not change with temperature. Its power consumption only has several hundred nano-Watt and its area is only several hundred squre nanometer. In addition, the voltage derivation only has several dozens milli-Volt when temperature range is from -80℃ to 165℃. Therefore, proposed architectures can supply a stable voltage reference in battery-operated systems.

APA, Harvard, Vancouver, ISO, and other styles

47

Wang, Ru-Jie, and 王銣傑. "CMOS Voltage References without Resistors." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/77139533456387300631.

Full text

Abstract:

碩士
輔仁大學
電子工程學系
95
This work presents two CMOS voltage references without resistors. The first one is a curvature-compensated bandgap reference without resistors in 0.18-μm CMOS technology. The circuit uses a new current generator circuit for higher order temperature terms curvature compensation and a PMOS voltage divider for scaling down the reference voltage. A 605.6mV output voltage is generated with a temperature coefficient of 1 ppm/°C from –40 to 125 °C. It dissipates 77μW at a supply voltage of 1.8-V. The second one is a low-voltage low-power bandgap voltage reference without using passive components. A reference voltage of 646.4 mV is generated with a temperature coefficient of 1.7 ppm/°C in the range [−40, +125] °C at 1.8-V supply voltage. A line sensitivity of 0.18 mV/V in the supply voltage range [+1, +1.8] V are achieved. It dissipates a maximum power of 4.9 μW at a 1.8-V supply voltage and 125 °C. The silicon area is as small as 100 × 50 μm2 in 0.18um CMOS process.

APA, Harvard, Vancouver, ISO, and other styles

48

Hsu, Heng, and 徐. 珩. "Design of Low Temperature-Coefficient CMOS Reference Voltages." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/p35be8.

Full text

Abstract:

碩士
國立虎尾科技大學
電子工程系碩士班
104
In this thesis, two low temperature-coefficient CMOS reference voltage circuits have been proposed. The design principle is based on using the characteristics of the forward-biased pn junction of the BJT transistor to generate the necessary positive and negative temperature-coefficients. Appropriately combine the positive and negative temperature-coefficients, a zero temperature coefficient reference voltage circuit can be realized. Besides, second order temperature-coefficient compensation has been performed to further reduce the variation of the output voltages. As compared with the existed reference voltage circuits, the proposed circuit benefits from low-power consumption, simpler circuit architecture, and less chip area. In this thesis, detailed design principle has been disclosed, also the HSPICE and LAKER simulation program with 0.35-m process parameters have been used to perform the pre-layout and post-layout simulations. According to the post-layout simulation results, under the supply voltage of 2.4V, as the temperature varies from -20oC to 120oC, the output voltage variations of the proposed second order single-ended reference voltage is 0.052mV, the corresponding power dissipation is only 0.457mW and the variation per temperature is 3.04 ppm/˚C. The simulation results of the proposed second order differential mode reference voltage circuit shows that, under the supply voltage of 2.4V, the temperature varies from -20oC to 120oC, the output voltage changes 8.603mV, the power dissipation is only 0.897mW and the variation per temperature is 132.31ppm/˚C. Both the simulation results are consistent with the theoretic analysis. The proposed circuit can be applied to different analog circuits.

APA, Harvard, Vancouver, ISO, and other styles

Dissertations / Theses on the topic 'CMOS Voltage Reference'

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles