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Journal articles on the topic 'CMOS Voltage Reference'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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1

Dai, Y., D. T. Comer, D. J. Comer, and C. S. Petrie. "Threshold voltage based CMOS voltage reference." IEE Proceedings - Circuits, Devices and Systems 151, no. 1 (2004): 58. http://dx.doi.org/10.1049/ip-cds:20040217.

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2

Kim, Jae-Bung, and Seong-Ik Cho. "Modified Low-Votlage CMOS Bandgap Voltage Reference with CTAT Compensation." Transactions of The Korean Institute of Electrical Engineers 61, no. 5 (May 1, 2012): 753–56. http://dx.doi.org/10.5370/kiee.2012.61.5.753.

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3

Li, Lin An, Ming Tang, Wen Ou, and Yang Hong. "An All CMOS Current Reference." Applied Mechanics and Materials 135-136 (October 2011): 192–97. http://dx.doi.org/10.4028/www.scientific.net/amm.135-136.192.

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In this paper, an all CMOS current reference circuit which generates a reference current independent of PVT (Process, supply Voltage, and Temperature) variations is presented. The circuit consists of a self-biased current source (SBCS) and two nested connected transistors which supply a voltage with positive temperature coefficient and the resulting reference circuit has low temperature coefficient. It is based on CSMC 0.5um mixed-signal process with the supply voltage of 5V. The precision of reference current is about ±3.05% when considering the process, supply voltage and temperature variation at the same time.

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4

Olivera, Fabian, and Antonio Petraglia. "Adjustable Output CMOS Voltage Reference Design." IEEE Transactions on Circuits and Systems II: Express Briefs 67, no. 10 (October 2020): 1690–94. http://dx.doi.org/10.1109/tcsii.2019.2943303.

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5

Gu, Y. B., S. F. Yueh, T. W. Chang, and K. C. Huang. "CMOS voltage reference with multiple outputs." IET Circuits, Devices & Systems 2, no. 2 (2008): 222. http://dx.doi.org/10.1049/iet-cds:20070211.

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6

Lo, Tien-Yu, Chung-Chih Hung, and Mohammed Ismail. "CMOS voltage reference based on threshold voltage and thermal voltage." Analog Integrated Circuits and Signal Processing 62, no. 1 (June 11, 2009): 9–15. http://dx.doi.org/10.1007/s10470-009-9321-y.

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7

Wang, San-Fu. "A 5 V-to-3.3 V CMOS Linear Regulator with Three-Output Temperature-Independent Reference Voltages." Journal of Sensors 2016 (2016): 1–7. http://dx.doi.org/10.1155/2016/1436371.

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This paper presents a 5 V-to-3.3 V linear regulator circuit, which uses 3.3 V CMOS transistors to replace the 5 V CMOS transistors. Thus, the complexity of the manufacturing semiconductor process can be improved. The proposed linear regulator is implemented by cascode architecture, which requires three different reference voltages as the bias voltages of its circuit. Thus, the three-output temperature-independent reference voltage circuit is proposed, which provides three accurate reference voltages simultaneously. The three-output temperature-independent reference voltages also can be used in other circuits of the chip. By using the proposed temperature-independent reference voltages, the proposed linear regulator can provide an accurate output voltage, and it is suitable for low cost, small size, and highly integrated system-on-chip (SoC) applications. Moreover, the proposed linear regulator uses the cascode technique, which improves both the gain performance and the isolation performance. Therefore, the proposed linear regulator has a good performance in reference voltage to output voltage isolation. The voltage variation of the linear regulator is less than 2.153% in the temperature range of −40°C–120°C, and the power supply rejection ratio (PSRR) is less than −42.8 dB at 60 Hz. The regulator can support 0~200 mA output current. The core area is less than 0.16 mm2.

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8

Ria, Andrea, Alessandro Catania, Paolo Bruschi, and Massimo Piotto. "A Low-Power CMOS Bandgap Voltage Reference for Supply Voltages Down to 0.5 V." Electronics 10, no. 16 (August 8, 2021): 1901. http://dx.doi.org/10.3390/electronics10161901.

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A voltage reference is strictly required for sensor interfaces that need to perform nonratiometric data acquisition. In this work, a voltage reference capable of working with supply voltages down to 0.5 V is presented. The voltage reference was based on a classic CMOS bandgap core, properly modified to be compatible with low-threshold or zero-threshold MOSFETs. The advantages of the proposed circuit are illustrated with theoretical analysis and supported by numerical simulations. The core was combined with a recently proposed switched capacitor, inverter-like integrator implementing offset cancellation and low-frequency noise reduction techniques. Experimental results performed on a prototype designed and fabricated using a commercial 0.18 μm CMOS process are presented. The prototype produces a reference voltage of 220 mV with a temperature sensitivity of 45 ppm/°C across a 10–50 °C temperature range. The proposed voltage reference can be used to source currents up to 100 μA with a quiescent current consumption of only 630 nA.

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9

Zhou, Qian Neng, Yun Song Li, Jin Zhao Lin, Hong Juan Li, Chen Li, Yu Pang, Guo Quan Li, Xue Mei Cai, and Qi Li. "A High-Order CMOS Bandgap Voltage Reference." Advanced Materials Research 989-994 (July 2014): 1165–68. http://dx.doi.org/10.4028/www.scientific.net/amr.989-994.1165.

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A high-order bandgap voltage reference (BGR) is designed by adopting a current which is proportional to absolute temperature T1.5. The high-order BGR is analyzed and simulated in SMIC 0.18μm CMOS process. Simulation results show that the designed high-order BGR achieves temperature coefficient of 2.54ppm/°C when temperature ranging from-55°C to 125°C. The high-order BGR at 10Hz, 100Hz, 1kHz, 10kHz and 100kHz achieves, respectively, the power supply rejection ratio of-64.01dB, -64.01dB, -64dB, -63.5dB and-53.2dB. When power supply voltage changes from 1.7V to 2.5V, the output voltage deviation of BGR is only 617.6μV.

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10

Park, Minseon, and Sung Min Park. "A CMOS symmetric self-biased voltage reference." Microelectronics Journal 80 (October 2018): 28–33. http://dx.doi.org/10.1016/j.mejo.2018.08.002.

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11

Xinquan, Lai, Xu Ziyou, Li Yanming, Ye Qiang, and Man Maoli. "A CMOS piecewise curvature-compensated voltage reference." Microelectronics Journal 40, no. 1 (January 2009): 39–45. http://dx.doi.org/10.1016/j.mejo.2008.09.006.

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12

Mitrea, O., C. Popa, A. M. Manolescu, and M. Glesner. "A curvature-corrected CMOS bandgap reference." Advances in Radio Science 1 (May 5, 2005): 181–84. http://dx.doi.org/10.5194/ars-1-181-2003.

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Abstract. This paper presents a CMOS bandgap reference that employs a curvature correction technique for compensating the nonlinear voltage temperature dependence of a diode connected BJT. The proposed circuit cancels the first and the second order terms in the VBE(T ) expansion by using the current of an autopolarizedWidlar source and a small correction current generated by a MOSFET biased in weak inversion. The voltage reference has been fabricated in a 0.35µm 3Metal/2Poly CMOS technology and the chip area is approximately 70µm × 110µm. The measured temperature coefficient is about 10.5 ppm/K over a temperature range of 10– 90°C while the power consumption is less than 1.4mW.

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13

MATSUDA, T. "A Temperature and Supply Voltage Independent CMOS Voltage Reference Circuit." IEICE Transactions on Electronics E88-C, no. 5 (May 1, 2005): 1087–93. http://dx.doi.org/10.1093/ietele/e88-c.5.1087.

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14

ZHU, ZHANGMING, WEI WEI, LIANXI LIU, and YINTANG YANG. "A HIGH PRECISION CMOS VOLTAGE REFERENCE WITHOUT RESISTORS." Journal of Circuits, Systems and Computers 21, no. 03 (May 2012): 1250019. http://dx.doi.org/10.1142/s0218126612500193.

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With the application of the voltage divider to the traditional bandgap reference without resistors, a high precision CMOS voltage reference without resistors has been proposed. The temperature coefficient has improved because the divider introduces the temperature compensation. The output reference voltage is 410.39 mV at the room temperature. The temperature coefficient of the voltage reference is 3.02 ppm/°C in the range from -20°C to 120°C. Moreover, the power supply rejection ratio of the voltage reference is -52.6 dB and the power consumption is 5.61 μW.

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15

Singhal, Sonal, Rohit Singh, and Amit Kumar Singh. "Design of a Sub-0.4 V Reference Circuit in 0.18μm CMOS Technology." Advanced Materials Research 816-817 (September 2013): 882–86. http://dx.doi.org/10.4028/www.scientific.net/amr.816-817.882.

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This paper proposes a low power voltage reference generator in 0.18μm CMOS technology.The circuit presented here includes MOSFETs in sub threshold mode and uses the temperature dependence of threshold voltages and sub-threshold current of MOSFET to form a temperature-insensitive reference. An input supply voltage of 1.8 Volt is used for the circuit generating a total current of 1.33μA. By varying the device temperature over the range of-20°C to 100°C corresponding variation over the output voltage was found to lie in the range 397.8 to 400.2 mV. Thus a 0.6% variation in voltage over the considered range of temperature is obtained.

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16

Cunha, Ana Isabela Araújo, Antonio José Sobrinho De Sousa, Edson Pinto Santana, Robson Nunes De Lima, Fabian Souza De Andrade, Matheus Artur Macedo Bomfim, Hildeloi Cunha Dos Santos, and Alípio Souza Silva. "Compact CMOS Analog Multiplier Free of Voltage Reference Generators." Journal of Integrated Circuits and Systems 15, no. 3 (December 3, 2020): 1–12. http://dx.doi.org/10.29292/jics.v15i3.139.

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This work presents a CMOS four quadrant analog multiplier architecture for application as the synapse element in analog cellular neural networks. For this reason, the circuit has voltage-mode inputs and a current-mode output and the chief design targets are compactness and low energy consumption. A signal application method is proposed that avoids voltage reference generators, which contributes to reduce sensitivity to supply voltage variation. Performance analysis through simulation has been accomplished for a design in CMOS 130 nm technology with 163 µm2 total active area. The circuit features ±50 mV input voltage range, 86 µW static power and ‑28.4 dB maximum total harmonic distortion. A simple technique for manual calibration is also presented.

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17

Olmos, Alfredo, Fabricio Ferreira, Fernando Paixão Cortes, Fernando Chavez, and Marcelo Soares Lubaszewski. "A 2-Transistor Sub-1V Low Power Temperature Compensated CMOS Voltage Reference: Design and Application." Journal of Integrated Circuits and Systems 10, no. 2 (December 28, 2015): 74–80. http://dx.doi.org/10.29292/jics.v10i2.408.

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This paper presents the design and application of a CMOS sub-1V voltage reference using a 2-transistor Self-Cascode MOSFET (SCM) structure able to get low power consumption, temperature compensation, and small area. An efficient design procedure applied to this simple topology relying on NMOS transistors with different threshold voltages allows attaining large immunity against bias current and supply voltage variations. The two transistors can operate in weak, moderate, or strong inversion making the design flexible in terms of area and power consumption. Implemented in a > 0.18mm standard CMOS technology, the circuit provides a 400mV voltage reference with a variation of ±0.18% from -20°C to 75°C (or less than 15ppm/°C), operates from 3.6V down to 800mV while biased with a 5nA resistor-less PTAT current source that varies ±30% over PVT, and consumes less than 20nA with an area of 0.01mm2. The same concept was used to create a temperature compensated voltage drop with regard to a monitored power supply voltage but using a 2-PMOS SCM structure with transistors of different threshold voltages. These two circuits were adopted as part of a Power Management (PM) system for RFID tag applications. The PM includes a LDO voltage regulator and a low voltage detector that require both the voltage reference and the low voltage monitor. The LDO regulated output voltage and the trip-point of the voltage detector vary +/-5.5% and +/-3.3%, respectively, over temperature, without trimming.

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18

Guang, Yang, Bin Yu, and Huang Hai. "Design of a High Performance CMOS Bandgap Voltage Reference." Advanced Materials Research 981 (July 2014): 90–93. http://dx.doi.org/10.4028/www.scientific.net/amr.981.90.

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Bandgap voltage reference, to provide a temperature and power supply insensitive output voltage, is a very important module in the analog integrated circuits and mixed-signal integrated circuits. In this paper, a high performance CMOS bandgap with low-power consumption has been designed. It can get the PTAT (Proportional to absolute temperature) current, and then get the reference voltage. Based on 0.35μm CMOS process, using HSPICE 2008 software for circuit simulation, the results showed that , when the temperature changes from -40 to 80 °C, the proposed circuit’s reference voltage achieve to 1.2V, temperature coefficient is 3.09ppm/°C. Adopt a series of measures, like ESD protection circuit, in layout design. The ultimately design through the DRC and LVS verification, and the final layout size is 700μm * 560μm.

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19

Sahafi, A., J. Sobhi, and Z. D. Koozekanani. "Pico Watt sub-threshold CMOS voltage reference circuit." IEICE Electronics Express 10, no. 4 (2013): 20120945. http://dx.doi.org/10.1587/elex.10.20120945.

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20

Zawawi, Ruhaifi Abdullah, and Othman Sidek. "A new curvature-corrected CMOS bandgap voltage reference." IEICE Electronics Express 9, no. 4 (2012): 240–44. http://dx.doi.org/10.1587/elex.9.240.

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21

Becker-Gomez, A., T. Lakshmi Viswanathan, and T. R. Viswanathan. "A Low-Supply-Voltage CMOS Sub-Bandgap Reference." IEEE Transactions on Circuits and Systems II: Express Briefs 55, no. 7 (July 2008): 609–13. http://dx.doi.org/10.1109/tcsii.2008.921580.

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22

Siqueira Dias, José A., Welligton A. do Amaral, and Wilmar B. de Moraes. "A curvature-compensated CMOS voltage reference using characteristics." Microelectronics Journal 40, no. 12 (December 2009): 1772–78. http://dx.doi.org/10.1016/j.mejo.2009.10.001.

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23

Albano, Domenico, Felice Crupi, Francesca Cucchi, and Giuseppe Iannaccone. "A picopower temperature-compensated, subthreshold CMOS voltage reference." International Journal of Circuit Theory and Applications 42, no. 12 (June 10, 2013): 1306–18. http://dx.doi.org/10.1002/cta.1925.

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24

Tsitouras, A., F. Plessas, M. Birbas, J. Kikidis, and G. Kalivas. "A sub-1V supply CMOS voltage reference generator." International Journal of Circuit Theory and Applications 40, no. 8 (February 23, 2011): 745–58. http://dx.doi.org/10.1002/cta.753.

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25

Park, Chang-Bum, and Shin-Il Lim. "A Sub-1V Nanopower CMOS Only Bandgap Voltage Reference." Journal of IKEEE 20, no. 2 (June 30, 2016): 192–95. http://dx.doi.org/10.7471/ikeee.2016.20.2.192.

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26

Colombo, Dalton, Christian Fayomi, Frederic Nabki, Luiz F. Ferreira, Gilson Wirth, and Sergio Bampi. "A Design Methodology Using the Inversion Coefficient for Low-Voltage Low-Power CMOS Voltage References." Journal of Integrated Circuits and Systems 6, no. 1 (December 27, 2011): 7–17. http://dx.doi.org/10.29292/jics.v6i1.333.

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This paper presents an analog design methodology, which uses the selection of the inversion coefficient of MOS devices, to design low-voltage and low-power (LVLP) CMOS voltage references. The motivation of this work comes from the demand for analog design methods that optimize the sizing process of transistors working in subthreshold operation. The advantage of the presented method – compared to the traditional approaches for circuit design – is the reduction of design cycle time and the minimization of simulation iterations when the proposed equations are used. As a case study, a LVLP voltage reference based on subthreshold MOSFETs with a supply voltage of 0.7 V was designed in a 0.18-μm CMOS technology.

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27

FERREIRA, L. H. C., T. C. PIMENTA, and R. L. MORENO. "An Ultra Low-Voltage Ultra Low-Power CMOS Threshold Voltage Reference." IEICE Transactions on Electronics E90-C, no. 10 (October 1, 2007): 2044–50. http://dx.doi.org/10.1093/ietele/e90-c.10.2044.

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28

Ferreira, Luis H. C., Tales C. Pimenta, and Robson L. Moreno. "A CMOS threshold voltage reference source for very-low-voltage applications." Microelectronics Journal 39, no. 12 (December 2008): 1867–73. http://dx.doi.org/10.1016/j.mejo.2008.02.001.

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29

Khong-Meng Tham and K. Nagaraj. "A low supply voltage high PSRR voltage reference in CMOS process." IEEE Journal of Solid-State Circuits 30, no. 5 (May 1995): 586–90. http://dx.doi.org/10.1109/4.384173.

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30

Zhou, Qian Neng, Rong Xue, Hong Juan Li, Jin Zhao Lin, Yun Song Li, Yu Pang, Qi Li, Guo Quan Li, and Lu Deng. "A Sub-1V High Precision CMOS Bandgap Reference." Applied Mechanics and Materials 427-429 (September 2013): 1097–100. http://dx.doi.org/10.4028/www.scientific.net/amm.427-429.1097.

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In this paper, a low temperature coefficient bandgap voltage (BGR) is designed for A/D converter by adopting piecewise-linear compensation technique. The designed BGR is analyzed and simulated in SMIC 0.18μm CMOS process. Simulation results show that the PSRR of the designed BGR achieves-72.51dB, -72.49dB, and-70.58dB at 10Hz, 100Hz and 1kHz respectively. The designed BGR achieve the temperature coefficient of 1.57 ppm/°C when temperature is in the range from-35°C to 125°C. When power supply voltage VDD changes from 1V to 7V, the deviation of the designed BGR output voltage VREF is only 4.465μV.

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31

Lee, Geun-Ho. "Dual-mode CMOS Current Reference for Low-Voltage Low-Power." Journal of the Korean Institute of Information and Communication Engineering 14, no. 4 (April 30, 2010): 917–22. http://dx.doi.org/10.6109/jkiice.2010.14.4.917.

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32

Barteselli, Edoardo, Luca Sant, Richard Gaggl, and Andrea Baschirotto. "Design Techniques for Low-Power and Low-Voltage Bandgaps." Electricity 2, no. 3 (July 26, 2021): 271–84. http://dx.doi.org/10.3390/electricity2030016.

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Reverse bandgaps generate PVT-independent reference voltages by means of the sums of pairs of currents over individual matched resistors: one (CTAT) current is proportional to VEB; the other one (PTAT) is proportional to VT (Thermal voltage). Design guidelines and techniques for a CMOS low-power reverse bandgap reference are presented and discussed in this paper. The paper explains firstly how to design the components of the bandgap branches to minimize circuit current. Secondly, error amplifier topologies are studied in order to reveal the best one, depending on the operation conditions. Finally, a low-voltage bandgap in 65 nm CMOS with 5 ppm/°C, with a DC PSR of −91 dB, with power consumption of 5.2 μW and with an area of 0.0352 mm2 developed with these techniques is presented.

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33

Ragheb, A., and Hyung Kim. "Reference-Free Dynamic Voltage Scaler Based on Swapping Switched-Capacitors." Energies 12, no. 4 (February 15, 2019): 625. http://dx.doi.org/10.3390/en12040625.

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This paper introduces a reference-free, scalable, and energy-efficient dynamic voltage scaler (DVS) that can be reconfigured for multiple outputs. The proposed DVS employs a novel swapping switched-capacitor (SSC) technique, which can generate target output voltages with higher resolution and smaller ripple voltages than the conventional voltage scalers based on switched-capacitors. The proposed DVS consists of a cascaded 2:1 converter based on swapping capacitors, which is essential to achieve both very small voltage ripple and fine-grain conversion ratios. One of the serious drawbacks of the conventional voltage scalers is the need for external reference voltages to maintain the target output voltage. The proposed SSC; however, eliminates the needs for any reference voltages. This significant benefit is achieved by the self-charging ability of the SSC, which can recharge all its capacitors to the configured voltage by simply swapping the two capacitors in each stage. The proposed SSC-DVS was designed with a resolution of 16 output levels and implemented using a 130 nm CMOS (Complementary Metal Oxide semiconductor) process. We conducted measured results and post-layout simulations with an input voltage of 1.5 V to produce an output voltage range of 0.085–1.4 V, which demonstrated a power efficiency of 85% for a load current of 550 µA with a voltage ripple of as low as 2.656 mV for a 2 KΩ resistor load.

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34

Ytterdal, T. "CMOS bandgap voltage reference circuit for supply voltages down to 0.6 V." Electronics Letters 39, no. 20 (2003): 1427. http://dx.doi.org/10.1049/el:20030937.

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35

Xu, Chen, Xiang Ning Fan, Zai Jun Hua, and Zhou Yu. "Design of a CMOS Voltage-Controlled Ring Oscillator with Bandgap Voltage Reference." Applied Mechanics and Materials 618 (August 2014): 558–62. http://dx.doi.org/10.4028/www.scientific.net/amm.618.558.

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Voltage controlled oscillator has been used in every field of the electronics industry, and plays an indispensable role. In the fractional divider, in order to reduce the product size, voltage controlled ring oscillator is used to meet the design requirements, at the same time as much as possible to reduce the area. The design of wide tuning voltage-controlled ring oscillator was designed with the reference voltage source. This design not only could reduce the error brought by the external voltage reference, and was also very good realization structure innovation in the film. This design used 0.5 μ m CMOS Hua technology. The post simulation results show: when the coarse voltage and fine voltage are respectively 1V and 2V, voltage waveform oscillator output swing is 2.4V; when the coarse voltage and fine voltage are respectively 1.13V and 2V, voltage waveform oscillator output swing is 2.8V; when the coarse voltage and fine voltage are respectively 1.3V and 2V, voltage waveform oscillator output swing is 3V. After simulations, the frequency range of the voltage-controlled ring oscillator adjustment is 100 ~ 200MHz.

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36

IKEDA, H. "CMOS Zero-Temperature-Coefficient Point Voltage Reference with Variable-Output-Voltage Level." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E88-A, no. 2 (February 1, 2005): 476–82. http://dx.doi.org/10.1093/ietfec/e88-a.2.476.

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37

Wang, Honglai, Xiaoxing Zhang, Yujie Dai, and Yingjie Lü. "A low-voltage low-power CMOS voltage reference based on subthreshold MOSFETs." Journal of Semiconductors 32, no. 8 (August 2011): 085009. http://dx.doi.org/10.1088/1674-4926/32/8/085009.

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38

Saponara, Sergio. "Integrated Bandgap Voltage Reference for High Voltage Vehicle Applications." Journal of Circuits, Systems and Computers 24, no. 08 (August 12, 2015): 1550125. http://dx.doi.org/10.1142/s021812661550125x.

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This work presents a bandgap voltage reference (BGR) integrated in 0.25-μm bipolar-CMOS-DMOS (BCD) technology. The BGR circuit generates a reference voltage of 1.22 V. It is able to withstand large supply voltage variations of vehicle applications from 4.5 V, e.g., in case of cranking, up to 60-V, maximum value in case of emerging 48-V battery systems for hybrid and electrical vehicles. The circuit has an embedded high-voltage (HV) pseudo-regulator block that provides a more stable internal supply rail for a cascaded low-voltage bandgap core. HV MOS are used only in the pre-regulator block thus allowing the design of a BGR with compact size. The proposed architecture permits to withstand large input voltage variations with a temperature drift of a hundred of ppm/°C, a line regulation (LR) of few mV/V versus the external supply voltage and a power supply rejection ratio (PSRR) higher than 90 dB.

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39

Tsitouras, Athanasios, and Paul P. Sotiriadis. "Design of a sub-1V CMOS reference voltage generator." Microelectronics Journal 91 (September 2019): 92–99. http://dx.doi.org/10.1016/j.mejo.2019.05.023.

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40

Parisi, Alessandro, Alessandro Finocchiaro, Giuseppe Papotto, and Giuseppe Palmisano. "Nano-Power CMOS Voltage Reference for RF-Powered Systems." IEEE Transactions on Circuits and Systems II: Express Briefs 65, no. 10 (October 2018): 1425–29. http://dx.doi.org/10.1109/tcsii.2018.2857626.

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41

Zhou, Ze-Kun, Yue Shi, Yao Wang, Nie Li, Zhiping Xiao, Yunkun Wang, Xiaolin Liu, Zhuo Wang, and Bo Zhang. "A Resistorless High-Precision Compensated CMOS Bandgap Voltage Reference." IEEE Transactions on Circuits and Systems I: Regular Papers 66, no. 1 (January 2019): 428–37. http://dx.doi.org/10.1109/tcsi.2018.2857821.

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42

Chahardori, Mohammad, Mojtaba Atarodi, and Mohammad Sharifkhani. "A sub 1V high PSRR CMOS bandgap voltage reference." Microelectronics Journal 42, no. 9 (September 2011): 1057–65. http://dx.doi.org/10.1016/j.mejo.2011.06.010.

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43

Ferro, M., F. Salerno, and R. Castello. "A floating CMOS bandgap voltage reference for differential applications." IEEE Journal of Solid-State Circuits 24, no. 3 (June 1989): 690–97. http://dx.doi.org/10.1109/4.32027.

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44

Yang, Yuanyuan, Kushal Das, Alireza Moini, and David J. Reilly. "A Cryo-CMOS Voltage Reference in 28-nm FDSOI." IEEE Solid-State Circuits Letters 3 (2020): 186–89. http://dx.doi.org/10.1109/lssc.2020.3010234.

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45

Liu, Fan, Feng Yang, Han Wang, Xun Xiang, Xichuan Zhou, Shengdong Hu, Zhi Lin, Amine Bermak, and Fang Tang. "Radiation-Hardened CMOS Negative Voltage Reference for Aerospace Application." IEEE Transactions on Nuclear Science 64, no. 9 (September 2017): 2505–10. http://dx.doi.org/10.1109/tns.2017.2733738.

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46

Lin, Jie, Lidan Wang, Yan Lu, and Chenchang Zhan. "A Nano-Watt Dual-Output Subthreshold CMOS Voltage Reference." IEEE Open Journal of Circuits and Systems 1 (2020): 100–106. http://dx.doi.org/10.1109/ojcas.2020.3005546.

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47

Shi, Jian Ying, Hui Ya Li, and Yan Bin Xu. "A New No Op Amp Full CMOS Voltage Reference Circuit." Applied Mechanics and Materials 519-520 (February 2014): 1067–70. http://dx.doi.org/10.4028/www.scientific.net/amm.519-520.1067.

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Abstract:

A no op amp structure full CMOS reference voltage circuit is designed. The two currents which are proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) are added together to get the reference output voltage which is obtained through a resistance. The characteristics of the new circuit are simulated using 0.5 μm BSIM3V3 spice models in HSPICE. The simulation results show that the output voltage of the circuit is 997mV, the power consumption is 1.12mW, the temperature coefficient is 15.2 ppm/°C in the range from-30°C to 100°C at the supply voltage of 2V.

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Sun, Ye Chao, Zhuo Lei Huang, and Wei Bing Wang. "A Bandgap Reference without Passive Components Based on Standard CMOS." Applied Mechanics and Materials 475-476 (December 2013): 1679–84. http://dx.doi.org/10.4028/www.scientific.net/amm.475-476.1679.

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A bandgap reference without passive components based on standard CMOS is proposed. Using an improved inverse-function technique without any curvature-compensated techniques, two reference voltages are got in different temperature ranges. One is 1.56V with a temperature coefficient of 9.2ppm/°C in the range [0, 14 °C at 3.3V supply voltage, and the other is 1.546V with 47ppm/°C in [-25, 15 °C at 3.3V. Its PSRR (power supply rejection ratio) is below-60dB at 10kHz, and it is quite suitable for integration in processing circuits of MEMS (micro-electro-mechanical systems) devices.

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Nagulapalli, R., K. Hayatleh, S. Barker, A. A. Tammam, P. Georgiou, and F. J. Lidgey. "A 0.55 V Bandgap Reference with a 59 ppm/°C Temperature Coefficient." Journal of Circuits, Systems and Computers 28, no. 07 (June 27, 2019): 1950120. http://dx.doi.org/10.1142/s0218126619501202.

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Abstract:

This paper presents a novel low power, low voltage CMOS bandgap reference (BGR) that overcomes the problems with the existing BJT-based reference circuits by using a MOS transistor operating in sub-threshold region. A proportional to absolute temperature (PTAT) voltage is generated by exploiting the self-bias cascode branch, while a Complementary to Absolute Temperature (CTAT) voltage is generated by using the threshold voltage of the transistor. The proposed circuit is implemented in 65[Formula: see text]nm CMOS technology. Post-layout simulation results show that the proposed circuit works with a supply voltage of 0.55[Formula: see text]V, and generates a 286[Formula: see text]mV reference voltage with a temperature coefficient of 59[Formula: see text]ppm/∘C. The circuit takes 413[Formula: see text]nA current from 0.55[Formula: see text]V supply and occupies 0.00986[Formula: see text]mm2 of active area.

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Kim, Kwang-Hyun, Gyu-Seong Cho, and Young-Hee Kim. "A CMOS Bandgap Reference Voltage Generator for a CMOS Active Pixel Sensor Imager." Transactions on Electrical and Electronic Materials 5, no. 2 (April 1, 2004): 71–75. http://dx.doi.org/10.4313/teem.2004.5.2.071.

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