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Relevant bibliographies by topics / Coarse grained architecture

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Academic literature on the topic 'Coarse grained architecture'

Author: Grafiati

Published: 4 June 2021

Last updated: 4 February 2022

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Journal articles on the topic "Coarse grained architecture"

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Xu, Jinwei, Jingfei Jiang, Yong Dou, Xiaolong Shen, and Zhiqiang Liu. "Coarse-Grained Architecture for Fingerprint Matching." ACM Transactions on Reconfigurable Technology and Systems 9, no. 2 (February 3, 2016): 1–15. http://dx.doi.org/10.1145/2791296.

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Lopes, João D., Mário P. Véstias, Rui Policarpo Duarte , Horácio C. Neto, and José T. de Sousa. "Coarse-Grained Reconfigurable Computing with the Versat Architecture." Electronics 10, no. 6 (March 12, 2021): 669. http://dx.doi.org/10.3390/electronics10060669.

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Reconfigurable computing architectures allow the adaptation of the underlying datapath to the algorithm. The granularity of the datapath elements and data width determines the granularity of the architecture and its programming flexibility. Coarse-grained architectures have shown the right balance between programmability and performance. This paper provides an overview of coarse-grained reconfigurable architectures and describes Versat, a Coarse-Grained Reconfigurable Array (CGRA) with self-generated partial reconfiguration, presented as a case study for better understanding these architectures. Unlike most of the existing approaches, which mainly use pre-compiled configurations, a Versat program can generate and apply myriads of on-the-fly configurations. Partial reconfiguration plays a central role in this approach, as it speeds up the generation of incrementally different configurations. The reconfigurable array has a complete graph topology, which yields unprecedented programmability, including assembly programming. Besides being useful for optimising programs, assembly programming is invaluable for working around post-silicon hardware, software, or compiler issues. Results on core area, frequency, power, and performance running different codes are presented and compared to other implementations.

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Paek, Jong Kyung, Kiyoung Choi, and Jongeun Lee. "Binary acceleration using coarse-grained reconfigurable architecture." ACM SIGARCH Computer Architecture News 38, no. 4 (September 14, 2010): 33–39. http://dx.doi.org/10.1145/1926367.1926374.

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Dube, Rohit. "Scalable hierarchical coarse-grained timers." ACM SIGOPS Operating Systems Review 34, no. 1 (January 2000): 11–20. http://dx.doi.org/10.1145/506128.506130.

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Boxer, Laurence. "Coarse Grained Parallel Selection." Parallel Processing Letters 31, no. 01 (February 24, 2021): 2150003. http://dx.doi.org/10.1142/s0129626421500031.

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Several efficient, but non-optimal, solutions to the Selection Problem on coarse grained parallel computers have appeared in the literature. We consider the example of the Saukas-Song algorithm; we analyze it without expressing the running time in terms of communication rounds. This shows that while in the best case the Saukas-Song algorithm runs in asymptotically optimal time, in general it does not. We propose another algorithm for coarse grained selection that has optimal expected running time.

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Kim, Yoonjin, Hyejin Joo, and Sohyun Yoon. "Inter‐coarse‐grained reconfigurable architecture reconfiguration technique for efficient pipelining of kernel‐stream on coarse‐grained reconfigurable architecture‐based multi‐core architecture." IET Circuits, Devices & Systems 10, no. 4 (July 2016): 251–65. http://dx.doi.org/10.1049/iet-cds.2015.0047.

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Lilja, David J. "A multiprocessor architecture combining fine-grained and coarse-grained parallelism strategies." Parallel Computing 20, no. 5 (May 1994): 729–51. http://dx.doi.org/10.1016/0167-8191(94)90003-5.

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Munaf, S., Dr A. Bharathi, and Dr A. N. Jayanthi. "Double Pumping Low Power Technique for Coarse - Grained Reconfigurable Architecture." International Journal of Electrical and Electronics Research 4, no. 1 (March 31, 2016): 10–15. http://dx.doi.org/10.37391/ijeer.040103.

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Coarse-grained reconfigurable architectures (CGRAs) require many processing elements (PEs) and a con- figuration memory unit (configuration cache) for reconfiguration of its PE array. Though this architecture is meant for high performance and flexibility. Power reduction is very crucial for CGRA to be more competitive and reliable processing core in embedded systems. We propose a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) architecture to reduce power-overhead caused by reconfiguration. The power reduction can be achieved by using the characteristics like double pumping the data bus and an I/O buffer between the memory and the data bus of DDR SDRAM. All modules have been designed at behavioral level with VHDL coding and to Simulate in Xilinx ISE navigator.

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YIN, Shouyi, Chongyong YIN, Leibo LIU, Min ZHU, and Shaojun WEI. "Configuration Context Reduction for Coarse-Grained Reconfigurable Architecture." IEICE Transactions on Information and Systems E95-D, no. 2 (2012): 335–44. http://dx.doi.org/10.1587/transinf.e95.d.335.

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Wang, Chao, Peng Cao, and Jun Yang. "Efficient AES cipher on coarse-grained reconfigurable architecture." IEICE Electronics Express 14, no. 11 (2017): 20170449. http://dx.doi.org/10.1587/elex.14.20170449.

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Dissertations / Theses on the topic "Coarse grained architecture"

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Guo, Yuanqing. "Mapping applications to a coarse-grained reconfigurable architecture." Enschede : University of Twente [Host], 2006. http://doc.utwente.nl/57121.

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Lee, Jong-Suk Mark. "FleXilicon: a New Coarse-grained Reconfigurable Architecture for Multimedia and Wireless Communications." Diss., Virginia Tech, 2010. http://hdl.handle.net/10919/77094.

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High computing power and flexibility are important design factors for multimedia and wireless communication applications due to the demand for high quality services and frequent evolution of standards. The ASIC (Application Specific Integrated Circuit) approach provides an area efficient, high performance solution, but is inflexible. In contrast, the general purpose processor approach is flexible, but often fails to provide sufficient computing power. Reconfigurable architectures, which have been introduced as a compromise between the two extreme solutions, have been applied successfully for multimedia and wireless communication applications. In this thesis, we investigated a new coarse-grained reconfigurable architecture called FleXilicon which is designed to execute critical loops efficiently, and is embedded in an SOC with a host processor. FleXilicon improves resource utilization and achieves a high degree of loop level parallelism (LLP). The proposed architecture aims to mitigate major shortcomings with existing architectures through adoption of three schemes, (i) wider memory bandwidth, (ii) adoption of a reconfigurable controller, and (iii) flexible wordlength support. Increased memory bandwidth satisfies memory access requirement in LLP execution. New design of reconfigurable controller minimizes overhead in reconfiguration and improves area efficiency and reconfiguration overhead. Flexible word-length support improves LLP by increasing the number of processing elements executable. The simulation results indicate that FleXilicon reduces the number of clock cycles and increases the speed for all five applications simulated. The speedup ratios compared with conventional architectures are as large as two orders of magnitude for some applications. VLSI implementation of FleXilicon in 65 nm CMOS process indicates that the proposed architecture can operate at a high frequency up to 1 GHz with moderate silicon area.
Ph. D.

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Malik, Omer. "Pragma-Based Approach For Mapping DSP Functions On A Coarse Grained Reconfigurable Architecture." Licentiate thesis, KTH, Elektronik och Inbyggda System, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-166410.

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Yang, Yu. "BENCHMARK OF TRIGGERED INSTRUCTION BASED COARSE GRAINED RECONFIGURABLE ARCHITECTURE FOR RADIO BASE STATION." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-177446.

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Spatially-programmed architectures such as FPGA are among the most prevailing hardware in various application areas. However FPGA suffers from great overheads such as area, latency and power efficiency. Coarse-grained Reconfigurable Architecture (CGRA) is designed in order to compensate these disadvantages of FPGA. In this thesis, a Triggered Instruction based novel CGRA designed by Intel is evaluated. Benchmark work in this thesis focuses on signal processing area. Three performance limiting functions, Channel Estimation, Radix-2 FFT and Interleaving are selected from LTE Uplink Receiver PHY Benchmark which is an open source benchmark, and implemented and analyzed in Triggered Instruction Architecture (TIA). Throughput-area relationships and throughput/area-area relationships are summarized in curves using a resource estimation method. The benchmark result shows that TIA offers good flexibility for temporal and spatial execution, and a mix of them. Designs in TIA are scalable and adjustable according to different performance requirement. Moreover, based on the development work, this thesis discusses development flow of TIA, various programming techniques, low latency mapping solutions, code size comparison, development environment and integration of heterogeneous system with TIA.

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Zhao, Xin. "High efficiency coarse-grained customised dynamically reconfigurable architecture for digital image processing and compression technologies." Thesis, University of Edinburgh, 2012. http://hdl.handle.net/1842/6187.

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Digital image processing and compression technologies have significant market potential, especially the JPEG2000 standard which offers outstanding codestream flexibility and high compression ratio. Strong demand for high performance digital image processing and compression system solutions is forcing designers to seek proper architectures that offer competitive advantages in terms of all performance metrics, such as speed and power. Traditional architectures such as ASIC, FPGA and DSPs have limitations in either low flexibility or high power consumption. On the other hand, through the provision of a degree of flexibility similar to that of a DSP and performance and power consumption advantages approaching that of an ASIC, coarse-grained dynamically reconfigurable architectures are proving to be strong candidates for future high performance digital image processing and compression systems. This thesis investigates dynamically reconfigurable architectures and especially the newly emerging RICA paradigm. Case studies such as Reed- Solomon decoder and WiMAX OFDM timing synchronisation engine are implemented in order to explore the potential of RICA-based architectures and the possible optimisation approaches such as eliminating conditional branches, reducing memory accesses and constructing kernels. Based on investigations in this thesis, a novel customised dynamically reconfigurable architecture targeting digital image processing and compression applications is devised, which can be tailored to adopt different applications. A demosaicing engine based on the Freeman algorithm is designed and implemented on the proposed architecture as the pre-processing module in a digital imaging system. An efficient data buffer rotating scheme is designed with the aim of reducing memory accesses. Meanwhile an investigation targeting mapping the demosaicing engine onto a dual-core RICA platform is performed. After optimisation, the performance of the proposed engine is carefully evaluated and compared in aspects of throughput and consumed computational resources. When targeting the JPEG2000 standard, the core tasks such as 2-D Discrete Wavelet Transform (DWT) and Embedded Block Coding with Optimal Truncation (EBCOT) are implemented and optimised on the proposed architecture. A novel 2-D DWT architecture based on vector operations associated with RICA paradigm is developed, and the complete DWT application is highly optimised for both throughput and area. For the EBCOT implementation, a novel Partial Parallel Architecture (PPA) for the most computationally intensive module in EBCOT, termed Context Modeling (CM), is devised. Based on the algorithm evaluation, an ARM core is integrated into the proposed architecture for performance enhancement. A Ping-Pong memory switching mode with carefully designed communication scheme between RICA based architecture and ARM is proposed. Simulation results demonstrate that the proposed architecture for JPEG2000 offers significant advantage in throughput.

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Kattah, Senira da Silva. "Controls on deposition and resulting stratal architecture of coarse-grained alluvial and near-shore facies associations /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

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Saraswat, Rohit. "A Finite Domain Constraint Approach for Placement and Routing of Coarse-Grained Reconfigurable Architectures." DigitalCommons@USU, 2010. https://digitalcommons.usu.edu/etd/689.

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Scheduling, placement, and routing are important steps in Very Large Scale Integration (VLSI) design. Researchers have developed numerous techniques to solve placement and routing problems. As the complexity of Application Specific Integrated Circuits (ASICs) increased over the past decades, so did the demand for improved place and route techniques. The primary objective of these place and route approaches has typically been wirelength minimization due to its impact on signal delay and design performance. With the advent of Field Programmable Gate Arrays (FPGAs), the same place and route techniques were applied to FPGA-based design. However, traditional place and route techniques may not work for Coarse-Grained Reconfigurable Architectures (CGRAs), which are reconfigurable devices offering wider path widths than FPGAs and more flexibility than ASICs, due to the differences in architecture and routing network. Further, the routing network of several types of CGRAs, including the Field Programmable Object Array (FPOA), has deterministic timing as compared to the routing fabric of most ASICs and FPGAs reported in the literature. This necessitates a fresh look at alternative approaches to place and route designs. This dissertation presents a finite domain constraint-based, delay-aware placement and routing methodology targeting an FPOA. The proposed methodology takes advantage of the deterministic routing network of CGRAs to perform a delay aware placement.

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Bozetti, Guilherme. "Stratigraphy and architecture of a coarse-grained deep-water system within the Cretaceous Cerro Toto formation, Silla Syncline area, southern Chile." Thesis, University of Aberdeen, 2017. http://digitool.abdn.ac.uk:80/webclient/DeliveryManager?pid=235577.

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The Upper Cretaceous Cerro Toro Formation, southern Chile, is characterised by thinbedded turbidites that envelope a series of coarse-grained, confined slope complex systems, interpreted as part of the Lago Sofia Member. This deep-water slope system overlies basin floor sheets of the Punta Barrosa Formation, and is overlain by the sand-filled slope channels of the Tres Pasos Formation. Particularly distinctive beds, known as TEDs (transitional event deposits), are up to 40 m thick, laterally extensive, have prominent fluted bases, and have a vertical fabric starting with (1) a thin, inversely-graded, clast-supported base; then (2) a normally-graded and clastsupported interval; (3) an increasingly sand and clay matrix-supported conglomerate, with (4) a progressive upwards increase in matrix and normally grading, both in the floating gravel clast and matrix grain sizes, towards the top; and (5) a co-genetic sandstone on top. In the Cerro Toro formation, these TEDs tend to occur as multiple beds in the initial phases of deposition of each channel complex system. The TEDs are highly aggradational, slightly more amalgamated in the channel-axis, and more layered towards the margins. The fabric of these spectacular event beds is described in some detail from measured sections, combined with petrographic analysis and high-resolution field mapping. The 4 km x 200 m channel systems are contained within topographically irregular bathymetric lows that formed sediment pathways, interpreted to be either the result of slope deformation, or contained by poorly preserved, tectonically disrupted or slumped external levee. Syn-sedimentary tectonism is interpreted to be responsible for sharp changes in the system's architecture from channels to ponds, marked by a sharp change in lithofacies from dominantly conglomerates to dominantly sandstones. A refined architectural analysis is proposed, focusing on the recurrent pattern of at least 5 cycles of conglomerate-filled channel systems – ponded sheet sandstones.

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Tuitt, Natasha R. T. "4D interpretation of texture and architecture of a coarse grained slope channel system using automated statistics from high resolution outcrop photography." Thesis, University of Aberdeen, 2014. http://digitool.abdn.ac.uk:80/webclient/DeliveryManager?pid=218284.

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The building blocks of a sedimentary system are essential inputs into studies of reservoir character and comparisons with other sedimentary systems. Yet, our current knowledge of the building blocks of deep water slope channel deposits is still largely speculative. A quantitative approach has been utilised in order to analyse a host of lithological data and objectively identify these sedimentary components. The laterally-extensive and gently-dipping continental slope deposits of the San Fernando Channel System, Baja California, provide the required control on sub-seismic-scale temporal and lateral variations of lithofacies and 3D architecture. High resolution photo-panoramas (with better than 2mm accuracy) of the prominent conglomeratic component of the succession were collected from various key parts of the outcrop. Image analysis of segments extracted from the photo-panoramas generates key parameters for comparison of texture and fabric of conglomerates, such as clast to matrix ratio, major axis length and relative orientation. Statistical analysis of these data enabled the erection of an objective lithofacies scheme for the gravel fraction, the grouping of lithofacies into objectively-defined assemblages, and the establishment of models for the lateral and stratigraphic distributions of these assemblages. 12 lithofacies were objectively identified through hierarchical cluster analysis of 4 quantitative lithological parameters. Statistical analyses indicate significant differences in diversity in the lithofacies assemblages between the early and later parts (termed Stage 1 and Stage 2) of a channel complex set (sensu Sprague, et al., 2002), and to a lesser extent between marginal and axial parts of the system. These can be related to spatial differences and temporal changes in the nature of the turbidity currents flowing through the channel system. Gravelly units become more organised and less diverse with time in one CCS, and each successive CCS more organised at earlier stratigraphic levels than the next, except for the last CCS which is interpreted as influenced by a tectonic paroxysm. These seemingly autocyclic changes in organisation are interpreted as process-responses to changes in equilibrium profile as the nature of confinement changes with the infilling of an initial erosional confinement, to confinement by a master levee and gradual infilling through the evolution of each CCS.

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Das, Satyajit. "Architecture and Programming Model Support for Reconfigurable Accelerators in Multi-Core Embedded Systems." Thesis, Lorient, 2018. http://www.theses.fr/2018LORIS490/document.

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La complexité des systèmes embarqués et des applications impose des besoins croissants en puissance de calcul et de consommation énergétique. Couplé au rendement en baisse de la technologie, le monde académique et industriel est toujours en quête d'accélérateurs matériels efficaces en énergie. L'inconvénient d'un accélérateur matériel est qu'il est non programmable, le rendant ainsi dédié à une fonction particulière. La multiplication des accélérateurs dédiés dans les systèmes sur puce conduit à une faible efficacité en surface et pose des problèmes de passage à l'échelle et d'interconnexion. Les accélérateurs programmables fournissent le bon compromis efficacité et flexibilité. Les architectures reconfigurables à gros grains (CGRA) sont composées d'éléments de calcul au niveau mot et constituent un choix prometteur d'accélérateurs programmables. Cette thèse propose d'exploiter le potentiel des architectures reconfigurables à gros grains et de pousser le matériel aux limites énergétiques dans un flot de conception complet. Les contributions de cette thèse sont une architecture de type CGRA, appelé IPA pour Integrated Programmable Array, sa mise en œuvre et son intégration dans un système sur puce, avec le flot de compilation associé qui permet d'exploiter les caractéristiques uniques du nouveau composant, notamment sa capacité à supporter du flot de contrôle. L'efficacité de l'approche est éprouvée à travers le déploiement de plusieurs applications de traitement intensif. L'accélérateur proposé est enfin intégré à PULP, a Parallel Ultra-Low-Power Processing-Platform, pour explorer le bénéfice de ce genre de plate-forme hétérogène ultra basse consommation
Emerging trends in embedded systems and applications need high throughput and low power consumption. Due to the increasing demand for low power computing and diminishing returns from technology scaling, industry and academia are turning with renewed interest toward energy efficient hardware accelerators. The main drawback of hardware accelerators is that they are not programmable. Therefore, their utilization can be low is they perform one specific function and increasing the number of the accelerators in a system on chip (SoC) causes scalability issues. Programmable accelerators provide flexibility and solve the scalability issues. Coarse-Grained Reconfigurable Array (CGRA) architecture consisting of several processing elements with word level granularity is a promising choice for programmable accelerator. Inspired by the promising characteristics of programmable accelerators, potentials of CGRAs in near threshold computing platforms are studied and an end-to-end CGRA research framework is developed in this thesis. The major contributions of this framework are: CGRA design, implementation, integration in a computing system, and compilation for CGRA. First, the design and implementation of a CGRA named Integrated Programmable Array (IPA) is presented. Next, the problem of mapping applications with control and data flow onto CGRA is formulated. From this formulation, several efficient algorithms are developed using internal resources of a CGRA, with a vision for low power acceleration. The algorithms are integrated into an automated compilation flow. Finally, the IPA accelerator is augmented in PULP - a Parallel Ultra-Low-Power Processing-Platform to explore heterogeneous computing

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Books on the topic "Coarse grained architecture"

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N, Mahapatra Rabi, ed. Design of low-power coarse-grained reconfigurable architectures. Boca Raton, FL: CRC Press, 2011.

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Wijtvliet, Mark, Henk Corporaal, and Akash Kumar. Blocks, Towards Energy-efficient, Coarse-grained Reconfigurable Architectures. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-79774-4.

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Mahapatra, Rabi N., and Yoonjin Kim. Design of Low-Power Coarse-Grained Reconfigurable Architectures. Taylor & Francis Group, 2017.

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Nandy, Soumitra Kumar, and Masahisa Fujita. Coarse Grain Reconfigurable Architectures: Polymorphism in Silicon Cores. Springer, 2016.

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(Foreword), Y. Patt, J. Smith (Foreword), M. Valero (Foreword), Stamatis Vassiliadis (Editor), and Dimitrios Soudris (Editor), eds. Fine- and Coarse-Grain Reconfigurable Computing. Springer, 2007.

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Book chapters on the topic "Coarse grained architecture"

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Wijtvliet, Mark, Henk Corporaal, and Akash Kumar. "Concept of the Blocks Architecture." In Blocks, Towards Energy-efficient, Coarse-grained Reconfigurable Architectures, 61–92. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-79774-4_3.

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Ghariani, Heni, Zied Marrakchi, Abdulfattah Obeid, Mohammed S. BenSaleh, Mohamed Abid, and Habib Mehrez. "New Coarse-Grained Configurable Architecture for DSP Applications." In Computing in Research and Development in Africa, 205–27. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-08239-4_10.

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Xu, Jinhui, Guiming Wu, Yong Dou, and Yazhuo Dong. "Designing a Coarse-Grained Reconfigurable Architecture Using Loop Self-Pipelining." In Advances in Computer Systems Architecture, 567–73. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11859802_59.

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Bouwens, Frank, Mladen Berekovic, Bjorn De Sutter, and Georgi Gaydadjiev. "Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array." In High Performance Embedded Architectures and Compilers, 66–81. Berlin, Heidelberg: Springer Berlin Heidelberg, 2008. http://dx.doi.org/10.1007/978-3-540-77560-7_6.

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Sougoumar, Yazhinian, and Tamilselvan Sadasivam. "Coarse-Grained Architecture Pursuance Investigation with Bidirectional NoC Router." In Algorithms for Intelligent Systems, 127–34. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-4936-6_13.

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de Moura, Rafael Fão, Michael Guilherme Jordan, Antonio Carlos Schneider Beck, and Mateus Beck Rutzig. "Exploiting Partial Reconfiguration on a Dynamic Coarse Grained Reconfigurable Architecture." In Applied Reconfigurable Computing. Architectures, Tools, and Applications, 355–66. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-78890-6_29.

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Käsgen, Philipp S., Markus Weinhardt, and Christian Hochberger. "Dynamic Scheduling of Pipelined Functional Units in Coarse-Grained Reconfigurable Array Elements." In Architecture of Computing Systems – ARCS 2019, 156–67. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-18656-2_12.

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Syrivelis, Dimitris, and Spyros Lalis. "Extracting Coarse-Grained Pipelined Parallelism Out of Sequential Applications for Parallel Processor Arrays." In Architecture of Computing Systems – ARCS 2009, 4–15. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-00454-4_4.

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Jiao, Yuzhong, Xin’an Wang, and Xuewen Ni. "A Fully Data-Driven Reconfigurable Architecture with Very Coarse-Grained Execution Units." In Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, 1–13. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-10485-5_1.

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Lee, Ganghee, Seokhyun Lee, Kiyoung Choi, and Nikil Dutt. "Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable Architecture." In Lecture Notes in Computer Science, 231–43. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-12133-3_22.

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Conference papers on the topic "Coarse grained architecture"

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Sarkar, Ardhendu, and Surajeet Ghosh. "A Coarse-Grained Pipeline Architecture for Sequence Alignment." In 2018 15th IEEE India Council International Conference (INDICON). IEEE, 2018. http://dx.doi.org/10.1109/indicon45594.2018.8987014.

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Lee, Hyuk-Jun, and Michael J. Flynn. "Coarse-grained carry architecture for FPGA (poster abstract)." In the 2000 ACM/SIGDA eighth international symposium. New York, New York, USA: ACM Press, 2000. http://dx.doi.org/10.1145/329166.329211.

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Farooq, Umer, Husain Parvez, Zied Marrakchi, and Habib Mehrez. "A new Tree-based coarse-grained FPGA architecture." In 2009 Ph.D. Research in Microelectronics and Electronics (PRIME). IEEE, 2009. http://dx.doi.org/10.1109/rme.2009.5201347.

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Alnajiar, Dawood, Younghun Ko, Takashi Imagawa, Hiroaki Konoura, Masayuki Hiromoto, Yukio Mitsuyama, Masanori Hashimoto, Hiroyuki Ochi, and Takao Onoye. "Coarse-grained dynamically reconfigurable architecture with flexible reliability." In 2009 International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2009. http://dx.doi.org/10.1109/fpl.2009.5272317.

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Jo, Manhwee, Ganghee Lee, Kyungwook Chang, Kyuseung Han, Kiyoung Choi, Hoonmo Yang, and Kiwook Yoon. "Coarse-grained reconfigurable architecture for multiple application domains." In the 2009 International Conference. New York, New York, USA: ACM Press, 2009. http://dx.doi.org/10.1145/1644993.1645095.

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Yin, Shouyi, Chongyong Yin, Leibo Liu, Min Zhu, Yansheng Wang, and Shaojun Wei. "Reducing configuration contexts for coarse-grained reconfigurable architecture." In 2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012. IEEE, 2012. http://dx.doi.org/10.1109/iscas.2012.6271452.

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Azad, Siavoosh Payandeh, Nasim Farahini, and Ahmed Hemani. "Customization methodology of a Coarse Grained Reconfigurable architecture." In 2014 NORCHIP. IEEE, 2014. http://dx.doi.org/10.1109/norchip.2014.7004736.

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Ran, Duan, and Liang Jie. "A Mapping Strategy for Coarse-grained Reconfigurable Architecture." In 2011 First International Conference on Instrumentation, Measurement, Computer, Communication and Control (IMCCC). IEEE, 2011. http://dx.doi.org/10.1109/imccc.2011.164.

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Cao, Lan, Xinhong Hao, and Xiaolin Chen. "Automatic visualization interface for coarse grained reconfigurable architecture." In 2013 6th International Conference on Biomedical Engineering and Informatics (BMEI). IEEE, 2013. http://dx.doi.org/10.1109/bmei.2013.6747033.

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Parvez, Husain, Zied Marrakchi, Umer Farooq, and Habib Mehrez. "A new coarse-grained FPGA architecture exploration environment." In 2008 International Conference on Field-Programmable Technology (FPT). IEEE, 2008. http://dx.doi.org/10.1109/fpt.2008.4762399.

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Reports on the topic "Coarse grained architecture"

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Sliozberg, Yelena R., and Jan W. Andzelm. Preparation of Entangled Polymer Melts of Various Architecture for Coarse-Grained Models. Fort Belvoir, VA: Defense Technical Information Center, September 2011. http://dx.doi.org/10.21236/ada549947.

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