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Journal articles on the topic 'Coarse-Grained Reconfigurable Architecture'

Author: Grafiati

Published: 4 June 2021

Last updated: 6 September 2023

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1

Lopes, João D., Mário P. Véstias, Rui Policarpo Duarte , Horácio C. Neto, and José T. de Sousa. "Coarse-Grained Reconfigurable Computing with the Versat Architecture." Electronics 10, no. 6 (March 12, 2021): 669. http://dx.doi.org/10.3390/electronics10060669.

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Reconfigurable computing architectures allow the adaptation of the underlying datapath to the algorithm. The granularity of the datapath elements and data width determines the granularity of the architecture and its programming flexibility. Coarse-grained architectures have shown the right balance between programmability and performance. This paper provides an overview of coarse-grained reconfigurable architectures and describes Versat, a Coarse-Grained Reconfigurable Array (CGRA) with self-generated partial reconfiguration, presented as a case study for better understanding these architectures. Unlike most of the existing approaches, which mainly use pre-compiled configurations, a Versat program can generate and apply myriads of on-the-fly configurations. Partial reconfiguration plays a central role in this approach, as it speeds up the generation of incrementally different configurations. The reconfigurable array has a complete graph topology, which yields unprecedented programmability, including assembly programming. Besides being useful for optimising programs, assembly programming is invaluable for working around post-silicon hardware, software, or compiler issues. Results on core area, frequency, power, and performance running different codes are presented and compared to other implementations.

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2

Paek, Jong Kyung, Kiyoung Choi, and Jongeun Lee. "Binary acceleration using coarse-grained reconfigurable architecture." ACM SIGARCH Computer Architecture News 38, no. 4 (September 14, 2010): 33–39. http://dx.doi.org/10.1145/1926367.1926374.

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3

Wijtvliet, Mark, Henk Corporaal, and Akash Kumar. "CGRA-EAM—Rapid Energy and Area Estimation for Coarse-grained Reconfigurable Architectures." ACM Transactions on Reconfigurable Technology and Systems 14, no. 4 (December 31, 2021): 1–28. http://dx.doi.org/10.1145/3468874.

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Reconfigurable architectures are quickly gaining in popularity due to their flexibility and ability to provide high energy efficiency. However, reconfigurable systems allow for a huge design space. Iterative design space exploration (DSE) is often required to achieve good Pareto points with respect to some combination of performance, area, and/or energy. DSE tools depend on information about hardware characteristics in these aspects. These characteristics can be obtained from hardware synthesis and net-list simulation, but this is very time-consuming. Therefore, architecture models are common. This work introduces CGRA-EAM (Coarse-Grained Reconfigurable Architecture - Energy & Area Model), a model for energy and area estimation framework for coarse-grained reconfigurable architectures. The model is evaluated for the Blocks CGRA. The results demonstrate that the mean absolute percentage error is 15.5% and 2.1% for energy and area, respectively, while the model achieves a speedup of close to three orders of magnitude compared to synthesis.

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4

Thomas, Alexander, Michael Rückauer, and Jürgen Becker. "HoneyComb: An Application-Driven Online Adaptive Reconfigurable Hardware Architecture." International Journal of Reconfigurable Computing 2012 (2012): 1–17. http://dx.doi.org/10.1155/2012/832531.

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Since the introduction of the first reconfigurable devices in 1985 the field of reconfigurable computing developed a broad variety of architectures from fine-grained to coarse-grained types. However, the main disadvantages of the reconfigurable approaches, the costs in area, and power consumption, are still present. This contribution presents a solution for application-driven adaptation of our reconfigurable architecture at register transfer level (RTL) to reduce the resource requirements and power consumption while keeping the flexibility and performance for a predefined set of applications. Furthermore, implemented runtime adaptive features like online routing and configuration sequencing will be presented and discussed. A presentation of the prototype chip of this architecture designed in 90 nm standard cell technology manufactured by TSMC will conclude this contribution.

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5

YIN, Shouyi, Chongyong YIN, Leibo LIU, Min ZHU, and Shaojun WEI. "Configuration Context Reduction for Coarse-Grained Reconfigurable Architecture." IEICE Transactions on Information and Systems E95-D, no. 2 (2012): 335–44. http://dx.doi.org/10.1587/transinf.e95.d.335.

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6

Wang, Chao, Peng Cao, and Jun Yang. "Efficient AES cipher on coarse-grained reconfigurable architecture." IEICE Electronics Express 14, no. 11 (2017): 20170449. http://dx.doi.org/10.1587/elex.14.20170449.

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7

Choi, Kiyoung. "Coarse-Grained Reconfigurable Array: Architecture and Application Mapping." IPSJ Transactions on System LSI Design Methodology 4 (2011): 31–46. http://dx.doi.org/10.2197/ipsjtsldm.4.31.

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8

Atak, Oguzhan, and Abdullah Atalar. "BilRC: An Execution Triggered Coarse Grained Reconfigurable Architecture." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, no. 7 (July 2013): 1285–98. http://dx.doi.org/10.1109/tvlsi.2012.2207748.

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9

Kim, Yoonjin, Hyejin Joo, and Sohyun Yoon. "Inter‐coarse‐grained reconfigurable architecture reconfiguration technique for efficient pipelining of kernel‐stream on coarse‐grained reconfigurable architecture‐based multi‐core architecture." IET Circuits, Devices & Systems 10, no. 4 (July 2016): 251–65. http://dx.doi.org/10.1049/iet-cds.2015.0047.

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10

Munaf, S., Dr A. Bharathi, and Dr A. N. Jayanthi. "Double Pumping Low Power Technique for Coarse - Grained Reconfigurable Architecture." International Journal of Electrical and Electronics Research 4, no. 1 (March 31, 2016): 10–15. http://dx.doi.org/10.37391/ijeer.040103.

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Coarse-grained reconfigurable architectures (CGRAs) require many processing elements (PEs) and a con- figuration memory unit (configuration cache) for reconfiguration of its PE array. Though this architecture is meant for high performance and flexibility. Power reduction is very crucial for CGRA to be more competitive and reliable processing core in embedded systems. We propose a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) architecture to reduce power-overhead caused by reconfiguration. The power reduction can be achieved by using the characteristics like double pumping the data bus and an I/O buffer between the memory and the data bus of DDR SDRAM. All modules have been designed at behavioral level with VHDL coding and to Simulate in Xilinx ISE navigator.

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11

YIN, Shouyi, Rui SHI, Leibo LIU, and Shaojun WEI. "Battery-Aware Task Mapping for Coarse-Grained Reconfigurable Architecture." IEICE Transactions on Information and Systems E96.D, no. 12 (2013): 2524–35. http://dx.doi.org/10.1587/transinf.e96.d.2524.

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12

Wu, Kehuai, Andreas Kanstein, Jan Madsen, and Mladen Berekovic. "MT-ADRES: multi-threading on coarse-grained reconfigurable architecture." International Journal of Electronics 95, no. 7 (July 2008): 761–76. http://dx.doi.org/10.1080/00207210802213930.

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13

Yin, ShouYi, ShengJia Shao, LeiBo Liu, and ShaoJun Wei. "MapReduce inspired loop mapping for coarse-grained reconfigurable architecture." Science China Information Sciences 57, no. 12 (December 2014): 1–14. http://dx.doi.org/10.1007/s11432-014-5198-1.

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14

Liu, Leibo, Jianfeng Zhu, Zhaoshi Li, Yanan Lu, Yangdong Deng, Jie Han, Shouyi Yin, and Shaojun Wei. "A Survey of Coarse-Grained Reconfigurable Architecture and Design." ACM Computing Surveys 52, no. 6 (January 21, 2020): 1–39. http://dx.doi.org/10.1145/3357375.

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15

Kim, Yoonjin, Rabi N. Mahapatra, Ilhyun Park, and Kiyoung Choi. "Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17, no. 5 (May 2009): 593–603. http://dx.doi.org/10.1109/tvlsi.2008.2006039.

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16

Alnajjar, Dawood, Hiroaki Konoura, Younghun Ko, Yukio Mitsuyama, Masanori Hashimoto, and Takao Onoye. "Implementing Flexible Reliability in a Coarse-Grained Reconfigurable Architecture." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, no. 12 (December 2013): 2165–78. http://dx.doi.org/10.1109/tvlsi.2012.2228015.

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17

Amagasaki, Motoki, Ryoichi Yamaguchi, Masahiro Koga, Masahiro Iida, and Toshinori Sueyoshi. "An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture." International Journal of Reconfigurable Computing 2008 (2008): 1–14. http://dx.doi.org/10.1155/2008/180216.

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Reconfigurable logic devices (RLDs) are classified as the fine-grained or coarse-grained type based on their basic logic cell architecture. In general, each architecture has its own advantage. Therefore, it is difficult to achieve a balance between the operation speed and implementation area in various applications. In the present paper, we propose a variable grain logic cell (VGLC) architecture, which consists of a 4-bit ripple carry adder with configuration memory bits and develop a technology mapping tool. The key feature of the VGLC architecture is that the variable granularity is a tradeoff between coarse-grained and fine-grained types required for the implementation arithmetic and random logic, respectively. Finally, we evaluate the proposed logic cell using the newly developed technology mapping tool, which improves logic depth by 31% and reduces the number of configuration data by 55% on average, as compared to the Virtex-4 logic cell architecture.

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18

KIM, YOONJIN. "POWER-EFFICIENT CONFIGURATION CACHE STRUCTURE FOR COARSE-GRAINED RECONFIGURABLE ARCHITECTURE." Journal of Circuits, Systems and Computers 22, no. 03 (March 2013): 1350001. http://dx.doi.org/10.1142/s0218126613500011.

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Coarse-grained reconfigurable architectures (CGRA) require many processing elements (PEs) and a configuration memory unit (configuration cache) for reconfiguration of its PE array. Although this structure is meant for high performance and flexibility, it consumes significant power. Specially, power consumption by configuration cache is explicit overhead compared to other types of IP cores. Reducing power in configuration cache is very crucial for CGRA to be more competitive and reliable processing core in embedded systems. In this paper, I propose a power-efficient configuration cache structure based on two design schemes — one is a reusable context pipelining (RCP) architecture to reduce power-overhead caused by reconfiguration and another is a dynamic context management strategy for power saving in configuration cache. This power-efficient approach works without degrading the performance and flexibility of CGRA. Experimental results show that the proposed approach saves 56.50%/86.84% of the average power in write/read-operation of configuration cache compared to the previous design.

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19

Akbari, Omid, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram, and Muhammad Shafique. "Toward Approximate Computing for Coarse-Grained Reconfigurable Architectures." IEEE Micro 38, no. 6 (November 1, 2018): 63–72. http://dx.doi.org/10.1109/mm.2018.2873951.

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20

Sankara Phani, T. Siva, M. Sujatha, K. Hari Kishore, and M. Durga Prakash. "Implementation of FPGA based MRPMA for high performance applications." International Journal of Engineering & Technology 7, no. 1.5 (December 31, 2017): 158. http://dx.doi.org/10.14419/ijet.v7i1.5.9139.

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In the last few decay, Network on Chip’s (NoC) are the powerful chips for high speed communications pertaining to 802.11 Ethernet protocol which is a need to be reconfigurable for successful data frame transmission. The existing architectures like coarse grained reconfigurable, ALU cluster and expression grain reconfigurable architecture and look-up-table used in fine grained reconfigurable devices requires a lot of storage memory, hardware resources such as slices, cell area and cell delay. To tackle these issues, Multigrained Reconfiguration and Parallel Mapping Architecture (MRPMA) is proposed and their performance analysis parameters are calculated. The MRPMA uses the four contributions to optimize Processing Elements (PE’s) operations: 1) Fast Fourier Transformation (FFT) to perform fixed point numbers to the configuration words, 2) Discrete Cosine Transformation (DCT) to analyze the data in the frequency domain, 3) Finite Impulse Response (FIR) for parallel mapping the data and 4) Channel encoder and decoder to encode the data and to calculate the shortest route from source to destination switch.

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21

Lee, Ganghee, Ediz Cetin, and Oliver Diessel. "Fault Recovery Time Analysis for Coarse-Grained Reconfigurable Architectures." ACM Transactions on Embedded Computing Systems 17, no. 2 (April 26, 2018): 1–21. http://dx.doi.org/10.1145/3140944.

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22

Murali, P. "Design of Reusable Context Pipelining for Coarse Grained Reconfigurable Architecture." International Journal for Research in Applied Science and Engineering Technology 6, no. 4 (April 30, 2018): 3584–89. http://dx.doi.org/10.22214/ijraset.2018.4596.

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23

LIANG, Cao, and Xinming HUANG. "Mapping Parallel FFT Algorithm onto SmartCell Coarse-Grained Reconfigurable Architecture." IEICE Transactions on Electronics E93-C, no. 3 (2010): 407–15. http://dx.doi.org/10.1587/transele.e93.c.407.

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24

Wan, Lu, Chen Dong, and Deming Chen. "A Coarse-Grained Reconfigurable Architecture with Compilation for High Performance." International Journal of Reconfigurable Computing 2012 (2012): 1–17. http://dx.doi.org/10.1155/2012/163542.

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We propose afast data relay(FDR) mechanism to enhance existing CGRA (coarse-grained reconfigurable architecture). FDR can not only provide multicycle data transmission in concurrent with computations but also convert resource-demanding inter-processing-element global data accesses into local data accesses to avoid communication congestion. We also propose the supporting compiler techniques that can efficiently utilize the FDR feature to achieve higher performance for a variety of applications. Our results on FDR-based CGRA are compared with two other works in this field: ADRES and RCP. Experimental results for various multimedia applications show that FDR combined with the new compiler deliver up to 29% and 21% higher performance than ADRES and RCP, respectively.

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25

Liang, Shuang, Shouyi Yin, Leibo Liu, Yike Guo, and Shaojun Wei. "A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Acceleration." IEEE Computer Architecture Letters 15, no. 2 (July 1, 2016): 69–72. http://dx.doi.org/10.1109/lca.2015.2458318.

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26

Dou, Yong, GuiMing Wu, JinHui Xu, and XingMing Zhou. "A coarse-grained reconfigurable computing architecture with loop self-pipelining." Science in China Series F: Information Sciences 52, no. 4 (December 4, 2008): 575–87. http://dx.doi.org/10.1007/s11432-008-0146-6.

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27

Zhou, Li, Dongpei Liu, Jianfeng Zhang, and Hengzhu Liu. "Application-specific coarse-grained reconfigurable array: architecture and design methodology." International Journal of Electronics 102, no. 6 (August 8, 2014): 897–910. http://dx.doi.org/10.1080/00207217.2014.942885.

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28

mani, P. Kabila, and C. Gom athy. "Performance Evaluation of LTE Based Coarse Grained Reconfigurable SOC Architecture." International Journal of Electronics and Communication Engineering 6, no. 1 (January 25, 2019): 1–7. http://dx.doi.org/10.14445/23488549/ijece-v6i1p101.

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29

Filho, J. O., S. Masekowsky, T. Schweizer, and W. Rosenstiel. "CGADL: An Architecture Description Language for Coarse-Grained Reconfigurable Arrays." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17, no. 9 (September 2009): 1247–59. http://dx.doi.org/10.1109/tvlsi.2008.2002429.

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30

Kim, Yoonjin, and Rabi N. Mahapatra. "Dynamic Context Compression for Low-Power Coarse-Grained Reconfigurable Architecture." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18, no. 1 (January 2010): 15–28. http://dx.doi.org/10.1109/tvlsi.2008.2006846.

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31

Zhao, Xin, Ahmet T. Erdogan, and Tughrul Arslan. "High-Efficiency Customized Coarse-Grained Dynamically Reconfigurable Architecture for JPEG2000." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, no. 12 (December 2013): 2343–48. http://dx.doi.org/10.1109/tvlsi.2012.2230034.

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32

Akbari, Omid, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram, and Muhammad Shafique. "X-CGRA: An Energy-Efficient Approximate Coarse-Grained Reconfigurable Architecture." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, no. 10 (October 2020): 2558–71. http://dx.doi.org/10.1109/tcad.2019.2937738.

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33

Theocharis, Panagiotis, and Bjorn De Sutter. "A Bimodal Scheduler for Coarse-Grained Reconfigurable Arrays." ACM Transactions on Architecture and Code Optimization 13, no. 2 (June 27, 2016): 1–26. http://dx.doi.org/10.1145/2893475.

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34

WANG, Da-Wei, Yong DOU, and Si-Kun LI. "Loop Kernel Pipelining Mapping onto Coarse-Grained Reconfigurable Architectures." Chinese Journal of Computers 32, no. 6 (August 11, 2009): 1089–99. http://dx.doi.org/10.3724/sp.j.1016.2009.01089.

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35

Lee, Jong Eun, Kiyoung Choi, and Nikil Dutt. "Evaluating memory architectures for media applications on Coarse-grained Reconfigurable Architectures." International Journal of Embedded Systems 3, no. 3 (2008): 119. http://dx.doi.org/10.1504/ijes.2008.020293.

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36

KOJIMA, Takuya, and Hideharu AMANO. "A Fine-Grained Multicasting of Configuration Data for Coarse-Grained Reconfigurable Architectures." IEICE Transactions on Information and Systems E102.D, no. 7 (July 1, 2019): 1247–56. http://dx.doi.org/10.1587/transinf.2018edp7336.

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37

Chen, Naijin, Zhen Wang, Ruixiang He, Jianhui Jiang, Fei Cheng, and Chenghao Han. "Efficient scheduling mapping algorithm for row parallel coarse-grained reconfigurable architecture." Tsinghua Science and Technology 26, no. 5 (October 2021): 724–35. http://dx.doi.org/10.26599/tst.2020.9010035.

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38

Zhang, Huizhen, Yubiao Pan, Yiwen Zhang, and Cheng Wang. "Allocating resources based on a model of coarse-grained reconfigurable architecture." Journal of Engineering 2019, no. 10 (October 1, 2019): 7272–78. http://dx.doi.org/10.1049/joe.2018.5230.

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39

Dimitroulakos, Grigorios, Stavros Georgiopoulos, Michalis D. Galanis, and Costas E. Goutis. "Resource aware mapping on coarse grained reconfigurable arrays." Microprocessors and Microsystems 33, no. 2 (March 2009): 91–105. http://dx.doi.org/10.1016/j.micpro.2008.07.002.

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40

Chen, Longlong, Jianfeng Zhu, Yangdong Deng, Zhaoshi Li, Jian Chen, Xiaowei Jiang, Shouyi Yin, Shaojun Wei, and Leibo Liu. "An Elastic Task Scheduling Scheme on Coarse-Grained Reconfigurable Architectures." IEEE Transactions on Parallel and Distributed Systems 32, no. 12 (December 1, 2021): 3066–80. http://dx.doi.org/10.1109/tpds.2021.3084804.

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41

Rouson, Damian W. I., and Yi Xiong. "Design Metrics in Quantum Turbulence Simulations: How Physics Influences Software Architecture." Scientific Programming 12, no. 3 (2004): 185–96. http://dx.doi.org/10.1155/2004/910505.

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The information hiding philosophy of object-oriented programming encourages localizing data structures within objects rather than sharing data globally across different classes of objects. This emphasis on local data leads naturally to fine-grained data abstractions, particularly in scientific simulations involving large collections of small, discrete physical or mathematical objects. This paper focuses on a subset of such simulations where dynamically reconfigurable links bind the objects together. It is demonstrated that fine-grained data structures reduce the complexity of local operations on the data at the potential expense of increased global operation complexity. Two metrics are used to describe data structures: granularity is the number of instantiations required to cover the data space, whereas extent is the continuously traversable length of the data along a given direction. These definitions are applied to two abstractions for simulating the turbulent motion of quantum vortices in superfluid liquid helium. Several local and global operations on a fine-grained linked list are compared with those on a coarse-grained array. It is demonstrated that fine-grained data structures recover the simplicity of more coarse-grained structures if maximal extent is maintained as the granularity increases.

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42

Venkataramani, Girish, Walid Najjar, Fadi Kurdahi, Nader Bagherzadeh, Wim Bohm, and Jeff Hammes. "Automatic compilation to a coarse-grained reconfigurable system-opn-chip." ACM Transactions on Embedded Computing Systems 2, no. 4 (November 2003): 560–89. http://dx.doi.org/10.1145/950162.950167.

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43

Dimitroulakos, Grigorios, Nikos Kostaras, Michalis D. Galanis, and Costas E. Goutis. "Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays." Journal of Supercomputing 48, no. 2 (May 16, 2008): 115–51. http://dx.doi.org/10.1007/s11227-008-0208-y.

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44

Rauwerda, G. K., P. M. Heysters, and G. J. M. Smit. "Towards Software Defined Radios Using Coarse-Grained Reconfigurable Hardware." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16, no. 1 (January 2008): 3–13. http://dx.doi.org/10.1109/tvlsi.2007.912075.

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45

Patel, Kunjan, Séamas McGettrick, and C. J. Bleakley. "Rapid functional modelling and simulation of coarse grained reconfigurable array architectures." Journal of Systems Architecture 57, no. 4 (April 2011): 383–91. http://dx.doi.org/10.1016/j.sysarc.2011.02.006.

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46

Wang, Chao, Peng Cao, Bo Liu, and Jun Yang. "Coarse-grained reconfigurable architecture with hierarchical context cache structure and management approach." IEICE Electronics Express 14, no. 6 (2017): 20170090. http://dx.doi.org/10.1587/elex.14.20170090.

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47

Liang, Cao, and Xinming Huang. "SmartCell: An Energy Efficient Coarse-Grained Reconfigurable Architecture for Stream-Based Applications." EURASIP Journal on Embedded Systems 2009 (2009): 1–15. http://dx.doi.org/10.1155/2009/518659.

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48

Cao, Peng, Bo Liu, Jinjiang Yang, Jun Yang, Meng Zhang, and Longxing Shi. "Context Management Scheme Optimization of Coarse-Grained Reconfigurable Architecture for Multimedia Applications." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, no. 8 (August 2017): 2321–31. http://dx.doi.org/10.1109/tvlsi.2017.2695493.

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49

Kim, Yoonjin, Rabi N. Mahapatra, and Kiyoung Choi. "Design Space Exploration for Efficient Resource Utilization in Coarse-Grained Reconfigurable Architecture." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18, no. 10 (October 2010): 1471–82. http://dx.doi.org/10.1109/tvlsi.2009.2025280.

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50

Kim, Wonsub, Yoonseo Choi, and Haewoo Park. "Fast modulo scheduler utilizing patternized routes for coarse-grained reconfigurable architectures." ACM Transactions on Architecture and Code Optimization 10, no. 4 (December 2013): 1–24. http://dx.doi.org/10.1145/2541228.2555314.

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