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Relevant bibliographies by topics / Combinatorial circuits

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Academic literature on the topic 'Combinatorial circuits'

Author: Grafiati

Published: 4 June 2021

Last updated: 20 February 2023

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Journal articles on the topic "Combinatorial circuits"

1

Tsuiki, Shigeya, and Takahiro Haga. "AND-inverse detecting circuit for the combinatorial logic circuits." Electronics and Communications in Japan (Part III: Fundamental Electronic Science) 73, no. 11 (1990): 51–60. http://dx.doi.org/10.1002/ecjc.4430731106.

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Matsushima, Ayano, and Ann M. Graybiel. "Combinatorial Developmental Controls on Striatonigral Circuits." Cell Reports 38, no. 2 (January 2022): 110272. http://dx.doi.org/10.1016/j.celrep.2021.110272.

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Matsushima, Ayano, and Ann M. Graybiel. "Combinatorial Developmental Controls on Striatonigral Circuits." Cell Reports 31, no. 11 (June 2020): 107778. http://dx.doi.org/10.1016/j.celrep.2020.107778.

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Donovan, Zola, Gregory Gutin, Vahan Mkrtchyan, and K. Subramani. "Clustering without replication in combinatorial circuits." Journal of Combinatorial Optimization 38, no. 2 (February 21, 2019): 481–501. http://dx.doi.org/10.1007/s10878-019-00394-1.

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Fang, K. Y., and A. S. Wojcik. "Modular decomposition of combinatorial multiple-values circuits." IEEE Transactions on Computers 37, no. 10 (1988): 1293–301. http://dx.doi.org/10.1109/12.5993.

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Chen, Ethan, and Vanessa Chen. "Statistical RF/Analog Integrated Circuit Design Using Combinatorial Randomness for Hardware Security Applications." Mathematics 8, no. 5 (May 20, 2020): 829. http://dx.doi.org/10.3390/math8050829.

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While integrated circuit technologies keep scaling aggressively, analog, mixed-signal, and radio-frequency (RF) circuits encounter challenges by creating robust designs in advanced complementary metal–oxide–semiconductor (CMOS) processes with the diminishing voltage headroom. The increasing random mismatch of smaller feature sizes in leading-edge technology nodes severely limit the benefits of scaling for (RF)/analog circuits. This paper describes the details of the combinatorial randomness by statistically selecting device elements that relies on the significant growth in subsets number of combinations. The randomness can be utilized to provide post-manufacturing reconfiguration of the selectable circuit elements to achieve required specifications for ultra-low-power systems. The calibration methodology is demonstrated with an ultra-low-voltage chaos-based true random number generator (TRNG) for energy-constrained Internet of things (IoT) devices in the secure communications.

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URAHAMA, KIICHI, and SHIN-ICHIRO UENO. "A GRADIENT SYSTEM SOLUTION TO POTTS MEAN FIELD EQUATIONS AND ITS ELECTRONIC IMPLEMENTATION." International Journal of Neural Systems 04, no. 01 (March 1993): 27–34. http://dx.doi.org/10.1142/s0129065793000043.

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A gradient system solution method is presented for solving Potts mean field equations for combinatorial optimization problems subject to winner-take-all constraints. In the proposed solution method the optimum solution is searched by using gradient descent differential equations whose trajectory is confined within the feasible solution space of optimization problems. This gradient system is proven theoretically to always produce a legal local optimum solution of combinatorial optimization problems. An elementary analog electronic circuit implementing the presented method is designed on the basis of current-mode subthreshold MOS technologies. The core constituent of the circuit is the winner-take-all circuit developed by Lazzaro et al. Correct functioning of the presented circuit is exemplified with simulations of the circuits implementing the scheme for solving the shortest path problems.

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Wróblewski, Artur, Christian V. Schimpfle, Otto Schumacher, and Josef A. Nossek. "Minimizing Spurious Switching Activities with Transistor Sizing." VLSI Design 15, no. 2 (January 1, 2002): 537–45. http://dx.doi.org/10.1080/1065514021000012156.

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In combinatorial blocks of static CMOS circuits transistor sizing can be applied for delay balancing as to guarantee synchronously arriving signal slopes at the input of logic gates, thereby avoiding glitches. Since the delay of logic gates depends directly on transistor sizes, their variation allows equalizing different path delays without influencing the total delay of the circuit. Unfortunately, not only the delay, but also power consumption circuits depend on the transistor sizes. To achieve optimal results, transistor lengths have to be increased, which results in both increased gate capacitances and area. Splitting the long transistors counteracts this negative influence.

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Zhu, Enqiang, Congzhou Chen, Yongsheng Rao, and Weicheng Xiong. "Biochemical Logic Circuits Based on DNA Combinatorial Displacement." IEEE Access 8 (2020): 34096–103. http://dx.doi.org/10.1109/access.2020.2974024.

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Fujiwara, Yuichiro, and Charles J. Colbourn. "A Combinatorial Approach to X-Tolerant Compaction Circuits." IEEE Transactions on Information Theory 56, no. 7 (July 2010): 3196–206. http://dx.doi.org/10.1109/tit.2010.2048468.

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Dissertations / Theses on the topic "Combinatorial circuits"

1

Agnihotri, Ameya Ramesh. "Combinatorial optimization techniques for VLSI placement." Diss., Online access via UMI:, 2007.

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Cox, Robert Sidney Sternberg Paul W. Sternberg Paul W. "Transcriptional regulation and combinatorial genetic logic in synthetic bacterial circuits /." Diss., Pasadena, Calif. : California Institute of Technology, 2008. http://resolver.caltech.edu/CaltechETD:etd-03042008-130011.

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Rinderknecht, William John. "A power reduction algorithm for combinatorial CMOS circuits using input disabling." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/36543.

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Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.<br>Includes bibliographical references (p. 61-62).<br>by William John Rinderknecht.<br>M.S.

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Hacker, Charles Hilton, and n/a. "WinLogiLab - A Computer-Based Teaching Suite for Digital Logic Design." Griffith University. School of Engineering, 2001. http://www4.gu.edu.au:8080/adt-root/public/adt-QGU20050915.172404.

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This thesis presents an interactive computerised teaching suite developed for the design of combinatorial and sequential logic circuits. This suite fills a perceived gap in the currently available computer-based teaching software for digital logic design. Several existing digital logic educational software are available, however these existing programs were found to be unsuitable for our use in providing alternative mode subject delivery. This prompted the development of a Microsoft Windows TM tutorial suite, called WinLogiLab. WinLogiLab comprises of a set of tutorials that uses student provided input data, to perform the initial design steps for digital Combinatorial and Sequential logic circuits. The combinatorial tutorials are designed to show the link between Boolean Algebra and Digital Logic circuits, and follows the initial design steps: from Boolean algebra, truth tables, to Exact and the Heuristic minimisation techniques, to finally produce the combinatorial circuit. Similarly, the sequential tutorials can design simple State Machine Counters, and can model more complex Finite State Automata.

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Hacker, Charles. "WinLogiLab - A Computer-Based Teaching Suite for Digital Logic Design." Thesis, Griffith University, 2001. http://hdl.handle.net/10072/367209.

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This thesis presents an interactive computerised teaching suite developed for the design of combinatorial and sequential logic circuits. This suite fills a perceived gap in the currently available computer-based teaching software for digital logic design. Several existing digital logic educational software are available, however these existing programs were found to be unsuitable for our use in providing alternative mode subject delivery. This prompted the development of a Microsoft Windows TM tutorial suite, called WinLogiLab. WinLogiLab comprises of a set of tutorials that uses student provided input data, to perform the initial design steps for digital Combinatorial and Sequential logic circuits. The combinatorial tutorials are designed to show the link between Boolean Algebra and Digital Logic circuits, and follows the initial design steps: from Boolean algebra, truth tables, to Exact and the Heuristic minimisation techniques, to finally produce the combinatorial circuit. Similarly, the sequential tutorials can design simple State Machine Counters, and can model more complex Finite State Automata.<br>Thesis (Masters)<br>Master of Philosophy (MPhil)<br>School of Engineering<br>Science, Environment, Engineering and Technology<br>Full Text

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Coward, Bob. "Genroute : a genetic algorithm (printed wire board (PWB) router) /." Online version of thesis, 1991. http://hdl.handle.net/1850/10711.

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Duran, Arqué Berta. "Combinatorial perspective on the gene expression circuits established by the CPEB-family of RNA binding proteins." Doctoral thesis, Universitat de Barcelona, 2020. http://hdl.handle.net/10803/673591.

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The complex changes that take place in the mature Xenopus oocyte and early embryo are orchestrated in the absence of transcription. Until zygotic transcription starts, after the mid-blastula transition, cells rely on tight spatiotemporal translational regulation. Some maternal mRNAs accumulate during oocyte growth and are stored, translationally silent. Upon stimuli, stored, silenced mRNAs become cytoplasmically polyadenylated and, subsequently, engage in translation. The timing and extent of translational activation are dictated by a complex code of 3’UTR motifs recognized by RNA-binding proteins. In meiotic maturation, at least three sequential polyadenylation waves occur. First, in response to progesterone, a single Aurora kinase A phosphorylation triggers CPEB1-directed cytoplasmic polyadenylation of mRNAs that are required for Cdk1 activation and meiotic progression. Second, activated Cdk1 targets CPEB1 for degradation, triggering a second polyadenylation surge that is necessary for the MI-MII transition. Last, CPEB4, synthesized from the first wave and activated by Cdk1 and ERK2 upon meiotic progression, drives a third wave during the second meiotic division that is required for the metaphase-II arrest. Unlike the well-studied roles of CPEB1 and CPEB4, the roles of the remaining family members, CPEB2 and CPEB3, remain uncharacterized. In this thesis we have performed a systematic investigation of the CPEB-family of RBPs in meiotic maturation in order to elucidate their combinatorial contribution to gene expression regulation. We have determined that CPEB1 and the CPEB2-4 subfamily differ in their expression dynamics, concentration and regulation. Like CPEB4, CPEB2 and CPEB3 are regulated by N-terminal hyperphosphorylation that causes dissolution of the CPEB-condensates. Furthermore, we have found that all CPEBs co-localize and are proximal to mRNA repression and storage proteins, probably reflecting their inclusion within large repressive mRNPs in the oocyte. We have also found that all CPEBs bind a highly overlapping subset of mRNAs, although CPEB1 and CPEB2-4 could differentially regulate a small subset of targets. All in all, we have contributed to the understanding of how the multiple CPEBs co-exist and how their activities are coordinated in the cell to dictate complex expression patterns.<br>La maduración meiótica y la embriogénesis temprana de Xenopus se dan en ausencia de transcripción. Hasta la transición materno-cigótica – después de la 12ª división embrionaria - la transcripción no se re-inicia y todos los cambios en expresión génica ocurren por mecanismos post- transcripcionales, entre los cuales destaca la poliadenilación citoplasmática. Durante su crecimiento, el oocito produce grandes cantidades de mRNA que mantiene silenciados, con una cola de poly(A) corta. En la maduración y embriogénesis, ciertos mRNAs son poliadenilados y traducidos. Cuando y cuanto cada mRNA es movilizado depende de la combinación de señales presentes en su 3’UTR y de las proteínas de unión al RNA que las reconocen. En la maduración meiótica se dan, al menos, tres olas secuenciales de poliadenilación. La primera es iniciada en respuesta a progesterona. Concretamente, la fosforilación por Aurora quinasa A causa la remodelación del complejo de represión de CPEB1 a complejo de activación, permitiendo la expresión de genes necesarios para la progresión meiótica, como Cdk1. Seguidamente, Cdk1 participa en la degradación de CPEB1 generando una segunda ola que es necesaria para la interkinesis. Por último, CPEB4, producida en la primera ola de poliadenilación y activada por fosforilación por Cdk1 abandera una tercera ola que posibilita la expresión de proteínas que mantienen el arresto en metafase-II. A diferencia de sus homólogos CPEB1 y CPEB4, los papeles de CPEB2 y CPEB3 en maduración meiótica siguen sin caracterizar. Por ello y para entender como esta familia de proteínas de unión al RNA se coordina para dictar la expresión génica hemos realizado una investigación sistemática y comparativa de las CPEBs en maduración meiótica.

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Goulart, Sobrinho Edilton Furquim [UNESP]. "Uma ferramenta alternativa para síntese de circuitos lógicos usando a técnica de circuito evolutivo." Universidade Estadual Paulista (UNESP), 2007. http://hdl.handle.net/11449/87253.

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Made available in DSpace on 2014-06-11T19:22:35Z (GMT). No. of bitstreams: 0 Previous issue date: 2007-05-25Bitstream added on 2014-06-13T20:49:18Z : No. of bitstreams: 1 goulartsobrinho_ef_me_ilha.pdf: 944900 bytes, checksum: 47dc5d964428b7cb8bd18e1e00e1d994 (MD5)<br>Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)<br>Neste trabalho descreve-se uma metodologia para síntese e otimização de circuitos digitais, usando a teoria de algoritmos evolutivos e como plataforma os dispositivos reconfiguráveis, denominada Hardware Evolutivo do inglês- Evolvable Hardware - EHW. O EHW, tornou-se viável com o desenvolvimento em grande escala dos dispositivos reconfiguráveis, Programmable Logic Devices (PLD s), cuja arquitetura e função podem ser determinadas por programação. Cada circuito pode ser representado como um indivíduo em um processo evolucionário, evoluindo-o através de operações genéticas para um resultado desejado. Como algoritmo evolutivo, aplicou-se o Algoritmo Genético (AG), uma das técnicas da computação evolutiva que utiliza os conceitos da genética e seleção natural. O processo de síntese aplicado neste trabalho, inicia por uma descrição do comportamento do circuito, através de uma tabela verdade para circuitos combinacionais e a tabela de estados para os circuitos seqüenciais. A técnica aplicada busca o arranjo correto e minimizado do circuito que desempenhe uma função proposta. Com base nesta metodologia, são implementados alguns exemplos em duas diferentes representações (mapas de fusíveis e matriz de portas lógicas).<br>In this work was described a methodology for optimization and synthesis of digital circuits, which consist of evolving circuits through evolvable algorithms using as platforms reconfigurable devices, denominated Evolvable Hardware (EHW). It was became viable with the large scale development of reconfigurable devices, whose architecture and function can be determined by programming. Each circuit can be represented as an individual within an evolutionary process, evolving through genetic operations to desire results. Genetic Algorithm (GA) was applied as evolutionary algorithm where this technique evolvable computation as concepts of genetics and natural selection. The synthesis process applied in this work starts from a description from the circuits behavior. Trust table for combinatorial circuits and state transition table for sequential circuits were used for synthesis process. This technic applied search the correct arrange and minimized circuit which response the propose function. Based on this methodology, some examples are implemented in two different representations (fuse maps and logic gate matrices).

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Nafkha, Amor. "A geometrical approach detector for solving the combinatorial optimisation problem : application in wireless communication systems." Lorient, 2006. http://www.theses.fr/2006LORIS067.

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Cette thèse s'intéresse à la résolution du problème classique de décodage d'un mélange linéaire entaché d'un bruit additif gaussien. A partir d'une observation bruitée: y = Hx+b, d'un vecteur d'entiers x mélangé linéairement par une matrice H connue, b étant un vecteur de bruit, on cherche le vecteur x minimisant la distance Euclidienne entre y et le vecteur Hx. Ce problème est réputé NP-complet. Il intervient dans un grand nombre de systèmes de télécommunications (MIMO, MC-CDMA, etc. ). Nous proposons dans cette thèse un algorithme de résolution quasi optimal de ce problème et bien adapté à une implémentation matérielle. Notre démarche s'appuie sur l'utilisation des méthodes classiques de recherche opérationnelle : trouver des points initiaux répartis sur l'espace des solutions possibles et potentiellement proches de la solution optimale (diversification) et effectuer une recherche locale au voisinage des ces points (intensification). Dans ce travail, la diversification est basée sur une approche géométrique utilisant les axes dominants de concentration du bruit. Les performances en terme de taux d'erreur par bit de la méthode proposée sont proches de l'optimum tout en gardant une complexité constante et un degré de parallélisme important. Nous avons étendu cette méthode à la constellation MAQ-16 d'une part, et à la génération d'une décision souple d'autre part. Nous avons étudié l'algorithme proposé du point de vue implémentation matérielle. L'algorithme proposé présente d'une part une nouvelle alternative pour le décodage quasi optimal du mélange bruité et d'autre part un important degré de parallélisme permettant une implémentation efficace<br>The demand for mobile communication systems with high data rates and improved link quality for a variety of applications has dramatically increased in recent years. New concepts and methods are necessary in order to cover this huge demand, which counteract or take advantage of the impairments of the mobile communication channel and optimally exploit the limited resources such as bandwidth and power. The problem of finding the least-squares solution to a system of linear equations where the unknown vector is comprised of integers, but the matrix coefficients and given vector are comprised of real numbers, arise in many applications: communications, cryptography, MC-CDMA, MIMO, to name a few. The Maximum Likelihood (ML) decoding is equivalent to finding the closest lattice point in an n-dimensional real space. In general, this problem is known to be non deterministic NP hard. In this thesis, a polynomial-time approximation method called Geometrical Intersection and Selection Detector (GISD) is applied to the MLD problem. Moreover, the proposed approach is based on two complementary "real time" operational research methods: intensification and diversification. Our approach has three important characteristics that make it very attractive for for VLSI implementation. First, It will be shown that the performance of GISD receiver is superior as compared to other sub-optimal detection methods and it provides a good approximation to the optimal detector. Second, the inherent parallel structure of the proposed method leads to a very suitable hardware implementation. Finaly, The GISD allows a near optimal performance with constant polynomial-time, O(n3), computational complexity (unlike the sphere decoding that has exponential-time complexity for low SNR). The proposed Detector can be efficiently employed in most wireless communications systems: MIMO, MC-CDMA, MIMO-CDMA etc. .

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Goulart, Sobrinho Edilton Furquim. "Uma ferramenta alternativa para síntese de circuitos lógicos usando a técnica de circuito evolutivo /." Ilha Solteira : [s.n.], 2007. http://hdl.handle.net/11449/87253.

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Orientador: Suely Cunha Amaro Mantovani<br>Banca: José Raimundo de Oliveira<br>Banca: Nobuo Oki<br>Resumo: Neste trabalho descreve-se uma metodologia para síntese e otimização de circuitos digitais, usando a teoria de algoritmos evolutivos e como plataforma os dispositivos reconfiguráveis, denominada Hardware Evolutivo do inglês- Evolvable Hardware - EHW. O EHW, tornou-se viável com o desenvolvimento em grande escala dos dispositivos reconfiguráveis, Programmable Logic Devices (PLDs), cuja arquitetura e função podem ser determinadas por programação. Cada circuito pode ser representado como um indivíduo em um processo evolucionário, evoluindo-o através de operações genéticas para um resultado desejado. Como algoritmo evolutivo, aplicou-se o Algoritmo Genético (AG), uma das técnicas da computação evolutiva que utiliza os conceitos da genética e seleção natural. O processo de síntese aplicado neste trabalho, inicia por uma descrição do comportamento do circuito, através de uma tabela verdade para circuitos combinacionais e a tabela de estados para os circuitos seqüenciais. A técnica aplicada busca o arranjo correto e minimizado do circuito que desempenhe uma função proposta. Com base nesta metodologia, são implementados alguns exemplos em duas diferentes representações (mapas de fusíveis e matriz de portas lógicas).<br>Abstract: In this work was described a methodology for optimization and synthesis of digital circuits, which consist of evolving circuits through evolvable algorithms using as platforms reconfigurable devices, denominated Evolvable Hardware (EHW). It was became viable with the large scale development of reconfigurable devices, whose architecture and function can be determined by programming. Each circuit can be represented as an individual within an evolutionary process, evolving through genetic operations to desire results. Genetic Algorithm (GA) was applied as evolutionary algorithm where this technique evolvable computation as concepts of genetics and natural selection. The synthesis process applied in this work starts from a description from the circuits behavior. Trust table for combinatorial circuits and state transition table for sequential circuits were used for synthesis process. This technic applied search the correct arrange and minimized circuit which response the propose function. Based on this methodology, some examples are implemented in two different representations (fuse maps and logic gate matrices).<br>Mestre

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Books on the topic "Combinatorial circuits"

1

Lengauer, T. Combinatorial algorithms for integrated circuit layout. Stuttgart: B.G. Teubner, 1990.

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Lengauer, Thomas. Combinatorial algorithms for integrated circuit layout. Chichester: Wiley, 1990.

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Engineering genetic circuits. Boca Raton: Chapman & Hall/CRC, 2010.

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Lengauer, Thomas. Combinatorial Algorithms for Integrated Circuit Layout. Wiesbaden: Vieweg+Teubner Verlag, 1990. http://dx.doi.org/10.1007/978-3-322-92106-2.

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Lengauer, T. Combinatorial Algorithms for Integrated Circuit Layout. Wiesbaden: Vieweg+Teubner Verlag, 1992.

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International Conference on Microreaction Technology (1st 1997). Microreaction technology: Proceedings of the First International Conference on Microreaction Technology. Berlin: Springer, 1998.

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Braun, Jaromír. Kombinatorické metody v analýze a modelování elektronických soustav. Praha: Academia, 1990.

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Barg, Alexander, and O. R. Musin. Discrete geometry and algebraic combinatorics. Providence, Rhode Island: American Mathematical Society, 2014.

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Myasnikov, Alexei G. Non-commutative cryptography and complexity of group-theoretic problems. Providence, R.I: American Mathematical Society, 2011.

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Morse, Robert Fitzgerald, editor of compilation, Nikolova-Popova, Daniela, 1952- editor of compilation, and Witherspoon, Sarah J., 1966- editor of compilation, eds. Group theory, combinatorics and computing: International Conference in honor of Daniela Nikolova-Popova's 60th birthday on Group Theory, Combinatorics and Computing, October 3-8, 2012, Florida Atlantic University, Boca Raton, Florida. Providence, Rhode Island: American Mathematical Society, 2013.

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Book chapters on the topic "Combinatorial circuits"

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Tietze, Ulrich, Christoph Schenk, and Eberhard Gamm. "Combinatorial Circuits." In Electronic Circuits, 635–58. Berlin, Heidelberg: Springer Berlin Heidelberg, 2008. http://dx.doi.org/10.1007/978-3-540-78655-9_8.

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Adam, Hans-Joachim, and Mathias Adam. "Combinatorial Circuits with PLC." In PLC Programming In Instruction List According To IEC 61131-3, 69–87. Berlin, Heidelberg: Springer Berlin Heidelberg, 2022. http://dx.doi.org/10.1007/978-3-662-65254-1_5.

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Donovan, Zola, K. Subramani, and Vahan Mkrtchyan. "Disjoint Clustering in Combinatorial Circuits." In Lecture Notes in Computer Science, 201–13. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-25005-8_17.

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Groote, Jan Friso, Rolf Morel, Julien Schmaltz, and Adam Watkins. "Basic components and combinatorial circuits." In Logic Gates, Circuits, Processors, Compilers and Computers, 1–22. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-68553-9_1.

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Mankowski, Michal, and Mikhail Moshkov. "Circuits and Cost Functions." In Dynamic Programming Multi-Objective Combinatorial Optimization, 17–27. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-63920-4_2.

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Donovan, Zola, Vahan Mkrtchyan, and K. Subramani. "On Clustering Without Replication in Combinatorial Circuits." In Combinatorial Optimization and Applications, 334–47. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-26626-8_25.

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Ellis, Samuel J., Titus H. Klinge, and James I. Lathrop. "Robust Combinatorial Circuits in Chemical Reaction Networks." In Theory and Practice of Natural Computing, 178–89. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-71069-3_14.

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Hoory, Shlomo, Avner Magen, and Toniann Pitassi. "Monotone Circuits for the Majority Function." In Approximation, Randomization, and Combinatorial Optimization. Algorithms and Techniques, 410–25. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11830924_38.

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Gupta, Meenakshi, Vikram Kumar Kamboj, and R. K. Sharma. "A novel hybrid GWO-PS based solution approach for combinatorial unit commitment problem." In Intelligent Circuits and Systems, 417–24. London: CRC Press, 2021. http://dx.doi.org/10.1201/9781003129103-65.

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Klivans, Adam R. "On the Derandomization of Constant Depth Circuits." In Approximation, Randomization, and Combinatorial Optimization: Algorithms and Techniques, 249–60. Berlin, Heidelberg: Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/3-540-44666-4_28.

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Conference papers on the topic "Combinatorial circuits"

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Wirth, Gilson I., Michele G. Vieira, Egas Henes Neto, and F. G. L. Kastensmidt. "Single event transients in combinatorial circuits." In the 18th annual symposium. New York, New York, USA: ACM Press, 2005. http://dx.doi.org/10.1145/1081081.1081115.

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Wirth, Gilson I., Michele G. Vieira, Egas Henes Neto, and F. G. L. Kastensmidt. "Single Event Transients in Combinatorial Circuits." In 2005 18th Symposium on Integrated Circuits and Systems Design. IEEE, 2005. http://dx.doi.org/10.1109/sbcci.2005.4286843.

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Kiselyov, Oleg, Kedar N. Swadi, and Walid Taha. "A methodology for generating verified combinatorial circuits." In the fourth ACM international conference. New York, New York, USA: ACM Press, 2004. http://dx.doi.org/10.1145/1017753.1017794.

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Serlet, B. P. "Fast, small, and static combinatorial CMOS circuits." In 24th ACM/IEEE conference proceedings. New York, New York, USA: ACM Press, 1987. http://dx.doi.org/10.1145/37888.37955.

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Strukov, Dmitri. "Solving Combinatorial Optimization Problems with Nanoelectronic Neuromorphic Circuits." In Neuromorphic Materials, Devices, Circuits and Systems. València: FUNDACIO DE LA COMUNITAT VALENCIANA SCITO, 2023. http://dx.doi.org/10.29363/nanoge.neumatdecas.2023.006.

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Oraon, Neha, and Madhav Rao. "Delay approximation for nanomagnetic logic based combinatorial circuits." In 2019 IEEE 14th International Conference on Nano/Micro Engineered and Molecular Systems (NEMS). IEEE, 2019. http://dx.doi.org/10.1109/nems.2019.8915607.

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Srivastava, Atul K., and Hariom Gupta. "Cluster growth technique for combinatorial evolvable digital circuits." In 2014 Seventh International Conference on Contemporary Computing (IC3). IEEE, 2014. http://dx.doi.org/10.1109/ic3.2014.6897189.

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Guindi, R. S. "Gate-leakage estimation and minimization in CMOS combinatorial circuits." In Proceedings of the 15th International Conference on Microelectronics. IEEE, 2003. http://dx.doi.org/10.1109/icm.2003.238361.

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Kechichian, Al-Khalili, and Al-Khalili. "Optimizing CMOS combinatorial circuits using multiple attribute decision making techniques." In Proceedings of Canadian Conference on Electrical and Computer Engineering CCECE-94. IEEE, 1994. http://dx.doi.org/10.1109/ccece.1994.405810.

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Kitamichi, J., H. Kageyama, and N. Funabiki. "Formal verification method for combinatorial circuits at high level design." In Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198). IEEE, 1999. http://dx.doi.org/10.1109/aspdac.1999.760023.

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