Relevant bibliographies by topics / Common Boolean Logic (CBL)

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Academic literature on the topic 'Common Boolean Logic (CBL)'

Author: Grafiati
Published: 2 June 2025
Last updated: 10 July 2025

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Journal articles on the topic "Common Boolean Logic (CBL)"

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PinnikaVenkateswarlu and Kalpana Ragutla. "An Efficient SQRT Architecture of Carry Select Adder Design by HA and Common Boolean Logic." SSRG International Journal of Electronics and Communication Engineering 1, no. 8 (2014): 36–41. https://doi.org/10.5281/zenodo.33082.

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As we are aware that carry select adder is the fastest one amongdata processing element, on the other hand due to having pairs of ripple carry adder structure traditional carry select adder consumes more area. So proposed scheme is to developa low power and low area half adder based (CSLA) using simple using common Boolean logic (CBL), where it employs one half adders to perform the summation operation for the common Boolean logic (CBL) and carry zero respectively. Half adder and CBL have to be designed where half adder requires one XOR gate, one AND gate where CBL requires only one NOT as well as one OR gate. Here also architecures like 8-bit, 16-bit, 32-bit, 64-bit square root carry select adder (SQRT CSLA) is compared with regular one and modified also. The results show there is a great reduction in area and power consumption. Our work shows the better performance in case of minimized delay, less area and low power.The obtained results from the simulation clearly proves our proposed CSLAscheme is dominates the regular SQRT CSLA.
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Priya, Meshram, Mahendra Mithilesh, and Jawarkar Parag. "Designed Implementation of Modified Area Efficient Enhanced Square Root Carry Select Adder." International Journal for Research in Emerging Science and Technology 2, no. 5 (2015): 96–99. https://doi.org/10.5281/zenodo.33092.

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In the design of Integrated Circuits, area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. In this paper, an area-efficient carry select adder by sharing the common Boolean logic term (CBL) with BEC is proposed. After logic simplification and sharing partial circuit, only one XOR gate and one inverter gate in each summation operation as well as one AND gate and one inverter gate in each carry-out operation are needed. Based on this modification a new modified 32-Bit Square-root CSLA (SQRT CSLA) architecture has been developed. The modified architecture has been developed using Common Boolean Logic(CBL). The proposed architecture has reduced area, power and delay.
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Syed, Mustafaa M., M. Sathish, S. Nivedha, Magribatul Noora A. K. Mohammed, and Sifana T. Safrin. "Design of Carry Select Adder using BEC and Common Boolean Logic." Indian Journal of VLSI Design (IJVLSID) 1, no. 3 (2022): 5–9. https://doi.org/10.54105/ijvlsid.C1205.031322.

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Carry Select Adder (CSLA) is known to be the fastest adder among the conventional adder structure, which uses multiple narrow adders. CSLA has a great scope of reducing area, power consumption, speed and delay. From the structure of regular CSLA using RCA, it consumes large area and power. This proposed work uses a simple and dynamic Gate Level Implementation which reduces the area, delay, power and speed of the regular CSLA. Based on a modified CSLA using BEC the implementation of 8-b, 16-b, 32-b square root CSLA (SQRT CSLA) architecture have been developed. In order to reduce the area and power consumptionin a great way we proposed a design using binary to excess 1 converter (BEC). This paper proposes an dynamic method which replaces a BEC using Common Boolean Logic.
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Priya, Meshram, and Sarode Prof.Mamta. "Designing of Modified Area Efficient Square Root Carry Select Adder(SQRT CSLA)." Journal of Emerging Technologies and Innovative Research 2, no. 3 (2015): 530–33. https://doi.org/10.5281/zenodo.33087.

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In the design of Integrated Circuits, The necessity of portable systems is increasing an area occupancy plays a vital role. Square Root Carry Select Adder (SQRT CSLA) is one of the fastest adders which is used in this data-processing processor to perform fast arithmetic functions. In this paper, an area-efficient square root carry select adder(SQRT CSLA design) by sharing Common Boolean logic term (CBL) is proposed The modified architecture has been developed using Binary to Excess-1 converter (BEC). Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed by using CBl. The proposed design has reduced area as well as power,but in this we study only for area with a slight increase in the delay.
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Priya, Meshram, and Sarode Prof.Mamta. "Design of Modified Area Efficient Square Root Carry Select Adder (SQRT CSLA)." International Journal of Industrial Electronics and Electrical Engineering, no. 4 (June 17, 2015): 216–19. https://doi.org/10.5281/zenodo.33098.

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In the design of Integrated Circuits, The necessity of portable systems is increasing an area occupancy plays a vital role. Square Root Carry Select Adder (SQRT CSLA) is one of the fastest adders which is used in this data-processing processor to perform fast arithmetic functions. In this paper, an area-efficient square root carry select adder(SQRT CSLA design) by sharing Common Boolean logic term (CBL) is proposed The modified architecture has been developed using Binary to Excess-1 converter (BEC). Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed by using CBl. The proposed design has reduced area as well as power,but in this we study only for area with a slight increase in the delay.
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A., Mounika, and Srinivasa Reddy K. "Designing and Performance Evaluation of Carry Select Adder." International Journal of VLSI System Design and Communication systems 3, no. 5 (2015): 0754–57. https://doi.org/10.5281/zenodo.48670.

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In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSA) is one of the fastest adder in processor architectures. This paper presents a modified carry select adder(CSA) that operates at low power and proves more area and delay efficient. Validation of the logic is done through extensive simulations for measuring the power and delay. Simple and efficient gate level modification is used in order to reduce the area, delay and power of CSA.The result analysis shows that the proposed structure(CSA CBL) is better than the conventional CSA and CSA with BEC. 
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Saini, Vikas K., Shamim Akhter, and Tanuj Chauhan. "Implementation, Test Pattern Generation, and Comparative Analysis of Different Adder Circuits." VLSI Design 2016 (June 8, 2016): 1–8. http://dx.doi.org/10.1155/2016/1260879.

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Addition usually affects the overall performance of digital systems and an arithmetic function. Adders are most widely used in applications like multipliers, DSP (i.e., FFT, FIR, and IIR). In digital adders, the speed of addition is constrained by the time required to propagate a carry through the adder. Various techniques have been proposed to design fast adders. We have derived architectures for carry-select adder (CSA), Common Boolean Logic (CBL) based adders, ripple carry adder (RCA), and Carry Look-Ahead Adder (CLA) for 8-, 16-, 32-, and 64-bit length. In this work we have done comparative analysis of different types of adders in Synopsis Design Compiler using different standard cell libraries at 32/28 nm. Also, the designs are analyzed for the stuck at faults (s-a-0, s-a-1) using Synopsis TetraMAX.
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Wright, Adam, Skye Aaron, Allison B. McCoy, et al. "Algorithmic Detection of Boolean Logic Errors in Clinical Decision Support Statements." Applied Clinical Informatics 12, no. 01 (2021): 182–89. http://dx.doi.org/10.1055/s-0041-1722918.

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Abstract Objective Clinical decision support (CDS) can contribute to quality and safety. Prior work has shown that errors in CDS systems are common and can lead to unintended consequences. Many CDS systems use Boolean logic, which can be difficult for CDS analysts to specify accurately. We set out to determine the prevalence of certain types of Boolean logic errors in CDS statements. Methods Nine health care organizations extracted Boolean logic statements from their Epic electronic health record (EHR). We developed an open-source software tool, which implemented the Espresso logic minimization algorithm, to identify three classes of logic errors. Results Participating organizations submitted 260,698 logic statements, of which 44,890 were minimized by Espresso. We found errors in 209 of them. Every participating organization had at least two errors, and all organizations reported that they would act on the feedback. Discussion An automated algorithm can readily detect specific categories of Boolean CDS logic errors. These errors represent a minority of CDS errors, but very likely require correction to avoid patient safety issues. This process found only a few errors at each site, but the problem appears to be widespread, affecting all participating organizations. Conclusion Both CDS implementers and EHR vendors should consider implementing similar algorithms as part of the CDS authoring process to reduce the number of errors in their CDS interventions.
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De Nijs, Roderick Sebastiaan, Christian Landsiedel, Dirk Wollherr, and Martin Buss. "Quadratization and Roof Duality of Markov Logic Networks." Journal of Artificial Intelligence Research 55 (March 25, 2016): 685–714. http://dx.doi.org/10.1613/jair.5023.

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This article discusses the quadratization of Markov Logic Networks, which enables efficient approximate MAP computation by means of maximum flows. The procedure relies on a pseudo-Boolean representation of the model, and allows handling models of any order. The employed pseudo-Boolean representation can be used to identify problems that are guaranteed to be solvable in low polynomial-time. Results on common benchmark problems show that the proposed approach finds optimal assignments for most variables in excellent computational time and approximate solutions that match the quality of ILP-based solvers.
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Nandam, Krishna Sravani, K. Jamal, Anil Kumar Budati, Kiran Mannem, and Manchalla O. V. P. Kumar. "Design and analysis of Dadda multiplier with Common Boolean Logic." Materials Today: Proceedings 33 (2020): 4833–36. http://dx.doi.org/10.1016/j.matpr.2020.08.392.

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Books on the topic "Common Boolean Logic (CBL)"

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Dooley, Brendan, ed. The Continued Exercise of Reason. The MIT Press, 2018. http://dx.doi.org/10.7551/mitpress/9780262535007.001.0001.

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George Boole (1815–1864), remembered by history as the developer of an eponymous form of algebraic logic, can be considered a pioneer of the information age not only because of the application of Boolean logic to the design of switching circuits but also because of his contributions to the mass distribution of knowledge. In the classroom and the lecture hall, Boole interpreted recent discoveries and debates in a wide range of fields for a general audience. This collection of lectures, many never before published, offers insights into the early thinking of an innovative mathematician and intellectual polymath. Bertrand Russell claimed that “pure mathematics was discovered by Boole,” but before Boole joined a university faculty as professor of mathematics in 1849, advocacy for science and education occupied much of his time. He was deeply committed to the Victorian ideals of social improvement and cooperation, arguing that “the continued exercise of reason” joined all disciplines in a common endeavor. In these talks, Boole discusses the genius of Isaac Newton; ancient mythologies and forms of worship; the possibility of other inhabited planets in the universe; the virtues of free and open access to knowledge; the benefits of leisure; the quality of education; the origin of scientific knowledge; and the fellowship of intellectual culture. The lectures are accompanied by a substantive introduction that supplies biographical and historical context.
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Book chapters on the topic "Common Boolean Logic (CBL)"

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Dacík, Tomáš, Adam Rogalewicz, Tomáš Vojnar, and Florian Zuleger. "Deciding Boolean Separation Logic via Small Models." In Tools and Algorithms for the Construction and Analysis of Systems. Springer Nature Switzerland, 2024. http://dx.doi.org/10.1007/978-3-031-57246-3_11.

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AbstractWe present a novel decision procedure for a fragment of separation logic (SL) with arbitrary nesting of separating conjunctions with boolean conjunctions, disjunctions, and guarded negations together with a support for the most common variants of linked lists. Our method is based on a model-based translation to SMT for which we introduce several optimisations—the most important of them is based on bounding the size of predicate instantiations within models of larger formulae, which leads to a much more efficient translation of SL formulae to SMT. Through a series of experiments, we show that, on the frequently used symbolic heap fragment, our decision procedure is competitive with other existing approaches, and it can outperform them outside the symbolic heap fragment. Moreover, our decision procedure can also handle some formulae for which no decision procedure has been implemented so far.
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Jujjuru, Jaya Lakshmi, and Rajanbabu Mallavarapu. "Improved SQRT Architecture for Carry Select Adder Using Modified Common Boolean Logic." In Proceedings of 2nd International Conference on Micro-Electronics, Electromagnetics and Telecommunications. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-4280-5_36.

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Akshay, S., Eliyahu Basa, Supratik Chakraborty, and Dror Fried. "On Dependent Variables in Reactive Synthesis." In Tools and Algorithms for the Construction and Analysis of Systems. Springer Nature Switzerland, 2024. http://dx.doi.org/10.1007/978-3-031-57246-3_8.

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AbstractGiven a Linear Temporal Logic (LTL) formula over input and output variables, reactive synthesis requires us to design a deterministic Mealy machine that gives the values of outputs at every time step for every sequence of inputs, such that the LTL formula is satisfied. In this paper, we investigate the notion of dependent variables in the context of reactive synthesis. Inspired by successful pre-processing techniques in Boolean functional synthesis, we define dependent variables in reactive synthesis as output variables that are uniquely assigned, given an assignment to all other variables and the history so far. We describe an automata-based approach for finding a set of dependent variables. Using this, we show that dependent variables are surprisingly common in reactive synthesis benchmarks. Next, we develop a novel synthesis framework that exploits dependent variables to construct an overall synthesis solution. By implementing this framework using the widely used library , we show that reactive synthesis that exploits dependent variables can solve some problems beyond the reach of existing techniques. Furthermore, we observe that among benchmarks with dependent variables, if the count of non-dependent variables is low ($$\le 3$$ ≤ 3 in our experiments), our method outperforms state-of-the-art tools for synthesis.
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Nguyen Hien D. and Do Nhon V. "Intelligent Problem Solver in Education for Discrete Mathematics." In Frontiers in Artificial Intelligence and Applications. IOS Press, 2017. https://doi.org/10.3233/978-1-61499-800-6-21.

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A grand challenge for artificial intelligence in education is building the Intelligent Problem Solver (IPS) for Science Technology Engineering and Math (STEM) Education. The IPS system has to be able to solve the exercises of the course automatically. It has the following criteria: the knowledge base is sufficient, the program can solve the common exercises in the curriculum of the course based on the knowledge base, the solutions are readable, pedagogical and suitable for the learner's level. Discrete Mathematics is an important course for the undergrad technological curriculum at the university. In this course, knowledge about logic and Boolean algebra is the foundation of logical thinking, it helps students improve their skills in logical reasoning, solving the problems. There are many programs for solving problems in propositional logic and first-order logic; nevertheless, they cannot meet the requirements of a learning support system. In this paper, an IPS system in knowledge domain about logic and Boolean algebra has been proposed. This system satisfies the criteria of the STEM education. It helps students to understand the methods for solving basic and advanced problems: simplify the logical expression in propositional logic, reasoning checking, determine the value or the negative expression of of a logical expression in predicate logic, find the minimization expression of a Boolean function with parameter and non-parameter. In this system, the knowledge base about propositional logic, predicate logic and Boolean algebra at the university for undergraduates has been built based on knowledge model of operators. Via this knowledge base, the inference engine has been designed to solve the kinds of general problems in this knowledge domain. The program has been also tested by the students in University of Information Technology, VNU-HCM.
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Flarend, Alice, and Bob Hilborn. "Traditional Computing." In Quantum Computing: From Alice to Bob. Oxford University Press, 2022. http://dx.doi.org/10.1093/oso/9780192857972.003.0002.

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Alice and Bob explain the difference between classical (traditional) computing and quantum computing, deploying a gentle introduction to classical binary digits (bits) beginning with a brief history of the development of quantum mechanics and computer architecture. The abstract backbone of classical computing is logic gates, which represent changes to input bits under specific rules. These rules, governed by Boolean, logic can be summarized in truth tables, giving the output values for specific input values. The most common classical gates—NOT, AND, NAND, and XOR gates—are introduced. The vocabulary of classical computing provides the basis for understanding quantum computing.
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Kaufmann, Mareile. "Association." In Making Information Matter. Policy Press, 2023. http://dx.doi.org/10.1332/policypress/9781529233575.003.0005.

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Association has become a central aspect of surveillance and a key practice of making information matter. It is critical to any kind of profiling that we experience on an everyday basis. To associate is to join, to make a connection ‘in an interest, object, employment or purpose’ (Harper, nd). One of the most widespread ways of analysing information is indeed to make a connection between different datasets. In her work on data derivatives Louise Amoore speaks of an ‘ontology of association’ (2011: 27). This means that associating data is not just a knowledge practice, but it describes a specific way in which data materialize and come to exist together. The most common approach of associating different datasets with each other follow a Boolean logic (Kitchin, 2016), named after the mathematician George Boole. We know them as if-then rules, that is: when if is true, then is executed. By means of if-then instructions disaggregated data are associated ‘to derive a lively and alert new form of data derivative – a flag, map or score that will go on to live and act in the world’ (Amoore, 2011: 27). The aim of associative practices is to connect different sets of information and to derive patterns from them (Kaufmann, Egbert, and Leese, 2019). What is more, such patterns, again, are likely to be associated with actions that matter to society. Whether a pattern is considered meaningful and actionable depends on many aspects, not least those involved in associating. Association is a classic analytic practice, which is also used to process analogue information. With the rise of digital information, however, association has shifted in terms of reach and quality.
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Conference papers on the topic "Common Boolean Logic (CBL)"

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Manju, S., and V. Sornagopal. "An efficient SQRT architecture of Carry Select adder design by Common Boolean logic." In 2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT). IEEE, 2013. http://dx.doi.org/10.1109/icevent.2013.6496590.

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Console, Marco, Paolo Guagliardo, and Leonid Libkin. "Do We Need Many-valued Logics for Incomplete Information?" In Twenty-Eighth International Joint Conference on Artificial Intelligence {IJCAI-19}. International Joint Conferences on Artificial Intelligence Organization, 2019. http://dx.doi.org/10.24963/ijcai.2019/851.

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One of the most common scenarios of handling incomplete information occurs in relational databases. They describe incomplete knowledge with three truth values, using Kleene's logic for propositional formulae and a rather peculiar extension to predicate calculus. This design by a committee from several decades ago is now part of the standard adopted by vendors of database management systems. But is it really the right way to handle incompleteness in propositional and predicate logics? Our goal is to answer this question. Using an epistemic approach, we first characterize possible levels of partial knowledge about propositions, which leads to six truth values. We impose rationality conditions on the semantics of the connectives of the propositional logic, and prove that Kleene's logic is the maximal sublogic to which the standard optimization rules apply, thereby justifying this design choice. For extensions to predicate logic, however, we show that the additional truth values are not necessary: every many-valued extension of first-order logic over databases with incomplete information represented by null values is no more powerful than the usual two-valued logic with the standard Boolean interpretation of the connectives. We use this observation to analyze the logic underlying SQL query evaluation, and conclude that the many-valued extension for handling incompleteness does not add any expressiveness to it.
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Johnson, K. M., M. Handschy, W. T. Cathey, N. Clark, and D. Walba. "Polarization-Based Optical Parallel Logic Gates Using Ferroelectric Liquid Crystal Spatial Light Modulators." In Optical Computing. Optica Publishing Group, 1987. http://dx.doi.org/10.1364/optcomp.1987.tuc4.

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Optical computing systems offer an increased information processing rate by facilitating parallel computing architectures. Previous experience with electronic computers indicates that desired accuracy can be achieved only with digital computation. Since the simplest digital arithmetic is binary, most recent work on optical computing is focused on the construction of binary optical logic gates. Many practical implementations of such logic gates have been suggested; a recent review is given by Sawchuck and Strand [1]. Most previous schemes operate on light intensity, much in the way that electronic systems operate on voltage or current. Another natural optical scheme represents the two binary states with two orthogonal polarizations of light. The optical element necessary to implement this scheme is a device with two states, one of which passes light of a chosen polarization unchanged, and the other of which converts light of the chosen polarization to its orthogonal complement. Tsvetkov et al. [1] have described a practical implementation of this logic using the now common twisted nematic (TN) liquid crystal device, which has two voltage-selected states, one of which rotates the polarization direction of appropriately oriented linearly polarized light by 90° and the other of which has no rotary power. Another implementation would use any of the variable retardation effects such as the Pockels effect. One state of the device would be chosen to have zero retardation, and the other to have half-wave retardation. In addition to either passing unchanged or imparting 90° rotation to linearly polarized light, this scheme could also work by either passing unchanged or reversing the handedness of circularly polarized light. An advantage pointed out by Lohmann [3] that any implementation of polarization-based logic has over logics based on intensity is that no light is lost in the logical operation of inversion. In intensity-based logics, it is difficult to invert an already dark input, since light has to be "recreated"; polarization-based elements, as described above, can convert the light representing either logical state to the other, making easy the realization of any desired Boolean function.
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