Relevant bibliographies by topics / Common Mode Voltage (CMV)

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  1. Journal articles
  2. Dissertations / Theses
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  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Common Mode Voltage (CMV)'

Author: Grafiati
Published: 4 June 2021
Last updated: 6 September 2023

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Journal articles on the topic "Common Mode Voltage (CMV)"

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R. Linga, Swamy, and R. Somanatham. "Reduction of common mode voltage for cascaded 3-level inverter using SVPWM." i-manager’s Journal on Electrical Engineering 15, no. 4 (2022): 1. http://dx.doi.org/10.26634/jee.15.4.18626.

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The common mode voltage (CMV) generated by multilevel inverters can be reduced. This paper presents a Spacevector pulse width modulation (SVPWM) approach for cascaded 3-level inverters to reduce common mode voltage. Conventional 3-level pulse width modulated (PWM) inverters are widely known for producing high-frequency commonmode voltages with high dv/dt. Motor shaft voltages and bearing currents can be caused by common mode voltages. In this work, to reduce common mode voltage, partial CMV elimination technique is used. In this method the redundant states of 3-level inverter having CMV less than or equal to Vdc/6 are only used and the redundant states having CMV greater than Vdc/6 are avoided by implementing SVPWM, where Vdc is the input DC voltage of inverter. A simulation of an dc SVM technique to reduce common mode voltage is implemented. Bearing voltages, bearing currents and total harmonic distortion (THD) are evaluated in the performance analysis. The results will prove the reduction of CMV with the proposed technique compared to conventional SVPWM.
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Wei, Hongye, Xiuhe Wang, and Xinghua Wang. "Brushless DC Motor Common-mode Voltage Analysis." Journal of Physics: Conference Series 2452, no. 1 (March 1, 2023): 012015. http://dx.doi.org/10.1088/1742-6596/2452/1/012015.

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Abstract Brushless DC motors (BLDCMs) with their own performance of obvious advantages: good speed regulation performance and high efficiency. BLDCMs have continuously replaced brushed DC and induction motors in many competitive fields and obtained more extensive applications. The common-mode voltage (CMV) in the motor parasitic capacitance coupling in the motor shaft induces the shaft voltage. It then triggers the shaft current, resulting in electrical corrosion of the bearing. It is necessary to conduct a systematic scientific analysis of its CMV. For different modulation methods, the phase voltages under three conditions without PWM modulation, HPWM_LPWM modulation, and HPWM_LON modulation are studied, FFT, and then the CMV is analyzed. Then, the correctness of the analysis is verified by simulation analysis.
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Chaturvedi, Pradyumn, Shailendra Jain, and Pramod Agarwal. "Carrier-Based Common Mode Voltage Control Techniques in Three-Level Diode-Clamped Inverter." Advances in Power Electronics 2012 (September 19, 2012): 1–12. http://dx.doi.org/10.1155/2012/327157.

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Switching converters are used in electric drive applications to produce variable voltage, variable frequency supply which generates harmful large dv/dt and high-frequency common mode voltages (CMV). Multilevel inverters generate lower CMV as compared to conventional two-level inverters. This paper presents simple carrier-based technique to control the common mode voltages in multilevel inverters using different structures of sine-triangle comparison method such as phase disposition (PD), phase opposition disposition (POD) by adding common mode voltage offset signal to actual reference voltage signal. This paper also presented the method to optimize the magnitude of this offset signal to reduce CMV and total harmonic distortion in inverter output voltage. The presented techniques give comparable performance as obtained in complex space vector-based control strategy, in terms of number of commutations, magnitude, and rate of change of CMV and harmonic profile of inverter output voltage. Simulation and experimental results presented confirm the effectiveness of the proposed techniques to control the common mode voltages.
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Negesse, Belete Belayneh, Chang-Hwan Park, Seung-Hwan Lee, Seon-Woong Hwang, and Jang-Mok Kim. "Optimized Modulation Method for Common-Mode Voltage Reduction in H7 Inverter." Energies 14, no. 19 (October 7, 2021): 6409. http://dx.doi.org/10.3390/en14196409.

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The three-phase H7 inverter topology installs an additional power semiconductor switch to the positive or negative node of the DC-link for reducing the common-mode voltage (CMV) by disconnecting the inverter from the DC source during the zero-voltage vectors. The conventional CMV reduction method for the three-phase H7 inverter uses modified discontinuous pulse width modulation (MDPWM) and generates a switching signal for the additional switch using logical operations. However, the conventional method is unable to eliminate the CMV for the entire dwell time of the zero-voltage vectors. It only has the effect of reducing the CMV in a limited area of the space vector where the V7 zero voltage vector is applied. Therefore, this paper proposes an optimized modulation method that can reduce the CMV during the entire dwell time of zero-voltage vectors. The proposed method moves the switching patterns by adding an offset voltage to guarantee that only one kind of zero-voltage vector, V7, is applied in the system. It then turns off the seventh switch only during the zero-voltage vector to disconnect the inverter from the DC source. As a result, the CMV and the leakage current are attenuated for the entire dwell time of the zero-voltage vector. Simulation and experimental results confirm the validity of the proposed method.
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Liu, Haiming, Linfeng Huang, Cheng Lin, Yifu Ding, Yun Wang, and Shanhu Li. "Analysis of High-Frequency Common Mode Component Characteristics of Common Mode Peak Voltage Suppression Method for Indirect Matrix Converter." Energies 15, no. 11 (May 28, 2022): 3991. http://dx.doi.org/10.3390/en15113991.

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A variety of modulation strategies for suppressing output common-mode voltage (CMV) of indirect matrix converters (IMC) have been proposed, but most of them mainly reduce the peak of CMV by 42.3%. The frequency-domain characteristics of CMV have not been deeply analyzed. In order to improve the theory of frequency-domain characteristics of output common-mode voltage of IMC, this paper proposed a common-mode frequency domain analysis of five common-mode voltage peak suppression modulation methods for IMC. The common-mode voltage spectrum corresponding to the five modulation methods is obtained by the triple Fourier series, and the variation laws of the output common-mode components of the five modulation methods under different modulation indexes are compared and analyzed. By comparing and analyzing the low-frequency amplitude characteristics and high-frequency amplitude characteristics of five modulation methods, the suppression performance of the five modulation methods is evaluated. Finally, experiments verify the correctness of the theoretical analysis of the frequency domain characteristics of the output common-mode voltage of the indirect matrix converter.
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Wang, Fusheng, Sai Weng, Lizhong Ye, and Tao Chen. "A Novel Low Common-Mode Voltage Modulation Strategy for ANPC-5L Inverter." E3S Web of Conferences 185 (2020): 01015. http://dx.doi.org/10.1051/e3sconf/202018501015.

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In order to suppress the leakage current of the active neutral point clamed five-level (ANPC-5L) inverter, this paper proposes a novel low common-mode voltage (CMV) modulation strategy based on the space vector modulation thought. Only the 55 voltage vectors with low CMV amplitude instead of all 125 voltage vectors are utilized. The CMV amplitude is suppressed to one-twelfth of the DC bus voltage (Vdc). In the simplified five-level space vector diagram, “obtuse triangle” synthesis principle is used to control the CMV changes twice in each carrier cycle, and get lower output current total harmonic distortion (THD). According to the vector thought, a carrier implementation method based on zero sequence voltage injection and carrier splitting is proposed. This method simplifies the calculation and is easy to implement.Simulation results prove the correctness and feasibility of this low CMV modulation strategy.
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Zalhaf, Amr, Mazen Abdel-Salam, and Mahmoud Ahmed. "An Active Common-Mode Voltage Canceler for PWM Converters in Wind-Turbine Doubly-Fed Induction Generators." Energies 12, no. 4 (February 21, 2019): 691. http://dx.doi.org/10.3390/en12040691.

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Wind energy integration in power grids is increasing day by day to reduce the use of fossil fuels, and consequently greenhouse gas emissions. Using the pulse-width modulated (PWM) power converters in wind turbine generators, specifically in doubly-fed induction generators, results in generating a common-mode voltage (CMV). This common-mode voltage causes a flow of common-mode current (CMC) that leaks through the stray capacitances in the generator structure. These currents impose a voltage on the generator bearing which may deteriorate them. In the current work, an active common-mode voltage canceler (ACMVC) is developed to eliminate the CMV produced by a PWM converter. The ACMVC generates a compensating voltage at the converter terminals to eliminate the CMV with a subsequent reduction of the voltage stress on the generator bearing. This compensating voltage has the same amplitude as CMV, but opposite polarity. A simulation of the ACMVC model is performed using the PSCAD/EMTDC (Electromagnetic Transient Design and Control) software package. Results confirm the effectiveness of ACMVC in canceling not only the CMV but the CMC and bearing voltage as well. In addition, the relationship between the rise time of CMV and the peak value of CMC is investigated.
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Guo, Yujing, and Junhuai Zhang. "Modulation Technique Design of An Improved Zero Common Mode Voltage (CMV)." Journal of Physics: Conference Series 2563, no. 1 (August 1, 2023): 012020. http://dx.doi.org/10.1088/1742-6596/2563/1/012020.

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Abstract Voltage imbalance of neutral-point and CMV are hot issues in the research of three-level inverters. This paper first introduces the three-level topology of the neutral-point clamped (NPC) inverter. Aiming to eliminate CMV of three-level NPC and balance the voltage of the neutral point simultaneously, a virtual space vector pulse modulation (VSVPWM) strategy is proposed. Virtual voltage vectors of this strategy are composed of 3 medium vectors. The voltage of the neutral point is balanced since the average current of the neutral point is 0. Therefore, the balance index is introduced to redefine virtual voltage vectors, so the voltage of the neutral point can recover quickly when the capacitors’ voltage of the dc-link is imbalanced.
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Fernandez, Markel, Endika Robles, Iker Aretxabaleta, Iñigo Kortabarria, Jon Andreu, and José Luis Martín. "A 3D Reduced Common Mode Voltage PWM Algorithm for a Five-Phase Six-Leg Inverter." Machines 11, no. 5 (May 6, 2023): 532. http://dx.doi.org/10.3390/machines11050532.

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Neutral point voltage control converters (NPVCC) are being considered for AC drive applications, where their additional degree of freedom can be used for different purposes, such as fault tolerance or common mode voltage (CMV) reduction. For every PWM-driven converter, the CMV is an issue that must be considered since it can lead to shaft voltages between rotor and stator windings, generating bearing currents that accelerate bearing degradation, and can also produce a high level of electromagnetic interference (EMI). In light of these considerations, in this paper a three-dimensional reduced common mode voltage PWM (3D RCMV-PWM) technique is proposed which effectively reduces CMV in five-phase six-leg NPVCCs. The mathematical description of both the converter and the modulation technique, in space-vector and carrier-based approaches, is included. Furthermore, the simulation and experimental analysis validate the CMV reduction capability in addition to the good behaviour in terms of the efficiency and harmonic distortion of the proposed RCMV-PWM algorithm.
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Szymański, Jerzy Ryszard, and Marta Żurek-Mortka. "Ground Leakage Current Caused by Common-Mode Voltage of PWM inverter." Journal of Civil Engineering and Transport 1, no. 1 (January 31, 2020): 15–25. http://dx.doi.org/10.24136/tren.2019.002.

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In railway tractive vehicles, three-phase PWM (Pulse Width Modulation) inverters generate parasitic Differential-Mode Voltages (DMV) and Common-Mode Voltages (CMV). Parasitic voltages are a side effect of using the width modulation to shape the phase-to-phase inverter’s voltage. In this article, the authors present a mathematical description of the DM and CM voltages and carry out their spectral analysis. Based on the spectral harmonics analysis, the authors present a method for filtration of harmonics of DM and CM voltages aimed at limiting the capacitance parasitic currents: due to DM voltage – phase-to-phase parasitic current and CM voltage – ground parasitic currents. As the final result of the tests, almost complete elimination of leakage parasitic current form PE shock protection system was achieved.
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Dissertations / Theses on the topic "Common Mode Voltage (CMV)"

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Aziz, Mohd Junaidi Bin Abdul. "Cancellation of common mode voltage in current source buck rectifier." Thesis, University of Nottingham, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.493328.

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AC/AC power conversion is widely used to feed AC loads with variable voltage and/or variable frequency from a constant voltage constant frequency power grid or to connect critical loads to an unreliable power supply while delivering a very accurate sinusoidal and balanced voltage system of constant amplitude and frequency. The load specifications will clearly impose the requirements for the inverter stage of the power converter, while a wider range of choices are available for the rectifier. This research investigates the utilization of a buck-type current source rectifier as an active front-end stage of an AC/AC converter for applications that require adjustable DC-link voltage and where elimination of the low-frequency common mode voltage is vital.
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Un, Emre. "Common Mode Voltage And Current Reduction In Voltage Source Inverter Driven Three Phase Ac Motors." Master's thesis, METU, 2008. http://etd.lib.metu.edu.tr/upload/12609062/index.pdf.

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In this thesis various reduced common mode voltage (RCMV) pulse width modulation (PWM) techniques and active/passive common mode voltage (CMV) reduction methods for voltage source inverter driven three-phase AC motors are theoretically and practically investigated. A novel RCMV-PWM method, the near state PWM (NSPWM) method is proposed for operation at high modulation index. At low modulation index, a modified version of an existing RCMV-PWM method, AZSPWM1, termed as MAZSPWM, is proposed to mitigate the voltage reflection problem of the method. An optimum modulation algorithm combining NSPWM and MAZSPWM with seamless transition is proposed. The proposed RCMV-PWM methods significantly reduce CMV but they suppress common mode current (CMC) partially. Utilization of a common mode inductor together with RCMV-PWM methods is effective in suppressing the CMC. In the study, in addition to the CMV characteristics, various practical performance characteristics such as voltage linearity, inverter output current ripple, inverter DC-link current ripple, and output line-to-line voltage pulse pattern are also analyzed. The study involves analysis, computer simulations, and detailed laboratory experiments.
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Somogyi, Chad Alexander. "Common mode voltage mitigation strategies using PWM in neutral-point-clamped multilevel inverters." Thesis, Marquette University, 2015. http://pqdtopen.proquest.com/#viewpdf?dispub=1594317.

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Over the last several decades, there has been consistent growth in the research and development of multilevel voltage-source inverter-based adjustable speed motor drives (ASDs) as a result of low cost, high reliability power semiconductors. The three-level neutral-point-clamped (NPC) ASD is a popular multilevel inverter used in low and medium voltage applications because of its ability to produce lower levels of total harmonic distortion (THD) and withstand higher voltages while preserving the rated output power compared to two-level ASDs.

As with other voltage-source inverters, three-level NPC ASDs produce common-mode voltage (CMV) that can cause motor shaft voltages, bearing currents, and excess voltage stresses on motor windings, resulting in the deterioration of motor bearings and insulation. Furthermore, the CMV and resultant currents can generate electromagnetic interference that can hinder the operation of sensitive control electronics. In this thesis, three carrier-based, three-level pulse-width-modulation (PWM) strategies were investigated to examine the levels of CMV, common-mode current, and dv/dt produced by the three-level NPC ASD. Additionally, the effects that each PWM strategy has on the THD in the output waveforms, as well as the total switching and conduction losses were analyzed through software simulation programs using a resistive-inductive load over a range of modulation indices. The first of the three methods, in-phase disposition sub-harmonic PWM (PD-SPWM), was verified experimentally using a laboratory-scale, 7.5 kVA three-level NPC ASD prototype.

It was determined that PD-SPWM produced the highest CMV amplitude of one-third the dc bus voltage, but the lowest values of differential-mode dv/dt, THD, and drive losses. The second strategy, phase-opposition (PO)-SPWM, reduced the CMV amplitude to one-sixth the dc bus voltage, at the cost of higher THD and drive losses and a doubling of the differential-mode dv/dt. The final strategy, zero common-mode (ZCM)-SPWM, was modified (MZCM-SPWM) to accommodate IGBT dead-time by delaying the output voltage transitions based on the polarity of the output currents and the direction of the commanded voltage transitions. The MZCM-SPWM method nearly eliminated all CMV pulses while maintaining comparable levels of THD, but produced twice the switching losses compared to PD- and PO- SPWM, and twice the differential-mode dv/dt compared to PD-SPWM.

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Chen, Mingdeng. "Low-voltage, low-power circuits for data communication systems." Diss., Texas A&M University, 2003. http://hdl.handle.net/1969.1/1585.

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There are growing industrial demands for low-voltage supply and low-power consumption circuits and systems. This is especially true for very high integration level and very large scale integrated (VLSI) mixed-signal chips and system-on-a-chip. It is mainly due to the limited power dissipation within a small area and the costs related to the packaging and thermal management. In this research work, two low-voltage, low-power integrated circuits used for data communication systems are introduced. The first one is a high performance continuous-time linear phase filter with automatic frequency tuning. The filter can be used in hard disk driver systems and wired communication systems such as 1000Base-T transceivers. A pseudo-differential operational transconductance amplifier (OTA) based on transistors operating in triode region is used to achieve a large linear signal swing with low-voltage supplies. A common-mode (CM) control circuit that combines common-mode feedback (CMFB), common-mode feedforward (CMFF), and adaptive-bias has been proposed. With a 2.3V single supply, the filter’s total harmonic distortion is less than –44dB for a 2VPP differential input, which is due to the well controlled CM behavior. The ratio of the root mean square value of the ac signal to the power supply voltage is around 31%, which is much better than previous realizations. The second integrated circuit includes two LVDS drivers used for high-speed point-to-point links. By removing the stacked switches used in the conventional structures, both LVDS drivers can operate with ultra low-voltage supplies. Although the Double Current Sources (DCS) LVDS driver draws twice minimum static current as required by the signal swing, it is quite simple and achieves very high speed operation. The Switchable Current Sources (SCS) LVDS driver, by dynamically switching the current sources, draws minimum static current and reduces the power consumption by 60% compared to the previously reported LVDS drivers. Both LVDS drivers are compliant to the standards and operate at data rates up to gigabits-per-second.
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Vázquez, Guzmán Gerardo. "Common-mode voltage cancellation in single- and three-phase transformer-less PV power converters." Doctoral thesis, Universitat Politècnica de Catalunya, 2013. http://hdl.handle.net/10803/116821.

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Electrical Energy generation is an issue that is continuously cause of concern around the world. Many efforts have been done in this sense to cover the requirements of the constantly growing in the electrical energy demand. But not only the electrical energy demand is growing but also clean electrical energy demand. In this sense, many countries are taking advantage from the renewable energy generation systems, considering mainly wind and solar energy. Solar energy systems provide a high percentage of the total energy production, according with the latest report of the International Energy Agency (IEA) regarding Photovoltaic Power System Program (PVPS), the cumulative installed PV power at the end of 2009 it was around 20.3 GW out of which 6.188 GW were installed in 2009. From the total PV power installed in 2009, 6.113 are grid connected systems. The growing of the PV systems is due to the new technologies and developments that have permitted to reduce costs in the total design and installation of a PV source. As the major percentage of the total PV energy installed is from grid connected systems, this thesis work deals with the analysis and proposals in the transformerless grid-connected PV systems which can provide higher efficiencies regarding PV system with transformer. In this sense, when there is not transformer between the electrical grid and the power converter, a problem regarding leakage ground currents appears, this is the main issue in this thesis work. The main research task in this thesis work is to analyze and evaluate the operation of the different transformerless topologies presented in the bibliography and then to provide some solutions to minimize the leakage ground current phenomenon in order to comply with the standard requirements.
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Rankin, Paul Edward. "Modeling and Design of a SiC Zero Common-Mode Voltage Three-Level DC/DC Converter." Thesis, Virginia Tech, 2019. http://hdl.handle.net/10919/93176.

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As wide-bandgap devices continue to experience deeper penetration in commercial applications, there are still a number of factors which make the adoption of such technologies difficult. One of the most notable issues with the application of wide-bandgap technologies is meeting existing noise requirements and regulations. Due to the faster dv/dt and di/dt of SiC devices, more noise is generated in comparison to Si IGBTs. Therefore, in order to fully experience the benefits offered by this new technology, the noise must either be filtered or mitigated by other means. A survey of various DC/DC topologies was conducted in order to find a candidate for a battery interface in a UPS system. A three-level NPC topology was explored for its potential benefit in terms of noise, efficiency, and additional features. This converter topology was modeled, simulated, and a hardware prototype constructed for evaluation within a UPS system, although its uses are not limited to such applications. A UPS system is a good example of an application with strict noise requirements which must be fulfilled according to IEC standards. Based on a newly devised mode of operation, this converter was verified to produce no common-mode voltage under ideal conditions, and was able to provide a 6 dB reduction in common-mode voltage emissions in the UPS prototype. This was done while achieving a peak efficiency in excess of 99% with the ability to provide bidirectional power flow between the UPS and battery backup. The converter was verified to operate at the rated UPS conditions of 20 kW while converting between a total DC bus voltage of 800 V and a nominal battery voltage of 540 V.
Master of Science
As material advancements allow for the creation of devices with superior electrical characteristics compared to their predecessors, there are still a number of factors which cause these devices to see limited usage in commercial applications. These devices, typically referred to as wide-bandgap devices, include silicon carbide (SiC) transistors. These SiC devices allow for much faster switching speeds, greater efficiencies, and lower system volume compared to their silicon counterparts. However, due to the faster switching of these devices, there is more electromagnetic noise generated. In many applications, this noise must be filtered or otherwise mitigated in order to meet international standards for commercial use. Consequently, new converter topologies and configurations are necessary to provide the most benefit of the new wide-bandgap devices while still meeting the strict noise requirements. A survey of topologies was conducted and the modeling, design, and testing of one topology was performed for use in an uninterruptible power supply (UPS). This converter was able to provide a noticeable reduction in noise compared to standard topologies while still achieving very high efficiency at rated conditions. This converter was also verified to provide power bidirectionally—both when the UPS is charging the battery backup, and when the battery is supplying power to the load.
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Adabi, Firouzjaee Jafar. "Remediation strategies of shaft and common mode voltages in adjustable speed drive systems." Thesis, Queensland University of Technology, 2010. https://eprints.qut.edu.au/39293/1/Jafar_Adabi_Firouzjaeel_Thesis.pdf.

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AC motors are largely used in a wide range of modern systems, from household appliances to automated industry applications such as: ventilations systems, fans, pumps, conveyors and machine tool drives. Inverters are widely used in industrial and commercial applications due to the growing need for speed control in ASD systems. Fast switching transients and the common mode voltage, in interaction with parasitic capacitive couplings, may cause many unwanted problems in the ASD applications. These include shaft voltage and leakage currents. One of the inherent characteristics of Pulse Width Modulation (PWM) techniques is the generation of the common mode voltage, which is defined as the voltage between the electrical neutral of the inverter output and the ground. Shaft voltage can cause bearing currents when it exceeds the amount of breakdown voltage level of the thin lubricant film between the inner and outer rings of the bearing. This phenomenon is the main reason for early bearing failures. A rapid development in power switches technology has lead to a drastic decrement of switching rise and fall times. Because there is considerable capacitance between the stator windings and the frame, there can be a significant capacitive current (ground current escaping to earth through stray capacitors inside a motor) if the common mode voltage has high frequency components. This current leads to noises and Electromagnetic Interferences (EMI) issues in motor drive systems. These problems have been dealt with using a variety of methods which have been reported in the literature. However, cost and maintenance issues have prevented these methods from being widely accepted. Extra cost or rating of the inverter switches is usually the price to pay for such approaches. Thus, the determination of cost-effective techniques for shaft and common mode voltage reduction in ASD systems, with the focus on the first step of the design process, is the targeted scope of this thesis. An introduction to this research – including a description of the research problem, the literature review and an account of the research progress linking the research papers – is presented in Chapter 1. Electrical power generation from renewable energy sources, such as wind energy systems, has become a crucial issue because of environmental problems and a predicted future shortage of traditional energy sources. Thus, Chapter 2 focuses on the shaft voltage analysis of stator-fed induction generators (IG) and Doubly Fed Induction Generators DFIGs in wind turbine applications. This shaft voltage analysis includes: topologies, high frequency modelling, calculation and mitigation techniques. A back-to-back AC-DC-AC converter is investigated in terms of shaft voltage generation in a DFIG. Different topologies of LC filter placement are analysed in an effort to eliminate the shaft voltage. Different capacitive couplings exist in the motor/generator structure and any change in design parameters affects the capacitive couplings. Thus, an appropriate design for AC motors should lead to the smallest possible shaft voltage. Calculation of the shaft voltage based on different capacitive couplings, and an investigation of the effects of different design parameters are discussed in Chapter 3. This is achieved through 2-D and 3-D finite element simulation and experimental analysis. End-winding parameters of the motor are also effective factors in the calculation of the shaft voltage and have not been taken into account in previous reported studies. Calculation of the end-winding capacitances is rather complex because of the diversity of end winding shapes and the complexity of their geometry. A comprehensive analysis of these capacitances has been carried out with 3-D finite element simulations and experimental studies to determine their effective design parameters. These are documented in Chapter 4. Results of this analysis show that, by choosing appropriate design parameters, it is possible to decrease the shaft voltage and resultant bearing current in the primary stage of generator/motor design without using any additional active and passive filter-based techniques. The common mode voltage is defined by a switching pattern and, by using the appropriate pattern; the common mode voltage level can be controlled. Therefore, any PWM pattern which eliminates or minimizes the common mode voltage will be an effective shaft voltage reduction technique. Thus, common mode voltage reduction of a three-phase AC motor supplied with a single-phase diode rectifier is the focus of Chapter 5. The proposed strategy is mainly based on proper utilization of the zero vectors. Multilevel inverters are also used in ASD systems which have more voltage levels and switching states, and can provide more possibilities to reduce common mode voltage. A description of common mode voltage of multilevel inverters is investigated in Chapter 6. Chapter 7 investigates the elimination techniques of the shaft voltage in a DFIG based on the methods presented in the literature by the use of simulation results. However, it could be shown that every solution to reduce the shaft voltage in DFIG systems has its own characteristics, and these have to be taken into account in determining the most effective strategy. Calculation of the capacitive coupling and electric fields between the outer and inner races and the balls at different motor speeds in symmetrical and asymmetrical shaft and balls positions is discussed in Chapter 8. The analysis is carried out using finite element simulations to determine the conditions which will increase the probability of high rates of bearing failure due to current discharges through the balls and races.
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Wang, Xiaodan. "The EMI Filter Design for GaN HEMT Based Two-Level Voltage Source Inverter." The Ohio State University, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=osu152424286628544.

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Dimarino, Christina Marie. "Design and Validation of a High-Density 10 kV Silicon Carbide MOSFET Power Module with Reduced Electric Field Strength and Integrated Common-Mode Screen." Diss., Virginia Tech, 2019. http://hdl.handle.net/10919/86596.

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Electricity is the fastest-growing type of end-use energy consumption in the world, and its generation and usage trends are changing. Hence, the power electronics that control the flow and conversion of electrical energy are an important research area. Advanced power electronics with improved efficiency, power density, reliability, and functionality are critical in data center, transportation, motor drive, renewable energy, and grid applications, among others. Wide-bandgap power semiconductors are enabling power electronics to meet these growing demands, and have thus begun appearing in commercial products, such as traction and solar inverters. Looking ahead, even greater strides can be made in medium-voltage systems due to the development of silicon carbide power devices with voltage ratings exceeding 10 kV. The ability of these devices to switch higher voltages faster and with lower losses than existing semiconductor technologies will drastically reduce the size, weight, and complexity of medium-voltage systems. However, these devices also bring new challenges for designers. This dissertation will present a package for 10 kV silicon carbide power MOSFETs that addresses the enhanced electric fields, greater electromagnetic interference, worsened dynamic imbalance, and higher heat flux issues associated with the packaging of these unique devices. Specifically, due to the low and balanced parasitic inductances, the power module prototype is able to switch at record speeds of tens of nanoseconds with negligible ringing and voltage overshoot. An integrated common-mode current screen contains the current that is generated by these fast voltage transients within the power module, rather than flowing to the system ground. This screen connection simultaneously increases the partial discharge inception voltage by reducing the electric field strength at the triple point of the insulating ceramic substrate. Further, field-grading plates are used in the bus bar to reduce the electric field strength at the module terminations. The heat flux is addressed by employing direct-substrate, jet-impingement cooling. The cooler is integrated into the module housing for increased power density.
Ph. D.
Electricity is the fastest-growing type of end-use energy consumption in the world, and its generation and usage trends are changing. Hence, the power electronics that control the flow and conversion of electrical energy are an important research area. Advanced power electronics with improved efficiency, power density, reliability, and functionality are critical in data center, transportation, motor drive, renewable energy, and grid applications, among others. Wide-bandgap power semiconductors are enabling power electronics to meet these growing demands, and have thus begun appearing in commercial products, such as traction and solar inverters. Looking ahead, even greater strides can be made in medium-voltage systems due to the development of silicon carbide power devices with voltage ratings exceeding 10 kV. The ability of these devices to switch higher voltages faster and with lower losses than existing semiconductor technologies will drastically reduce the size, weight, and complexity of medium-voltage systems. However, these devices also bring new challenges for designers. This dissertation will present a package for 10 kV silicon carbide power MOSFETs that addresses the enhanced electric fields, greater electromagnetic interference, worsened dynamic imbalance, and higher heat flux issues associated with the packaging of these unique devices. Specifically, due to the low and balanced parasitic inductances, the power module prototype is able to switch at record speeds of tens of nanoseconds with negligible ringing and voltage overshoot. An integrated common-mode current screen contains the current that is generated by these fast voltage transients within the power module, rather than flowing to the system ground. This screen connection simultaneously increases the partial discharge inception voltage by reducing the electric field strength at the triple point of the insulating ceramic substrate. Further, field-grading plates are used in the bus bar to reduce the electric field strength at the module terminations. The heat flux is addressed by employing direct-substrate, jet-impingement cooling. The cooler is integrated into the module housing for increased power density.
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10

Yan, Ning. "High-frequency Current-transformer Based Auxiliary Power Supply for SiC-based Medium Voltage Converter Systems." Thesis, Virginia Tech, 2020. http://hdl.handle.net/10919/101507.

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Auxiliary power supply (APS) plays a key role in ensuring the safe operation of the main circuit elements including gate drivers, sensors, controllers, etc. in medium voltage (MV) silicon carbide (SiC)-based converter systems. Such a converter requires APS to have high insulation capability, low common-mode coupling capacitance (Ccm ), and high-power density. Furthermore, considering the lifetime and simplicity of the auxiliary power supply system design in the MV converter, partial discharge (PD) free and multi-load driving ability are the additional two factors that need to be addressed in the design. However, today’s state-of-the-art products have either low power rating or bulky designs, which does not satisfy the demands. To improve the current designs, this thesis presents a 1 MHz isolated APS design using gallium nitride (GaN) devices with MV insulation reinforcement. By adopting LCCL-LC resonant topology, the proposed APS is able to supply multiple loads simultaneously and realize zero voltage switching (ZVS) at any load conditions. Since high reliability under faulty load conditions is also an important feature for APS in MV converter, the secondary side circuit of APS is designed as a regulated stage. To achieve MV insulation (> 20 kV) as well as low Ccm value (< 5 pF), a current-based transformer with a single turn structure using MV insulation wire is designed. Furthermore, by introducing different insulated materials and shielding structures, the APS is capable to achieve different partial discharge inception voltages (PDIV). In this thesis, the transformer design, resonant converter design, and insulation strategies will be detailly explained and verified by experiment results. Overall, this proposed APS is capable to supply multiple loads simultaneously with a maximum power of 120 W for the sending side and 20 W for each receiving side in a compact form factor. ZVS can be realized regardless of load conditions. Based on different insulation materials, two different receiving sides were built. Both of them can achieve a breakdown voltage of over 20 kV. The air-insulated solution can achieve a PDIV of 6 kV with Ccm of 1.2 pF. The silicone-insulated solution can achieve a PDIV of 17 kV with Ccm of 3.9 pF.
M.S.
Recently, 10 kV silicon carbide (SiC) MOSFET receives strong attention for medium voltage applications. Asit can switch at very high speed, e.g. > 50 V/ns, the converter system can operate at higher switching frequency condition with very small switching losses compared to silicon (Si) IGBT [8]. However, the fast dv/dt noise also creates the common mode current via coupling capacitors distributed inside the converter system, thereby introducing lots of electromagnetic interference (EMI) issues. Such issues typically occur within the gate driver power supplies due to the high dv/dt noises across the input and output of the supply. Therefore, the ultra-small coupling capacitor (<5 pF) of a gate driver power supply is strongly desired.[37] To satisfy the APS demands for high power modular converter system, a solution is proposed in this thesis. This work investigates the design of 1 MHz isolated APS using gallium nitride (GaN) devices with medium voltage insulation reinforcement. By increasing switching frequency, the overall converter size could be reduced dramatically. To achieve a low Ccm value and medium voltage insulation of the system, a current-based transformer with a single turn on the sending side is designed. By adopting LCCL-LC resonant topology, a current source is formed as the output of sending side circuity, so it can drive multiple loads importantly with a maximum of 120 W. At the same time, ZVS can use realized with different load conditions. The receiving side is a regulated stage, so the output voltage can be easily adjusted and it can operate in a load fault condition. Different insulation solutions will be introduced and their effect on Ccm will be discussed. To further reduce Ccm, shielding will be introduced. Overall, this proposed APS can achieve a breakdown voltage of over 20 kV and PDIV up to 16.6 kV with Ccm<5 pF. Besides, multi-load driving ability is able to achieve with a maximum of 120 W. ZVS can be realized. In the end, the experiment results will be provided.
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Books on the topic "Common Mode Voltage (CMV)"

1

Ro, Yoonhyuk. Common-Mode and Power Supply Noise Rejection in Low Voltage Analog Circuits. Creative Media Partners, LLC, 2018.

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Ro, Yoonhyuk. Common-mode and Power Supply Noise Rejection in Low Voltage Analog Circuits. Dissertation Discovery Company, 2018.

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Book chapters on the topic "Common Mode Voltage (CMV)"

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Weik, Martin H. "maximum common-mode voltage." In Computer Science and Communications Dictionary, 987. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_11201.

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Weik, Martin H. "operating common-mode voltage." In Computer Science and Communications Dictionary, 1149. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_12841.

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Weik, Martin H. "maximum operating common-mode voltage." In Computer Science and Communications Dictionary, 988. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_11213.

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Zhao, Le, Fang Chen, Mao Guo, Xuchuan Jing, and Youhua Jiang. "The Voltage Fluctuation Strategy of MMC Submodule Injected with Common Mode Voltage and Circulation." In Advances in Intelligent Automation and Soft Computing, 455–62. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-81007-8_51.

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Salmi, Tarak, Mounir Bouzguenda, Adel Gastli, and Ahmed Masmoudi. "Review of Common-Mode Voltage in Transformerless Inverter Topologies for PV Systems." In Sustainability in Energy and Buildings, 589–96. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-27509-8_49.

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Umashankar, Subramaniam, Vishnu Kalaiselvan Arun Shankar, Padmanaban Sanjeevikumar, and K. Harini. "Common-Mode Voltage Regulation of Three-Phase SVPWM-Based three-Level NPC Inverter." In Advances in Power Systems and Energy Management, 367–76. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-4394-9_37.

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Guzinski, Jaroslaw. "Common-Mode Voltage and Bearing Currents in PWM Inverters: Causes, Effects and Prevention." In Power Electronics for Renewable Energy Systems, Transportation and Industrial Applications, 664–94. Chichester, UK: John Wiley & Sons, Ltd, 2014. http://dx.doi.org/10.1002/9781118755525.ch21.

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Feng, Congqi, Wu Liao, Sheng Huang, Zexing Chen, Ge Liang, and Yu Liu. "Model Prediction Control with Common Mode Voltage Suppression for Dual Three-Phase PMSM." In Lecture Notes in Electrical Engineering, 434–45. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-1532-1_46.

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Ma, Yafei, Dong Jiang, and Zicheng Liu. "Common Mode Voltage Cancellation Method of PMSM Based on NPC Three Level Inverter." In The proceedings of the 10th Frontier Academic Forum of Electrical Engineering (FAFEE2022), 1051–59. Singapore: Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-3404-1_93.

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Ma, Yafei, Dong Jiang, and Zicheng Liu. "Common Mode Voltage Cancellation Method of PMSM Based on NPC Three Level Inverter." In The proceedings of the 10th Frontier Academic Forum of Electrical Engineering (FAFEE2022), 1051–59. Singapore: Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-3404-1_93.

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Conference papers on the topic "Common Mode Voltage (CMV)"

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Behera, Partha sarathi, G. Vivek, and Mukti Barai. "Common Mode Voltage (CMV) in Three level NPC VSI using Advanced Bus clamping methods:A Study." In 2018 International Conference on Recent Innovations in Electrical, Electronics & Communication Engineering (ICRIEECE). IEEE, 2018. http://dx.doi.org/10.1109/icrieece44171.2018.9009220.

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Wang Nan, Gao Penglu, Zhang Lina, Li Xuekun, Jia Yujian, Yu Zhanpeng, and Zhao Pengfei. "Research and simulation on minimized common-mode voltage SVPWM modulation algorithm for voltage source rectifier." In 2016 International Conference on Condition Monitoring and Diagnosis (CMD). IEEE, 2016. http://dx.doi.org/10.1109/cmd.2016.7757850.

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Fan Yue, P. W. Wheeler, and J. C. Clare. "Common-mode voltage in matrix converters." In 4th IET International Conference on Power Electronics, Machines and Drives (PEMD 2008). IEE, 2008. http://dx.doi.org/10.1049/cp:20080572.

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Jiang, Dong, and Zewei Shen. "Paralleled inverters with zero common-mode voltage." In 2016 IEEE Energy Conversion Congress and Exposition (ECCE). IEEE, 2016. http://dx.doi.org/10.1109/ecce.2016.7855330.

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Xie, Lihong, Xinbo Ruan, Haonan Zhu, and Yu-Kang Lo. "Common-Mode Noise Reduction in Phase-Shifted Full-Bridge Converter by Common-Mode Voltage Cancellation." In 2020 IEEE 9th International Power Electronics and Motion Control Conference (IPEMC2020-ECCE Asia). IEEE, 2020. http://dx.doi.org/10.1109/ipemc-ecceasia48364.2020.9367740.

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Jadhav, Aniruddha V., and P. V. Kapoor. "Reduction of common mode voltage using multilevel inverter." In 2016 International Conference on Energy Efficient Technologies for Sustainability (ICEETS). IEEE, 2016. http://dx.doi.org/10.1109/iceets.2016.7583822.

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Ray-Lee Lin, Jhen-Yuan Guo, and Chih-Ming Chang. "Study of common-mode voltage measurements for IEC62684." In 2013 IEEE Industry Applications Society Annual Meeting. IEEE, 2013. http://dx.doi.org/10.1109/ias.2013.6682606.

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Nicolae, Cojan, Cracan Arcadie, and Cojan Radu. "Test buffer with extended common mode input voltage." In Melecon 2010 - 2010 15th IEEE Mediterranean Electrotechnical Conference. IEEE, 2010. http://dx.doi.org/10.1109/melcon.2010.5476002.

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Tallam, Rangarajan M., Carlos D. Rodriguez Valdez, Russel J. Kerkman, Gary L. Skibinski, and Richard A. Lukaszewski. "Common-mode voltage reduction for regenerative AC drives." In 2012 IEEE Energy Conversion Congress and Exposition (ECCE). IEEE, 2012. http://dx.doi.org/10.1109/ecce.2012.6342499.

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Noroozi, N., M. R. Zolghadri, and M. Yaghoubi. "Reduced common-mode voltage in Z-Source Inverters." In 2017 8th Power Electronics, Drive Systems & Technologies Conference (PEDSTC). IEEE, 2017. http://dx.doi.org/10.1109/pedstc.2017.7910361.

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