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Journal articles on the topic 'Compact architecture'

Author: Grafiati

Published: 4 June 2021

Last updated: 13 February 2022

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1

Dvorak, Vojtech, Marek Bohrn, Lukas Fujcik, Jiri Haze, Vilem Kledrowetz, and Michal Pavlik. "Architecture of Compact Electrochemical Measurement Instrument." IFAC-PapersOnLine 49, no. 25 (2016): 159–63. http://dx.doi.org/10.1016/j.ifacol.2016.12.027.

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Yasir, Ning Wu, and Xiaoqiang Zhang. "Compact Hardware Implementations of MISTY1 Block Cipher." Journal of Circuits, Systems and Computers 27, no. 03 (2017): 1850037. http://dx.doi.org/10.1142/s0218126618500378.

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This paper proposes compact hardware implementations of 64-bit NESSIE proposed MISTY1 block cipher for area constrained and low power ASIC applications. The architectures comprise only one round MISTY1 block cipher algorithm having optimized FO/FI function by re-utilizing S9/S7 substitution functions. A focus is also made on efficient logic implementations of S9 and S7 substitution functions using common sub-expression elimination (CSE) and parallel AND/XOR gates hierarchy. The proposed architecture 1 generates extended key with independent FI function and is suitable for MISTY1 8-rounds imple

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3

Zhang, Jeff (Jun), Parul Raj, Shuayb Zarar, Amol Ambardekar, and Siddharth Garg. "CompAct." ACM Transactions on Embedded Computing Systems 18, no. 5s (2019): 1–24. http://dx.doi.org/10.1145/3358178.

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4

Wu, Xuan, Shuyin Liang, and David H. Byrne. "Architectural Components of Compact Growth Habits in Diploid Roses." HortTechnology 29, no. 5 (2019): 629–33. http://dx.doi.org/10.21273/horttech04343-19.

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Criteria to determine the horticultural quality of ornamental plants include plant architecture, flower characteristics, and resistance to biotic and abiotic stresses. The architecture of a rose (Rosa sp.) bush is linked to flower yield and ornamental value. The Texas A&M University (TAMU) Rose Breeding and Genetics program has the objective of developing garden rose cultivars that flower heavily and exhibit a compact full shape. To determine which architectural traits are key for the development of this desired shape, five rose seedlings with a desirable compact growth habit and five with

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Pyrgas, Lampros, and Paris Kitsos. "Compact Hardware Architectures of Enocoro-128v2 Stream Cipher for Constrained Embedded Devices." Electronics 9, no. 9 (2020): 1505. http://dx.doi.org/10.3390/electronics9091505.

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Lightweight cryptography is a vital and fast growing field in today’s world where billions of constrained devices interact with each other. In this paper, two novel compact architectures of the Enocoro-128v2 stream cipher are presented. The Enocoro-128v2 is part of the ISO/IEC 29192-3 standard. The first architecture has an 8-bit datapath while the second one has a 4-bit datapath. The proposed architectures were implemented on the BASYS3 board (Artix 7 XC7A35T) using the VERILOG hardware description language. The hardware implementation of the proposed 8-bit architecture runs at a 189 MHz cloc

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Crescentini, M., M. Tartagni, H. Morgan, and P. A. Traverso. "A compact low-noise broadband digital picoammeter architecture." Measurement 100 (March 2017): 194–204. http://dx.doi.org/10.1016/j.measurement.2016.12.040.

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7

Raghunath, Raghu K. J., Hashem Farrokh, Nagi Naganathan, et al. "Compact carry-save multiplier architecture and its applications." Computer Standards & Interfaces 20, no. 6-7 (1999): 442. http://dx.doi.org/10.1016/s0920-5489(99)90912-1.

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8

Saeed, Samah Mohamed Ahmed, and Ozgur Sinanoglu. "Expedited-compact architecture for average scan power reduction." IEEE Design & Test 30, no. 3 (2013): 25–33. http://dx.doi.org/10.1109/mdt.2012.2213793.

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9

Liu, Tian, and Carol Livermore. "A compact architecture for passively-switched energy harvesters." Journal of Physics: Conference Series 660 (December 10, 2015): 012090. http://dx.doi.org/10.1088/1742-6596/660/1/012090.

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Chard, S. P., and M. J. Damzen. "Compact architecture for power scaling bounce geometry lasers." Optics Express 17, no. 4 (2009): 2218. http://dx.doi.org/10.1364/oe.17.002218.

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11

Kong, Jia Hao, Li-Minn Ang, and Kah Phooi Seng. "A Very Compact AES-SPIHT Selective Encryption Computer Architecture Design with Improved S-Box." Journal of Engineering 2013 (2013): 1–26. http://dx.doi.org/10.1155/2013/785126.

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The “S-box” algorithm is a key component in the Advanced Encryption Standard (AES) due to its nonlinear property. Various implementation approaches have been researched and discussed meeting stringent application goals (such as low power, high throughput, low area), but the ultimate goal for many researchers is to find a compact and small hardware footprint for the S-box circuit. In this paper, we present our version of minimized S-box with two separate proposals and improvements in the overall gate count. The compact S-box is adopted with a compact and optimum processor architecture specifica

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Chancan, Marvin, Luis Hernandez-Nunez, Ajay Narendra, Andrew B. Barron, and Michael Milford. "A Hybrid Compact Neural Architecture for Visual Place Recognition." IEEE Robotics and Automation Letters 5, no. 2 (2020): 993–1000. http://dx.doi.org/10.1109/lra.2020.2967324.

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13

Petrosyan, Artur, Alexey Voskoboynikov, Natalia Slioussar, Mikhail Sinkin, and Alexey Ossadtchi. "Compact and Interpretable Architecture for Speech Decoding From iEEG." International Journal of Psychophysiology 168 (October 2021): S195. http://dx.doi.org/10.1016/j.ijpsycho.2021.07.531.

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14

García-Fernández, María, Guillermo Álvarez-Narciandi, Yuri Álvarez López, and Fernando Las-Heras Andrés. "Analysis and Validation of a Hybrid Forward-Looking Down-Looking Ground Penetrating Radar Architecture." Remote Sensing 13, no. 6 (2021): 1206. http://dx.doi.org/10.3390/rs13061206.

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Ground Penetrating Radar (GPR) has proved to be a successful technique for the detection of landmines and Improvised Explosive Devices (IEDs) buried in the ground. In the last years, novel architectures for safe and fast detection, such as those based on GPR systems onboard Unmanned Aerial Vehicles (UAVs), have been proposed. Furthermore, improvements in GPR hardware and signal processing techniques have resulted in a more efficient detection. This contribution presents an experimental validation of a hybrid Forward-Looking–Down-Looking GPR architecture. The main goal of this architecture is t

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JEON, YONG-SUNG, YOUNG-JIN KIM, and DONG-HO LEE. "A COMPACT MEMORY-FREE ARCHITECTURE FOR THE AES ALGORITHM USING RESOURCE SHARING METHODS." Journal of Circuits, Systems and Computers 19, no. 05 (2010): 1109–30. http://dx.doi.org/10.1142/s0218126610006633.

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This paper presents a resource-shared 8-bit (RS8) architecture for the AES algorithm, which aims at compacting the hardware architecture and allows hardware resources to be shared efficiently between encryption and decryption without using a memory. The RS8 architecture only requires one combined S-box/S-1-box for encryption, decryption and key expansion. The RS8 architecture implements the multiplicative inverse in the composite field GF((24)2) with resource sharing methods. In addition, the number of XOR gates used by the proposed combined MixColumns/InvMixColumns module is less than half th

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16

Ragonese, Egidio, Alessandro Parisi, Nunzio Spina, and Giuseppe Palmisano. "Compact Galvanically Isolated Architectures for Low-Power DC-DC Converters with Data Transmission." Electronics 10, no. 19 (2021): 2328. http://dx.doi.org/10.3390/electronics10192328.

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This paper reviews state-of-the-art architectures for galvanically isolated DC-DC converters with data transmission for low-power applications. Such applications do not have stringent requirements, in terms of power efficiency, but ask for very compact, highly integrated implementations. To this aim, architecture simplicity is crucial, especially when data transmission and/or output power regulation are required. Since the bottleneck of galvanically isolated systems is the isolation device (i.e., typically a stacked thick oxide or polyimide transformer), the reduction of the number of isolated

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IIDA, Masahiro, Motoki AMAGASAKI, Yasuhiro OKAMOTO, Qian ZHAO, and Toshinori SUEYOSHI. "COGRE: A Novel Compact Logic Cell Architecture for Area Minimization." IEICE Transactions on Information and Systems E95-D, no. 2 (2012): 294–302. http://dx.doi.org/10.1587/transinf.e95.d.294.

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Silva, Rodrigo Martins da, Luiza de Macedo Mourelle, and Nadia Nedjah. "Compact yet efficient hardware architecture for multilayer-perceptron neural networks." Sba: Controle & Automação Sociedade Brasileira de Automatica 22, no. 6 (2011): 647–63. http://dx.doi.org/10.1590/s0103-17592011000600010.

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There are several neural network implementations using either software, hardware-based or a hardware/software co-design. This work proposes a hardware architecture to implement an artificial neural network (ANN), whose topology is the multilayer perceptron (MLP). In this paper, we explore the parallelism of neural networks and allow on-thefly changes of the number of inputs, number of layers and number of neurons per layer of the net. This reconfigurability characteristic permits that any application of ANNs may be implemented using the proposed hardware. In order to reduce the processing time

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19

YAMAMOTO, Dai, Jun YAJIMA, and Kouichi ITOH. "Compact Architecture for ASIC Implementation of the MISTY1 Block Cipher." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E93-A, no. 1 (2010): 3–12. http://dx.doi.org/10.1587/transfun.e93.a.3.

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20

Chou, E. Y., B. J. Sheu, and M. Y. Wang. "A compact neural network for VLSI PRML detectors: scalable architecture." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 45, no. 6 (1998): 709–19. http://dx.doi.org/10.1109/82.686690.

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21

Blanco Granja, Angel, Bruno Cimoli, Sebastián Rodríguez, et al. "Compact high-speed envelope detector architecture for ultra-wideband communications." Microwave and Optical Technology Letters 60, no. 4 (2018): 936–41. http://dx.doi.org/10.1002/mop.31068.

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22

O'Shea, M., R. Duane, D. McCarthy, K. G. McCarthy, A. Concannon, and A. Mathewson. "Compact model development for a new nonvolatile memory cell architecture." IEEE Transactions on Semiconductor Manufacturing 16, no. 2 (2003): 215–19. http://dx.doi.org/10.1109/tsm.2003.811576.

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23

Yang, Kang, Tianzhang Xing, Yang Liu, et al. "cDeepArch: A Compact Deep Neural Network Architecture for Mobile Sensing." IEEE/ACM Transactions on Networking 27, no. 5 (2019): 2043–55. http://dx.doi.org/10.1109/tnet.2019.2936939.

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24

Saldana, Griselda, and Miguel Arias Estrada. "Compact FPGA-based systolic array architecture suitable for vision systems." International Journal of High Performance Systems Architecture 1, no. 2 (2007): 124. http://dx.doi.org/10.1504/ijhpsa.2007.015398.

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25

Desmet, Siel, Emmy Dhooghe, Ellen De Keyser, Johan Van Huylenbroeck, and Danny Geelen. "Compact shoot architecture of Osteospermum fruticosum transformed with Rhizobium rhizogenes." Plant Cell Reports 40, no. 9 (2021): 1665–78. http://dx.doi.org/10.1007/s00299-021-02719-z.

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26

Ezzeddine, Hussein, Stéphane Bila, Serge Verdeyme, et al. "Compact diplexers and triplexers implemented with dual-mode cavities." International Journal of Microwave and Wireless Technologies 4, no. 1 (2011): 51–58. http://dx.doi.org/10.1017/s1759078711000869.

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In this paper, the design of compact diplexers and triplexers with dual-mode cavities is presented. Such devices are composed of coupled resonators without additional waveguide element, leading to a more compact architecture. Two topologies of compact diplexers are implemented and compared to a standard manifold diplexer. A hardware prototype is fabricated and measured for experimental verification. A compact triplexer is finally introduced for extending the concept to more than three ports.

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27

Siswoyo, Bambang, M. Agus Choiron, Yudy Surya Irawan, and I. N. G. Wardana. "System Architecture and FPGA Embedding of Compact Fuzzy Logic Controller for Arm Robot Joints." Applied Mechanics and Materials 493 (January 2014): 480–85. http://dx.doi.org/10.4028/www.scientific.net/amm.493.480.

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This research is about the system architecture for embedding of the Compact Fuzzy Logic Controller (Compact-FLC) into the FPGA with a minimal need in device resource. This exciting research is to minimize the FPGA resources needed to build Compact-FLC based on FPGA for controlling each joint of arm robots manipulator. Compact-FLC results of this research have been used in the XILINX Spartan 3 XC3S1000 FPGA.The Compact-FLC has been applied with satisfactory results as Servo Controller for one joint of arm robot manipulator which the results showed that the controller achieved a process speed of

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28

Della Sala, Riccardo, Davide Bellizia, and Giuseppe Scotti. "A Novel Ultra-Compact FPGA PUF: The DD-PUF." Cryptography 5, no. 3 (2021): 23. http://dx.doi.org/10.3390/cryptography5030023.

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In this paper, we present a novel ultra-compact Physical Unclonable Function (PUF) architecture and its FPGA implementation. The proposed Delay Difference PUF (DD-PUF) is the most dense FPGA-compatible PUF ever reported in the literature, allowing the implementation of two PUF bits in a single slice and provides very good values for all the most important figures of merit. The architecture of the proposed PUF exploits the delay difference between two nominally identical signal paths and the metastability features of D-Latches with an asynchronous reset input. The DD-PUF has been implemented on

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29

Soniya, Sandeep Paul, and Lotika Singh. "Application and Need-Based Architecture Design of Deep Neural Networks." International Journal of Pattern Recognition and Artificial Intelligence 34, no. 13 (2020): 2052014. http://dx.doi.org/10.1142/s021800142052014x.

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This paper applies a hybrid evolutionary approach to a convolutional neural network (CNN) and determines the number of layers and filters based on the application and user need. It integrates compact genetic algorithm with stochastic gradient descent (SGD) for simultaneously evolving structure and parameters of the CNN. It defines an effectual string representation for combining structure and parameters of the CNN. The compact genetic algorithm helps in the evolution of network structure by optimizing the number of convolutional layers and number of filters in each convolutional layer. At the

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30

de Paulo, Vitor, and Cristinel Ababei. "3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans." International Journal of Reconfigurable Computing 2010 (2010): 1–12. http://dx.doi.org/10.1155/2010/603059.

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We propose new 3D 2-layer and 3-layer NoC architectures that utilizehomogeneousregular mesh networks on a separate layer and one or twoheterogeneousfloorplanning layers. These architectures combine the benefits of compact heterogeneous floorplans and of regular mesh networks. To demonstrate these benefits, a design methodology that integrates floorplanning, routers assignment, and cycle-accurate NoC simulation is proposed. The implementation of the NoC on a separate layer offers an additional area that may be utilized to improve the network performance by increasing the number of virtual chann

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31

Johnson, Bonnie J. "Codes of ethics, public values, and what public servants offer the bureaucratic compac." International Journal of Organization Theory & Behavior 17, no. 4 (2017): 459–97. http://dx.doi.org/10.1108/ijotb-17-04-2014-b004.

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Over 100 years ago, the bureaucratic compact and five professions were established: city/county management, city planning, civil engineering, landscape architecture, and architecture. In exchange for merit employment and independence from politics, these professions offered expertise and related values. To understand those values and changes in the compact from the 1900s to today, codes of ethics from the five professions were examined. Anticipated changes were a movement from traditional public values to business values including New Public Management. However, findings show traditional value

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32

Kolesnikova, M. N., Ye V. Bakhtina, and V. P. Timonin. "Libraries architecture and design as a subject of teaching at the library-information faculty." Bibliosphere, no. 2 (June 30, 2016): 3–6. http://dx.doi.org/10.20913/1815-3186-2016-2-3-6.

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The article represents major issues of academic subject «Libraries architecture and design» at the library-information faculty of Saint-Petersburg State Institute of Culture. Authors examine the course evolution, present its scientific and educational base (dissertations, monographs, textbooks, etc.). Goals and objectives of the discipline are identified. The represented structure of the discipline contains the following sections: 1. Introduction to architecture. Theoretical bases of architectural design; 2. Architecture and planning of library buildings. 3. Functional division of libraries’ r

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33

Mai, Huy Van, Olivier Bichler, Christian Gamrat, Yannick Viero, Fabien Alibart, and Dominique Vuillaume. "A Compact Device Model for Nanoparticle-organic Memory Transistor’s Characterization." Communications in Physics 28, no. 3 (2018): 191. http://dx.doi.org/10.15625/0868-3166/28/3/12359.

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Neuromorphic electronic devices have recently been a candidate for new computing architecture associated with innovative nanotechnologies. A report of the characterization of Nanoparticle organic memory transistor (NOMFET) introduced a similar behavior to a biological spiking synapse in neural networks. In this paper, a refinement model based on the extracted parameters including a hybrid NOMFET/CMOS neuromorphic computing circuit and architecture of synapse to neuron interface by characterizing transistor -- memory and the temporal dynamic function is presented. A compact EKV model refinement

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34

Santana, Edson P., Raimundo C. S. Freire, and Ana Isabela A. Cunha. "A Compact Low-Power CMOS Analog FSR Model-Based CNN." Journal of Integrated Circuits and Systems 7, no. 1 (2012): 72–80. http://dx.doi.org/10.29292/jics.v7i1.357.

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A compact low-power CMOS analog circuit implementation of a Cellular Neural Network based on Full Signal Range Model (FSR-CNN) is presented. The required operations in cell definition are synapses (multiplication and summation) and saturated integration. In each synapse, a new multiplier architecture is employed with voltage and current inputs and a current output, which allows sharing building blocks and using continuously programmable weight values. Feasibility and usefulness of the proposed FSR cell architecture is verified through the simulation of two applications: the connected component

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35

Ando, Kaori, and Rebecca Grumet. "Evaluation of Altered Cucumber Plant Architecture as a Means to Reduce Phytophthora capsici Disease Incidence on Cucumber Fruit." Journal of the American Society for Horticultural Science 131, no. 4 (2006): 491–98. http://dx.doi.org/10.21273/jashs.131.4.491.

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Fruit rot induced by Phytophthora capsici Leonian is an increasingly serious disease affecting pickling cucumber (Cucumis sativus L.) production in many parts of the United States. The absence of genetically resistant cultivars and rapid development of fungicide resistance makes it imperative to develop integrated disease management strategies. Cucumber fruit which come in direct contact with the soil-borne pathogen are usually located under the canopy where moist and warm conditions favor disease development. We sought to examine whether variations in plant architecture traits that influence

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36

Bronselaer, Antoon, Christophe Billiet, Robin De Mol, Joachim Nielandt, and Guy De Tré. "Compact representations of temporal databases." VLDB Journal 28, no. 4 (2018): 473–96. http://dx.doi.org/10.1007/s00778-018-0535-4.

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37

Šenk, Peter. "Aesthetics of sustainability: Capsule architecture in the city and in nature." SAJ - Serbian Architectural Journal 11, no. 3 (2019): 463–72. http://dx.doi.org/10.5937/saj1903463q.

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Architecture of minimum dwellings has been a hot topic recently. When minimum dwellings are compact, well-equipped, connected to the network, structurally, functionally and visually recognized as one thing, temporary and mobile or transportable, they may be designated as capsule architecture. Temporary by nature, these small dwellings, shelters, redesigned container units, special technological structures, parasites and other manifestations of the capsules concept encompass the logic of technological facilities with a distinct architectural expression. At the same time, it is a manifestation o

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38

Demigny, Didier, Ridha Djemal, and Rached Tourki. "A Real-time Image Processing with a Compact FPGA-based Architecture." Journal of Computer Science 1, no. 2 (2005): 207–14. http://dx.doi.org/10.3844/jcssp.2005.207.214.

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Pande, Sandeep, Fearghal Morgan, Seamus Cawley, et al. "Modular Neural Tile Architecture for Compact Embedded Hardware Spiking Neural Network." Neural Processing Letters 38, no. 2 (2013): 131–53. http://dx.doi.org/10.1007/s11063-012-9274-5.

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40

Araneda, Luis, and Miguel Figueroa. "A compact hardware architecture for digital image stabilization using integral projections." Microprocessors and Microsystems 39, no. 8 (2015): 987–97. http://dx.doi.org/10.1016/j.micpro.2015.04.003.

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41

Shoaran, Mahsa, Mahdad Hosseini Kamal, Claudio Pollo, Pierre Vandergheynst, and Alexandre Schmid. "Compact Low-Power Cortical Recording Architecture for Compressive Multichannel Data Acquisition." IEEE Transactions on Biomedical Circuits and Systems 8, no. 6 (2014): 857–70. http://dx.doi.org/10.1109/tbcas.2014.2304582.

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Stan, Mircea R., Kevin Skadron, Marco Barcella, Wei Huang, Karthik Sankaranarayanan, and Sivakumar Velusamy. "HotSpot: a dynamic compact thermal model at the processor-architecture level." Microelectronics Journal 34, no. 12 (2003): 1153–65. http://dx.doi.org/10.1016/s0026-2692(03)00206-4.

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Hua Li and Jianzhou Li. "A new compact dual-core architecture for AES encryption and decryption." Canadian Journal of Electrical and Computer Engineering 33, no. 3/4 (2008): 209–13. http://dx.doi.org/10.1109/cjece.2008.4721627.

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Torres-Huitzil, César, and Miguel Arias-Estrada. "Real-time image processing with a compact FPGA-based systolic architecture." Real-Time Imaging 10, no. 3 (2004): 177–87. http://dx.doi.org/10.1016/j.rti.2004.06.001.

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San, Ismail, and Nuray At. "Compact Keccak Hardware Architecture for Data Integrity and Authentication on FPGAs." Information Security Journal: A Global Perspective 21, no. 5 (2012): 231–42. http://dx.doi.org/10.1080/19393555.2012.660678.

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Giraud-Guille, M. M. "Twisted plywood architecture of collagen fibrils in human compact bone osteons." Calcified Tissue International 42, no. 3 (1988): 167–80. http://dx.doi.org/10.1007/bf02556330.

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Yang, Yi-Hua, and Viktor Prasanna. "High-Performance and Compact Architecture for Regular Expression Matching on FPGA." IEEE Transactions on Computers 61, no. 7 (2012): 1013–25. http://dx.doi.org/10.1109/tc.2011.129.

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Rodríguez-Flores, Luis, Miguel Morales-Sandoval, René Cumplido, Claudia Feregrino-Uribe, and Ignacio Algredo-Badillo. "Compact FPGA hardware architecture for public key encryption in embedded devices." PLOS ONE 13, no. 1 (2018): e0190939. http://dx.doi.org/10.1371/journal.pone.0190939.

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Yeh, Chih-Wei Stanley, and S. Simon Wong. "Compact One-Transistor-N-RRAM Array Architecture for Advanced CMOS Technology." IEEE Journal of Solid-State Circuits 50, no. 5 (2015): 1299–309. http://dx.doi.org/10.1109/jssc.2015.2402217.

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Baker, Jonathan M., Casey Duckering, David I. Schuster, and Frederic T. Chong. "Virtual Logical Qubits: A Compact Architecture for Fault-Tolerant Quantum Computing." IEEE Micro 41, no. 3 (2021): 95–101. http://dx.doi.org/10.1109/mm.2021.3072789.

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