Relevant bibliographies by topics / Comparator

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Comparator'

Author: Grafiati
Published: 4 June 2021
Last updated: 25 July 2025

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Journal articles on the topic "Comparator"

1

Song, Bangyu, and Yi Zhao. "A comparative research of innovative comparators." Journal of Physics: Conference Series 2221, no. 1 (2022): 012021. http://dx.doi.org/10.1088/1742-6596/2221/1/012021.

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Abstract This paper studies four novel design comparators and gives a detailed analysis and summary of them. edge-pursuit comparator (EPC) improved energy efficiency and noise over conventional comparators by a circuit loop consisting of numbers of delay units. The triple-tail fully dynamic comparator minimizes the comparator’s total delay time and enhances the sample rate. The dynamic bias architecture of the double-tail latch-type comparator can provide a relatively high voltage gain while ensuring a low power consumption by stabilizing the static operating point. It also has advantages over
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Sharmila Vallem. "Design of a High speed Low Low-Power Latched Comparator for Medical Implants." Communications on Applied Nonlinear Analysis 32, no. 8s (2025): 87–104. https://doi.org/10.52783/cana.v32.3610.

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The latched dynamic comparator is a fundamental component in all ADC architectures. Thermal effects, kickback, and offset voltage influence it. The kickback noise of the latched comparator in medical implant ADCs can impact the resolution, precision, and settling period. The current study examines a latching comparator that aims to reduce kickback noise. This research presents a low-power latched comparator for medical implants functioning at 1 V. This investigation implements a comparator utilising the sampling switching approach. This method successfully minimises kick-back noise and clockin
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Sun, Yuan. "A brief review on novel comparator design." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 418–27. http://dx.doi.org/10.54097/hset.v27i.3785.

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This paper reviewed three different kinds of comparators to show their respective advantage range. The Dynamic-bias comparator extends its pre-amplifier part with a capacitor and has a smaller power with a smaller input referred noise than Elzakker’s comparator but has a higher delay. The Quad high-speed comparator introduced the Quad into the comparator’s latch part. It has a lower delay and also make the calculation of the output voltage easier for it only depends on the skew factor. The low-power dynamic bias has a cross-couple device on its pre-amplifier part which slows down the discharge
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Du, Chengze. "Performance analysis of high-speed, low-power comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 292–301. http://dx.doi.org/10.54097/hset.v27i.3770.

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This article mainly presents a summary of development of dynamic comparators and the optimization to conventional comparator in recent years. By comparing the design of two different comparators, the design method of less power consumption, high speed or small delay, and low input referred noise can be concluded. The Dynamic comparator is designed to have small delay and less power consumption compared with two-stage comparator. The dynamic-bias comparator spends less power for operation the circuit compared with double-tail comparator. The FIA comparator operates under the controlling of logi
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Li, Yichen. "The Performance analysis of Low-Power High-Speed comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 72–82. http://dx.doi.org/10.54097/hset.v27i.3723.

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Comparators are the essential block for planning high-speed analog and. This paper presents three inventive designs of the comparators in recent years. First, innovated by classic two-stage comparator, the comparator with a transconductance-enhanced latching stage is suitable for low-power, high-speed operation. Second, triple-latch feed-forward(TLFF) fully dynamic comparator guarantees the maximum possible gain and speed for a specific power across the entire input range. Finally, the comparator with a dynamic floating inverter maximizes efficiency by reusing the current.
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Liu, Yuchuan. "An Review of Dynamic CMOS Comparators." Highlights in Science, Engineering and Technology 44 (April 13, 2023): 113–20. http://dx.doi.org/10.54097/hset.v44i.7273.

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CMOS dynamic comparators contributes a major role on the implementation of mixed signal successive approximation register (SAR) type of analog to digital converters (ADC). High precision, dynamic range, low voltage operation, high speed, low power consumption, reliability and offset voltage are the critical factors to be considered while designing CMOS dynamic comparators. This paper reviewed the performance of some popular dynamic CMOS comparators such as StrongARM latch comparator, double- tail dynamic-latched comparator, dynamic bias comparator and triple stage somparator.
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Palsodkar, Prachi, Pravin Dakhole, and Prasanna Palsodkar. "Reduced Complexity Linearity Improved Threshold Quantized Comparator Based Flash ADC." Journal of Circuits, Systems and Computers 26, no. 03 (2016): 1750046. http://dx.doi.org/10.1142/s0218126617500463.

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This paper describes a standard cell-based new approach of comparator design for flash ADC. Conventional flash ADC comparator consumes up to 60% of the power due to resistive ladder network and analog comparators. Threshold inverter quantized (TIQ) comparators reported earlier have improved speed and provide low-power, low-voltage operation. But they need feature size variation and have non-linearity issues. Here, a new standard cell comparator is proposed which retains all advantages of TIQ comparator and provides improved linearity with reduced hardware complexity. A 4-bit ADC designed using
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Du, Qinghang. "Analysis and comparison of several types of low-power, low offset comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 120–32. http://dx.doi.org/10.54097/hset.v27i.3728.

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This paper studies several excellent works of comparator constructions of comparators and compares them with the Double-tail latch-type comparator. Based on the Elzakker comparator, the comparator with a dynamic bias reduced the use of energy by partly discharging the preamplifier's output nodes. Edge-Pursuit Comparator(EPC) demonstrates a new approach to reducing energy consumption by automatic energy optimization. Apart from the designs that optimize energy consumption. Low-Noise Self-Calibrating Dynamic Comparator provides the low-offset feature while in relatively low power consumption.
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Fan, Jiangfeng. "Performance Analysis of Low-Power CMOS Dynamic Comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 62–71. http://dx.doi.org/10.54097/hset.v27i.3722.

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This paper studies four structures of CMOS dynamic comparators introduced in recent years. Based on conventional double-tail comparator, a comparator with a tail capacitor prevents output nodes of preamplifier from completely discharging to reduce energy consumption. Another comparator with a cross-coupled pairs achieves the same purpose of the first design. A comparator adds a floating inverter amplifier (FIA) to realize both dynamic bias and current reuse, achieve low energy consumption and be insensitive to the VCM. The triple-latch feed-forward (TLFF) comparator decreases delay conspicuous
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Takai, Nobukazu, Kento Suzuki, and Yoshiki Sugawara. "Comparator Synthesis Using Distributed Genetic Algorithm and HSPICE Optimization." Applied Mechanics and Materials 888 (February 2019): 17–28. http://dx.doi.org/10.4028/www.scientific.net/amm.888.17.

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In this paper, we propose an automatic design method that determines comparator topology and satisfies desired specification of the comparator by combining distributed genetic algorithm and HSPICE optimization function.In the comparator synthesis, new topology is created using known circuit topology information.After creating the topology, optimization of element values of the comparator is executed by distributed genetic algorithm and HSPICE optimization.As a target value example, specification of HA163S02 is used.Simulation results indicate that the proposed method can design the comparator
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Dissertations / Theses on the topic "Comparator"

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Sepke, Todd C. (Todd Christopher) 1975. "Comparator design and analysis for comparator-based switched-capacitor circuits." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/38925.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2007.<br>Includes bibliographical references (p. 177-182).<br>The design of high gain, wide dynamic range op-amps for switched-capacitor circuits has become increasingly challenging with the migration of designs to scaled CMOS technologies. The reduced power supply voltages and the low intrinsic device gain in scaled technologies offset some of the benefits of the reduced device parasitics. An alternative comparator-based switched-capacitor circuit (CBSC) technique that elimin
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Servoss, Thomas G. "Infrared symbolic scene comparator /." Online version of thesis, 1993. http://hdl.handle.net/1850/11725.

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Johnston, William F. (William Francis). "A low dispersion 2-GHz comparator." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/36781.

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Thesis (M. Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.<br>Includes bibliographical references (leaves 40-41).<br>A low dispersion 2-GHz comparator is an essential part of the latest automated VLSI tester by Teradyne Inc. With each new and faster CMOS logic VLSI microchips, faster and more precise comparators are needed to verify that the static discipline is being met on the many pins of the integrated circuit. As the error in the comparator is lowered, the VLSI production yield is greatly increased because of greater certa
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Shar, Ahmad. "Design of a High-Speed CMOS Comparator." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-10446.

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<p>This master thesis describes the design of high-speed latched comparator with 6-bit resolution, full scale voltage of 1.6 V and the sampling frequency of 250 MHz. The comparator is designed in a 0.35 9m CMOS process with a supply voltage of 3.3 V.</p><p>The comparator is designed for time-interleaved bandpass sigma-delta ADC.</p><p>Due to the nature of the target application, it should be possible to turn off the components to avoid the static power consumption. The comparator of this design implements the turn off technique when it is not in use. The settling time of the comparator is less
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Ouyang, Jingwen M. Eng Massachusetts Institute of Technology. "A Comparator-Based Switched-Capacitor delta sigma modulator." Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/61249.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2010.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (p. 81).<br>Comparator-Based Switched-Capacitor (CBSC) is a relatively new topology that replaces op-amps in sampled-data systems with a comparator and a set of current mirrors. CBSC is expected to lower power consumption, and to avoid several delicate tradeoffs of op-amp circuits. In this paper, the original single-ended CBSC block is extended to a fully differential version. The differenti
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Aizad, Noor. "Design and implementation of comparator for sigma delta modulator." Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-6965.

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<p>Comparator is the main building block in an ADC architecture. Main purpose of the comparator is to compare a signal with a reference signal and produce an output depending on whether the input signal is greater or smaller than reference. Many architectures for comparators exist for various purposes. In this thesis, Latched comparator architecture is used for sigma delta modulator. This particular design has two main characteristics that are very important for sigma delta application. First characteristic is the cancellation of memory effect which increases the speed and reliability of the s
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Wong, Kim Fai. "Speed enhancement techniques for comparator-based switched-capacitor circuits." Thesis, University of Macau, 2010. http://umaclib3.umac.mo/record=b2493500.

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Fiorenza, John Kenneth 1977. "A comparator-based switched-capacitor pipelined analog-to-digital converter." Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/40312.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Includes bibliographical references (leaves 112-115).<br>A new comparator-based switched-capacitor(CBSC) technique is proposed that eliminates the need for high gain op-amps in switched-capacitor circuits. The CBSC technique replaces the op-amp in switched-capacitor circuits with a comparator and a current source. Compared to op-
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Torgersen, Svend Bjarne. "Comparator-Based Switched-Capacitor Integrator for use in Delta-Sigma Modulator." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2009. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-9045.

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<p>A comparator-based switched capacitor integrator for use in a Delta Sigma ADC has been designed. Basic theory about comparator-based circuits has been presented and design equations have been developed. The integrator had a targeted performance of a bandwidth of 1.5MHz with a SNR of 80dB. Due to the lack of a complete modulator feedback system, the integrator was simulated in open-loop. For the integrator not to saturate in open-loop, an overshoot calibration circuit was enabled during the simulation. This resulted in a severe deterioration of the integrated signal. The results are therefor
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Abreu, Fernandes Miguel Filipe. "SQUID based cryogenic current comparator for measuring low-intensity antiproton beams." Thesis, University of Liverpool, 2018. http://livrepository.liverpool.ac.uk/3022531/.

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In the low-energy Antiproton Decelerator (AD) and the Extra Low ENergy Antiproton (ELENA) rings at CERN, an absolute measurement of the beam intensity is essential to commission and troubleshoot the different accelerator systems, to measure the operational efficiency, and to provide calibration information for the different experiments using the antiproton (p) beam. Both the AD and ELENA are synchrotron decelerators, operating with both bunched and debunched - Direct Current (DC) - beams. The beam currents can be smaller than 100 nA, and the total number of circulating particles is of the orde
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Books on the topic "Comparator"

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N, Miljanic P., ed. The current comparator. P. Peregrinus, 1988.

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Conklin & deDecker Associates., ed. The aircraft comparator. Conklin & deDecker Associates, 2001.

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Conklin & deDecker Associates., ed. The aircraft comparator. Conklin & deDecker Associates, 2003.

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Conklin & deDecker Associates., ed. The aircraft comparator. Conklin & deDecker Associates, 1998.

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Associates, Al Conklin, ed. The aircraft comparator. Conklin & deDecker Associates, 2001.

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Helen, Rodgers, Leading Learning Project, and Learning and Skills Research Centre., eds. International comparator contexts. Learning and Skills Research Centre, 2003.

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Associates, Al Conklin, ed. The Aircraft comparator. A. Conklin Associates, 1990.

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Associates, Al Conklin, ed. The Aircraft comparator. Al Conklin Associates, 1990.

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Conklin & deDecker Associates., ed. The aircraft comparator. Conklin & deDecker Associates, 2003.

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Conklin & deDecker Associates., ed. The aircraft comparator. Conklin & deDecker Associates, 2001.

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Book chapters on the topic "Comparator"

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Li, Weitao, Fule Li, and Zhihua Wang. "Comparator." In Analog Circuits and Signal Processing. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-62012-1_5.

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Nahler, Gerhard. "comparator product." In Dictionary of Pharmaceutical Medicine. Springer Vienna, 2009. http://dx.doi.org/10.1007/978-3-211-89836-9_250.

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Brooks, Jessica X., and Kathleen E. Cullen. "Comparator, The." In Encyclopedia of Animal Cognition and Behavior. Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-319-55065-7_217.

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El-Chammas, Manar. "Comparator Design." In Synthesis Lectures on Engineering, Science, and Technology. Springer International Publishing, 2023. http://dx.doi.org/10.1007/978-3-031-29700-7_5.

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Brooks, Jessica X., and Kathleen E. Cullen. "The Comparator." In Encyclopedia of Animal Cognition and Behavior. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-319-47829-6_217-1.

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Xie, Weidi, Li Shen, and Andrew Zisserman. "Comparator Networks." In Computer Vision – ECCV 2018. Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-030-01252-6_48.

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Cruz, Carlos Oliveira, and Rui Cunha Marques. "Public Sector Comparator." In Infrastructure Public-Private Partnerships. Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-36910-0_2.

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Dunbar, Norman. "Analog Comparator Interrupt." In Arduino Interrupts. Apress, 2023. http://dx.doi.org/10.1007/978-1-4842-9714-8_11.

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Fischer, Michael C. "Comparator Design and Effects." In Comparators. Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-95742-1_7.

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Soram, Julia, and Shyam Akashe. "A Relative Investigation of TIQ Comparator and Dynamic Latched Comparator." In Springer Proceedings in Physics. Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2367-2_37.

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Conference papers on the topic "Comparator"

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Shringi, Shivangi, Srinivasu Bodapati, and Srikant Srinivasan. "Magnetic Skyrmions Based One-Bit Comparator." In 2024 IEEE International Symposium on Smart Electronic Systems (iSES). IEEE, 2024. https://doi.org/10.1109/ises63344.2024.00022.

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R, Pooja C., Panwala Fenil Chetankumar, and Ravi H. K. "Design and Analysis of Two-Stage Comparator with Telescopic Amplifier and Dynamic Comparator for Low-Voltage Applications." In 2025 3rd International Conference on Smart Systems for applications in Electrical Sciences (ICSSES). IEEE, 2025. https://doi.org/10.1109/icsses64899.2025.11009925.

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Rogozin, A., and V. Shapkin. "DIGITAL COMPARATORS." In CHALLENGING ISSUES IN SYSTEMS MODELING AND PROCESSES. FSBE Institution of Higher Education Voronezh State University of Forestry and Technologies named after G.F. Morozov, 2025. https://doi.org/10.58168/cismp2024_689-693.

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In the course of the work, an analysis of the chosen topic was carried out. Theoretical materials on the chosen topic were studied. The comparator structure was determined and a truth table was compiled. A one-bit and two-bit comparator were compared, as well as the properties of comparators were revealed.
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Prusten, Mark J., and Arthur F. Gmitro. "An Optical Flash Analog to Digital Converter." In Optical Computing. Optica Publishing Group, 1995. http://dx.doi.org/10.1364/optcomp.1995.otue3.

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Fast analog-to-digital (A/D) converters are important in a number of applications. Several systems have been proposed for fast A/D converters using optical technology1-4. The most common types of converters are the successive approximation and Flash converters. In a Flash converter there is a separate comparator for each possible output bit code. Each comparator is biased with a reference level that is a specific increment of the full scale value. Since comparators in a Flash converter operate in parallel, this architecture is intrinsically fast. However, as the accuracy requirements increase,
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Molaei, Hasan, and Khosrow Hajsadeghi. "A low-power comparator-reduced flash ADC using dynamic comparators." In 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS). IEEE, 2017. http://dx.doi.org/10.1109/icecs.2017.8292010.

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Fedorov, V., and M. Melnikova. "COMPARATORS AND THEIR APPLICATIONS." In CHALLENGING ISSUES IN SYSTEMS MODELING AND PROCESSES. FSBE Institution of Higher Education Voronezh State University of Forestry and Technologies named after G.F. Morozov, 2025. https://doi.org/10.58168/cismp2024_598-600.

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In this work studying comparator and its applications, a complex analysis of chosen subject was conducted. Corresponding literature was studied, articles about comparators in the Internet also were studied.
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Janest, Alain, Marcel Fanjeaux, and Georges Negro. "Infrared radiance comparator." In Recent Advances in Sensors, Radiometric Calibration, and Processing of Remotely Sensed Data. SPIE, 1993. http://dx.doi.org/10.1117/12.161541.

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Iwasinska, Olga, and Marek Dobosz. "Interferometric dimension comparator." In Optoelectronic and Electronic Sensors V, edited by Wlodzimierz Kalita. SPIE, 2003. http://dx.doi.org/10.1117/12.517122.

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Izquierdo, Daniel, Carlos Faverio, Agustin Garcia, Leonardo Trigo, and Daniel Slomovitz. "Inductance comparator bridge." In 2014 Conference on Precision Electromagnetic Measurements (CPEM 2014). IEEE, 2014. http://dx.doi.org/10.1109/cpem.2014.6898511.

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Wulff, Carsten, and Trond Ytterdal. "CBSC pipelined ADC with comparator preset, and comparator delay compensation." In 2009 NORCHIP. IEEE, 2009. http://dx.doi.org/10.1109/norchp.2009.5397846.

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Reports on the topic "Comparator"

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Thompson, Greg. Virtual Optical Comparator. Office of Scientific and Technical Information (OSTI), 2008. http://dx.doi.org/10.2172/952474.

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Christian, David, and Bruce Merkel. Postamp/Comparator Hardware Description HN100. Office of Scientific and Technical Information (OSTI), 1991. http://dx.doi.org/10.2172/2478269.

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Christian, David, and Merle Haldeman. Draft Specification Postamp / Comparator (Discriminator) Version 2.3. Office of Scientific and Technical Information (OSTI), 1989. https://doi.org/10.2172/2479782.

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De la Barra, Mauricio. Public Sector Comparator: Aplicación Hospital Salvador Infante Chile. Inter-American Development Bank, 2009. http://dx.doi.org/10.18235/0007574.

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Presentación expuesta durante el "Primer Encuentro Técnico de capacitación en materia de estructuración de Proyectos de Asociación Público Privada", llevado a cabo en México, febrero, 2008. "El "Public Sector Comparator" es una estimación del costo, ajustado por riesgo, en el evento que el proyecto se financia, implementa y es propiedad del Estado; en este caso se aplica este método al Hospital Salvador Infante Chile.
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Assouline, Maurice. Computer Assisted Ada Validation Tools (C.A.V.). Comparator and Analyzer. Defense Technical Information Center, 1988. http://dx.doi.org/10.21236/ada213661.

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Gassner, G. Investigations of Digital Levels at the SLAC Vertical Comparator. Office of Scientific and Technical Information (OSTI), 2005. http://dx.doi.org/10.2172/839706.

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Soundararajan, Sathveeka Kasthurisamy, Ibrahim Almufarrij, Reza Hoseinabadi, and Kevin J. Munro. GAZE EVOKED TINNITUS (GET) POST SURGICAL EXCISION OF VESTIBULAR SCHWANNOMA: A SCOPING REVIEW PROTOCOL. INPLASY - International Platform of Registered Systematic Review and Meta-analysis Protocols, 2023. http://dx.doi.org/10.37766/inplasy2023.4.0024.

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Review question / Objective: The aim of this scoping review is to collate and catalogue what has been published on the symptom of Gaze-Evoked Tinnitus (GET) after surgery for removal of a Vestibular Schwannoma (VS). Eligibility criteria: The inclusion and exclusion criteria for studies are reported in accordance with Participant, Intervention, Comparator and Outcome (PICO) elements. Participant or Population: Adults with GET after surgical removal of VS. Intervention: The Intervention of interest will be surgical removal of the VS. Comparator: There will be no comparator. Outcomes: All outcome
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Glintborg, Dorte, Naja Due Kolster, Pernille Ravn, and Marianne Skovsager Andersen. Prospective risk of type 2 diabetes in normal weight women with polycystic ovary syndrome. INPLASY - International Platform of Registered Systematic Review and Meta-analysis Protocols, 2022. http://dx.doi.org/10.37766/inplasy2022.6.0070.

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Review question / Objective: To investigate the risk for type 2 diabetes (T2D) in normal weight women with PCOS. The following PECOs (Population, Exposure, Comparator and Outcome) were included: Population: Pre- and postmenopausal women. Exposure: PCOS Comparator: Healthy control or background population. Outcome: T2D. Condition being studied: Polycystic ovary syndrome (PCOS) is a common endocrine disorder of reproductive-aged women with a prevalence of 15–20%. Polycystic ovary syndrome (PCOS) is most often defined according to the Rotterdam criteria, which include irregular ovulation, biochem
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Chang, Y. May, and Summerfield B. Tillett. Calibration procedures for inductance standards using a commercial impedance meter as a comparator. National Institute of Standards and Technology, 1990. http://dx.doi.org/10.6028/nist.ir.4466.

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Lucon, Enrico. Dimensional Inspection of Charpy Indirect Verification Specimens by Means of a Digital Optical Comparator. National Institute of Standards and Technology, 2024. http://dx.doi.org/10.6028/nist.ir.8507.

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