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Dissertations / Theses on the topic 'Comparator'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 July 2025

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1

Sepke, Todd C. (Todd Christopher) 1975. "Comparator design and analysis for comparator-based switched-capacitor circuits." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/38925.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2007.<br>Includes bibliographical references (p. 177-182).<br>The design of high gain, wide dynamic range op-amps for switched-capacitor circuits has become increasingly challenging with the migration of designs to scaled CMOS technologies. The reduced power supply voltages and the low intrinsic device gain in scaled technologies offset some of the benefits of the reduced device parasitics. An alternative comparator-based switched-capacitor circuit (CBSC) technique that elimin

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2

Servoss, Thomas G. "Infrared symbolic scene comparator /." Online version of thesis, 1993. http://hdl.handle.net/1850/11725.

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3

Johnston, William F. (William Francis). "A low dispersion 2-GHz comparator." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/36781.

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Thesis (M. Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.<br>Includes bibliographical references (leaves 40-41).<br>A low dispersion 2-GHz comparator is an essential part of the latest automated VLSI tester by Teradyne Inc. With each new and faster CMOS logic VLSI microchips, faster and more precise comparators are needed to verify that the static discipline is being met on the many pins of the integrated circuit. As the error in the comparator is lowered, the VLSI production yield is greatly increased because of greater certa

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4

Shar, Ahmad. "Design of a High-Speed CMOS Comparator." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-10446.

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<p>This master thesis describes the design of high-speed latched comparator with 6-bit resolution, full scale voltage of 1.6 V and the sampling frequency of 250 MHz. The comparator is designed in a 0.35 9m CMOS process with a supply voltage of 3.3 V.</p><p>The comparator is designed for time-interleaved bandpass sigma-delta ADC.</p><p>Due to the nature of the target application, it should be possible to turn off the components to avoid the static power consumption. The comparator of this design implements the turn off technique when it is not in use. The settling time of the comparator is less

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5

Ouyang, Jingwen M. Eng Massachusetts Institute of Technology. "A Comparator-Based Switched-Capacitor delta sigma modulator." Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/61249.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2010.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (p. 81).<br>Comparator-Based Switched-Capacitor (CBSC) is a relatively new topology that replaces op-amps in sampled-data systems with a comparator and a set of current mirrors. CBSC is expected to lower power consumption, and to avoid several delicate tradeoffs of op-amp circuits. In this paper, the original single-ended CBSC block is extended to a fully differential version. The differenti

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6

Aizad, Noor. "Design and implementation of comparator for sigma delta modulator." Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-6965.

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<p>Comparator is the main building block in an ADC architecture. Main purpose of the comparator is to compare a signal with a reference signal and produce an output depending on whether the input signal is greater or smaller than reference. Many architectures for comparators exist for various purposes. In this thesis, Latched comparator architecture is used for sigma delta modulator. This particular design has two main characteristics that are very important for sigma delta application. First characteristic is the cancellation of memory effect which increases the speed and reliability of the s

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7

Wong, Kim Fai. "Speed enhancement techniques for comparator-based switched-capacitor circuits." Thesis, University of Macau, 2010. http://umaclib3.umac.mo/record=b2493500.

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8

Fiorenza, John Kenneth 1977. "A comparator-based switched-capacitor pipelined analog-to-digital converter." Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/40312.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Includes bibliographical references (leaves 112-115).<br>A new comparator-based switched-capacitor(CBSC) technique is proposed that eliminates the need for high gain op-amps in switched-capacitor circuits. The CBSC technique replaces the op-amp in switched-capacitor circuits with a comparator and a current source. Compared to op-

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9

Torgersen, Svend Bjarne. "Comparator-Based Switched-Capacitor Integrator for use in Delta-Sigma Modulator." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2009. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-9045.

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<p>A comparator-based switched capacitor integrator for use in a Delta Sigma ADC has been designed. Basic theory about comparator-based circuits has been presented and design equations have been developed. The integrator had a targeted performance of a bandwidth of 1.5MHz with a SNR of 80dB. Due to the lack of a complete modulator feedback system, the integrator was simulated in open-loop. For the integrator not to saturate in open-loop, an overshoot calibration circuit was enabled during the simulation. This resulted in a severe deterioration of the integrated signal. The results are therefor

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10

Abreu, Fernandes Miguel Filipe. "SQUID based cryogenic current comparator for measuring low-intensity antiproton beams." Thesis, University of Liverpool, 2018. http://livrepository.liverpool.ac.uk/3022531/.

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In the low-energy Antiproton Decelerator (AD) and the Extra Low ENergy Antiproton (ELENA) rings at CERN, an absolute measurement of the beam intensity is essential to commission and troubleshoot the different accelerator systems, to measure the operational efficiency, and to provide calibration information for the different experiments using the antiproton (p) beam. Both the AD and ELENA are synchrotron decelerators, operating with both bunched and debunched - Direct Current (DC) - beams. The beam currents can be smaller than 100 nA, and the total number of circulating particles is of the orde

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11

Morris, John D. (John David) 1978. "Improving toggle rate in a rail-to-rail comparator output stage." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/16854.

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Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.<br>Includes bibliographical references.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>The demand for high-speed components has driven an increase in the speed of analog comparators, a building block for many analog circuits. This paper describes the modification of one of Linear Technology's low-cost, high-speed comparators to increase the output toggle rate beyond the one h

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12

Patalay, Dinkar. "64-bit high efficiency binary comparator in quantum-dot cellular automata." Thesis, California State University, Long Beach, 2016. http://pqdtopen.proquest.com/#viewpdf?dispub=10111200.

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<p> Quantum-dot Cellular Automata (QCA) are proposed models of quantum computation, which are articulated in analogy to Von Neumann's conventional models of cellular automata. These models are worthy for the architecture of ultra-dense low-power and high-performance digital circuits. Efficient solutions have recently been proposed for several arithmetic circuits, such as adders, multipliers, and comparators. Since the design of digital circuits in QCA still poses several challenges, novel implementation strategies and methodologies are highly desirable. This project demonstrates a new design

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13

Kudari, Sheetal. "An Ontology-based Automated Test Oracle Comparator for Testing Web Applications." Thesis, Malmö högskola, Fakulteten för teknik och samhälle (TS), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:mau:diva-20586.

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Traditional test oracles have two problems. Firstly, several test oracles are needed for a single software program to perform different functions and maintaining a large number of test oracles is tedious and might be prone to errors. Secondly, testers usually test only the important criteria of a web application, since its time consuming to check with all the possible criteria. Ontologies have been used in a wide variety of domains and they have also been used in software testing. However, they have not been used for test oracle automation. The main idea of this thesis is to define a procedu

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14

Escobar, Kenny E. "Photonic front-end and comparator processor for a sigma-delta modulator." Thesis, Monterey, Calif. : Naval Postgraduate School, 2008. http://edocs.nps.edu/npspubs/scholarly/theses/2008/Sept/08Sep%5FEscobar.pdf.

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Thesis (M.S. in Electrincal Engineering)--Naval Postgraduate School, September 2008.<br>Thesis Advisor(s): Pace, Phillip E. "September 2008." Description based on title screen as viewed on November 4, 2008. Includes bibliographical references (p. 65-66). Also available in print.

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15

Gracová, Kateřina. "Potential use of PPP at the reconstruction of prison in Uherské Hradiště." Master's thesis, Vysoká škola ekonomická v Praze, 2011. http://www.nusl.cz/ntk/nusl-126807.

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The aim of my thesis is to consider the usage of PPP method by the reconstruction of the object of former prison in town Uherské Hradiště using the methodology of the Ministry of Finance of the Czech Republic. In the theoretical part the description of the PPP method and its features is given. In the practical part the simplified financial model for project is counted. The outcomes of the model should be taken from the public sector point of view as the basic source for making decision if PPP method is the most efficient for this project.

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16

Rydholm, Annie. "Analysis of noise and offset in the comparator of ananalog-to-digital converter." Thesis, Linköping University, Department of Electrical Engineering, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-15152.

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<p>Since digital system has become very common today it is important to have good interfaces in between the analog and digital domain. This puts high demandson the analog to digital converter. It is therefore important in the design of theanalog to digital converter to reduce noise and offset as much as possible. That isalso what this analysis is going to consider but in a comparator which is a crucialpart of the analog to digital converter. The comparator consists of a preamplifierand a latch and it is the preamplifier that will be studied here. The analog todigital converter in consider is o

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17

Chan, Chi Hang. "A study on comparator and offset calibration techniques in high speed Nyquist ADCs." Thesis, University of Macau, 2011. http://umaclib3.umac.mo/record=b2493284.

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18

Seigel, James H. "The design of a current comparator for video-rate analog to digital conversion." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0006/MQ42688.pdf.

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19

Lee, Anders Wen-Dao. "The design of a high precision, wide common mode range auto-zero comparator." Thesis, Massachusetts Institute of Technology, 2015. http://hdl.handle.net/1721.1/100610.

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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Cataloged from student-submitted PDF version of thesis.<br>Includes bibliographical references (pages 89-90).<br>This thesis discusses the design and analysis of a high common-mode input auto-zero comparator for use in a Hot Swap controller. Comparators are essential building blocks within the current limit detection schemes

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20

CAPRA, PIER PAOLO. "Project of a digital cryogenic current comparator bridge for high precision dc resistance measurements." Doctoral thesis, Politecnico di Torino, 2012. http://hdl.handle.net/11583/2497270.

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The argument of the thesis is the project of a digital CCC bridge for accurate measurement of resistance ratios. The thesis is divided in two parts. The first two chapters are dedicated to the resistance standards technology and the normal Direct Current Comparator bridge. Then a chapter describes the electronic circuit of the bridge. The next describes the cryogenic parts of the bridge: the flux detector, the CCC with its probe and the shields systems.

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21

West, Paul Martin. "TECHNIQUES FOR DIGITAL LOW DROPOUT REGULATOR MODELING AND TRANSIENT RESPONSE ENHANCEMENT." OpenSIUC, 2016. https://opensiuc.lib.siu.edu/theses/1878.

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Low dropout regulators (LDOs) are important components for power management in modern integrated circuits. With the continued scaling down of power supply voltage, digital LDOs have become a more attractive design choice since they avoid the difficulty of designing high-gain amplifiers with low voltage. This thesis investigates techniques for both modeling and enhancement of digital LDO transient response. It discusses the importance of the resistance in the output stage of an LDO, and proposes a simulation model for examining LDO transient response. In addition, the thesis studies circuit tec

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22

Whitehead, Nathan Robert. "Design and Measurement of StrongARM Comparators." BYU ScholarsArchive, 2019. https://scholarsarchive.byu.edu/etd/8715.

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The StrongARM comparator is utilized in many analog-to-digital converters (ADCs) because of its high power efficiency and rail-to-rail outputs. The performance of the comparator directly affects the speed, power, and accuracy of an ADC. However, the StrongARM comparator performance parameters such as delay, noise, and offset measured directly from silicon prototypes are rare in literature and often consist of small sample sets. In addition, existing techniques to measure the comparator require large chip areas, making it impractical to characterize a large number of comparators to obtain stoch

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23

Dowlatabadi, Ahmad Baghai. "A high speed, high resolution, self-clocked voltage comparator in a standard digital CMOS process." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/14794.

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24

Wedikandage, Lanka Nilmini Priyadarshani. "A study of multicultural practices in Sri Lankan secondary schools and an English comparator school." Thesis, University of Bedfordshire, 2014. http://hdl.handle.net/10547/345673.

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This study investigated stakeholders’ views of multicultural policies and practices in multicultural secondary schools in Sri Lanka and a comparator school in England, in order to elicit what new insights could be gained that could lead to educational improvements in Sri Lankan schools. Specifically, students and staff in five Sinhala-medium secondary schools in the Colombo region, all with reputations for good multicultural education practice, together with local community leaders and national policy makers, were interviewed. A series of questionnaires was designed to examine a wide range of

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25

Holmgren, Mary. "A method to evaluate environmental enrichments for Asian elephants (Elephas maximus) in zoos." Thesis, Linköping University, The Department of Physics, Chemistry and Biology, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-11902.

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<p>Environmental enrichment (EE) is used to improve the life of captive animals by giving them more opportunities to express species-specific behaviours. Zoo elephants are one of the species that is in great need of EE because their environment is often barren. Before making EE permanent, however, it is wise to test first if it works as intended, to save time and money. Maximum price paid is one measure that can be used to assess if an animal has any interest in a resource at all. Food is often used as a comparator against EEs in these kinds of studies. The aim was to investigate if the maximu

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Qazi, Sara. "Study of Time-Interleaved SAR ADC andImplementation of Comparator for High DefinitionVideo ADC in 65nm CMOS Process." Thesis, Linköpings universitet, Elektroniksystem, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-63854.

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The Analog to Digital Converter (ADC) is an inevitable part of video AnalogFront Ends (AFE) found in the electronic displays today. The need to integratemore functionality on a single chip (there by shrinking area), poses great designchallenges in terms of achieving low power and desired accuracy.The thesis initially focuses upon selection of suitable Analog to Digital Converter(ADC) architecture for a high definition video analog front end. SuccessiveApproximation Register (SAR) ADC is the selected architecture as it scales downwith technology, has very less analog part and has minimal power

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27

Hedayati, Raheleh. "A Study of Successive Approximation Registers and Implementation of an Ultra-Low Power 10-bit SAR ADC in 65nm CMOS Technology." Thesis, Linköpings universitet, Elektroniska komponenter, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72767.

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In recent years, there has been a growing need for Successive Approximation Register (SAR) Analog-to-Digital Converter in medical application such as pacemaker. The demand for long battery life-time in these applications poses the requirement for designing ultra-low power SAR ADCs. This thesis work initially investigates and compares different structures of SAR control logics including the conventional structures and the delay line based controller. Additionally, it focuses on selection of suitable dynamic comparator architecture. Based on this analysis, dynamic two-stage comparator is select

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28

Wang, Mingzhen. "High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip." Wright State University / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=wright1189815482.

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29

Cao, Xingping. "Comparaison d'images conceptuelles et d'images reelles : application a la vision par ordinateur." Université Louis Pasteur (Strasbourg) (1971-2008), 1987. http://www.theses.fr/1987STR13076.

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On propose un systeme d'inspection capable d'effectuer des mesures dimensionnelles de pieces de structure variee. On compare les images reelles aux images conceptuelles fournies par un dispositif de conception assistee par ordinateur comportant une base de donnees

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30

Wanjau, R. W. "The design and development of an organic comparator for use in low cost smart sensor systems." Thesis, University of Liverpool, 2017. http://livrepository.liverpool.ac.uk/3019225/.

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31

McConnell, Bridget L. "Contrasting the extended comparator hypothesis and acquisition-focused models of learning differential predictions of retrospective revaluation /." Diss., Online access via UMI:, 2008.

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32

Paixão, Rúben José Freitas. "Measuring value for money in public private partnerships: a review of the public sector comparator in Australia, Canada, New Zealand and United Kingdom." Master's thesis, Instituto Superior de Economia e Gestão, 2012. http://hdl.handle.net/10400.5/4622.

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Mestrado em Contabilidade, Fiscalidade e Finanças Empresariais<br>Public-Private Partnerships are defined by the OCDE (2008) as "an agreement between the government and one or more private partners (which may include the operators and the financers) according to which the private partners deliver the service in such a manner that the service delivery objectives of the government are aligned with the profit objectives of the private partners and where the effectiveness of the alignment depends on a sufficient transfer of risk to the private partners". Due to their characteristics and due to gov

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Curado, Vera Lúcia Canatário Ribeiro. "A experiência portuguesa de renegociações das parcerias público privadas." Master's thesis, Instituto Superior de Economia e Gestão, 2013. http://hdl.handle.net/10400.5/11038.

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Mestrado em Ciências Empresariais<br>Num contexto onde as Parcerias Público Privadas (PPP) são um modelo privilegiado de cooperação entre o sector privado e público, importa entender a sua evolução em diferentes fases. Só assim é possível minimizar algumas das suas fragilidades entre as quais se destacam os pedidos de renegociação. Neste âmbito e com base nos dados disponibilizados em relatórios da Direção Geral do Tesouro nomeadamente de auditorias às PPP, foi analisada a evolução do número de PPP contratadas anualmente entre 1995 e 2010 assim como o número de pedidos de renegociação por ti

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34

Fransson, Daniel. "Lågoffsetkomparator." Thesis, Linköping University, Department of Electrical Engineering, 2002. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1076.

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<p>Detecting small signals with a comparator demands that the total voltage offset is lower than the actual signal. The total offset includes the voltage offset in the comparator and the voltage offset that is created by the offset currents that flows thru the load at the comparators input. The goal with this comparator that has been developed has been that it will have a total voltage offset at maximum 500 uV. The comparator does not need to be extremely fast or does not need to operate in a big frequency area. To have all the flexibility that is needed a full custom technique is used. When t

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35

Micheva, Nora Iordanova. "Design port and optimization of a high-speed SAR ADC comparator from 65nm to 0.11[mu]M." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/66446.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, June 2011.<br>"May 2011." In title on title page, "[mu]" appears as lower case Greek letter. Cataloged from PDF version of thesis.<br>Includes bibliographical references (p. 50-51).<br>As the world continues to do more and more of its signal processing digitally, there is an ever increasing need for high speed high precision signal processors in consumer applications such as digital photography. Technological progress in CMOS fabrication has allowed chips to be made on nano scale proc

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Kollarits, Matthew David. "Design and Simulation of a Temperature-Insensitive Rail-to-Rail Comparator for Analog-to-Digital Converter Application." University of Akron / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=akron1279036924.

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37

Boppana, Naga Venkata Vijaya Krishna. "16-bit Digital Adder Design in 250nm and 64-bit Digital Comparator Design in 90nm CMOS Technologies." Wright State University / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=wright1420674477.

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Powell, I. A. (Ian Allan). "The design and simulation of a superconductive, COSL compatible comparator and high-speed superconductive analog-to-digital converter." Thesis, Stellenbosch : Stellenbosch University, 2004. http://hdl.handle.net/10019.1/53765.

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Thesis (PhD)--University of Stellenbosch, 2004.<br>ENGLISH ABSTRACT: Analog-to-digital converters (ADCs) are an integral part of the interface between the analog and digital realms. This dissertation presents the design and simulation of a Complementary Output Switching-Logic (COSL) compatible, voltage state, switching logic comparator and a flash ADC for high speed applications with multi-GHz input bandwidth. Josephson technology and the COSL family of gates were utilized for this purpose. A detailed design for the switching logic comparator is first provided. The design is verified wit

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Nisar, Kashif. "DC to DC converter for smart dust." Thesis, Linköpings universitet, Institutionen för systemteknik, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-77247.

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This work describes the implementation of DC to DC converter for Smart Dust in 65 nm CMOS technology. The purpose of a DC to DC converter is to convert a battery voltage of 1 Vto a lower voltage of 0.5 V used by the processor. The topology used in this DC to DC converteris of Buck type which converts a higher voltage to lower voltage with the advantage of givinghigh efficiency about 75%. The system uses PWM (Pulse width modulation) technique. It usesnon-overlapping clock generation technique for reducing the power consumption. The systemprovides up to 5 mA load current and has power consumptio

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Mohamad, Ali Norfadhilah. "Appropriate comparator in national treatment under international investment law : relevance of GATT/WTO, EU and international human rights jurisprudences." Thesis, University of Dundee, 2014. https://discovery.dundee.ac.uk/en/studentTheses/59a3f88c-8750-4f0b-a04b-7edfe15a477d.

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The minimalist state of the national treatment provision in the investment treaties has provided limited guidance for the tribunals for interpretation. As a result, there were inconsistencies in the interpretation of national treatment, in particular the question of likeness. This thesis aims to develop the doctrinal understanding of the determination of appropriate comparator guided by the underlying philosophies, historical evolution and relevant investment decisions. The methods applied in this thesis are doctrinal and comparative studies of international investment law and the compared jur

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Papanikolaou, Vaskis. "A comparator and track and hold for use in a 1 GS/s, 10 bit analog to digital converter." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0018/MQ45995.pdf.

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Oesterdiekhoff, Brigitte. "On periodic comparator networks /." 1997. http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&doc_number=015163782&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA.

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CAI, KUN-TING, and 蔡坤廷. "High speed CMOS comparator." Thesis, 1990. http://ndltd.ncl.edu.tw/handle/65711983891699523325.

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44

Senapati, Prasanta Kumar. "Low power dynamic comparator design." Thesis, 2014. http://ethesis.nitrkl.ac.in/6386/1/E-21.pdf.

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In many applications there is a growing demand for the development of low voltage and low power circuits and systems. Low power consumption is of great interest because it increases the battery lifetime. One of the main building blocks in many applications is the analogue-to-digital converter (ADC) which serves as an interface between the analogue world and the digital processing unit. In all these designs the comparator of the ADC, which is one the most power hungry blocks, is always on. In order to reduce the power consumption of the ADC it is possible to turn the comparator off when the dec

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Chien, Mao-Chuan, and 簡茂全. "A CMOS High-speed Voltage Comparator." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/ub99h5.

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碩士<br>逢甲大學<br>電機工程所<br>90<br>This thesis presents a design of an innovational high-speed CMOS voltage comparator. The comparator proposed in this thesis uses a p-type differential pair as input stage to provide more gains which differs from using an n-type differential pair. Furthermore, the comparator makes use of a self-biasing circuit to provide a stable 3.5 V output voltage. This output voltage is not affected by the variations of temperature or supplies. By utilizing the designed circuit, high-speed can be achieved. The designed comparator is fabricated by UMC 0.5mm double-poly, tripl

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黃俊穎. "0.18 µm Comparator Design and Layout." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/w5hj9q.

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碩士<br>明新科技大學<br>積體電路佈局產業碩士專班<br>105<br>This paper mainly focuses on the design of the rear end of the comparator . Comparator is by comparing the two input current or voltage of the size of the output at the output of different voltage results of electronic components. Comparators are often used in analog-to-digital conversion circuits. Somehow, the process flow is examined and drawn step by step in details. The design rules using 0.18-micron process are considered to minimize the whole layout area including active and passive devices because it is associated with the process capability. Of co

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Gao, Yang. "An Energy Efficient Asynchronous Time-Domain Comparator." Thesis, 2013. http://hdl.handle.net/1969.1/149314.

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In energy-limited applications, such as wearable battery powered systems and implantable circuits for biological applications, ultra-low power analog-to-digital converters (ADCs) are essential for sustaining long time operation. As a fundamental building block of ADC, comparator should support a tightened power budget. Therefore, developing low-power design techniques for comparator is becoming more and more important. As an alternative to the conventional voltage-mode comparator, this thesis proposed an energy efficient time-domain comparator, which uses digital circuits to process analog si

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Fan, Yang-Dian, and 范揚典. "Comparator Implemented Digital Power Factor Correction Rectifier." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/fe7tu6.

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碩士<br>國立高雄科技大學<br>電機工程系<br>107<br>Power factor correction rectifier (PFC) is the front end of most computer power supplies. Due to the climate change, high efficiency over wide load range is highly demanded in PFCs. This drives digital controller to replace analog controller. Analog to digital converters (ADC) are the essential parts for all digital powers. Some previous researches replace the ADC with a comparator and a counter for measuring the DC value of a rippled signal. Comparator based control does not only reduces system cost, but also eliminates the sampling error of the ADC. For thos

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Chen, Yu-Kuo, and 陳玉國. "Design of High-performance Op-Amp and Comparator." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/18106771326921666574.

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碩士<br>國立交通大學<br>電子研究所<br>83<br>High performance operational amplifier and comparator for use in a 10-bit 50-MHz pipelined two-step A/D converter are introduced in this thesis. This operational amplifier is a complementary folded cascode amplifier which has a larger unity- gain B.W. and low-frequency voltage gain and does not need miller compensation capacitor with symmetrically configured complementary input stage and cascode output stage. The simulation results demonstrate a dc- gain of 66

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Yang, Chen-Chia, and 楊振加. "A 64 Bit Asynchronous Low Power Consumption Comparator." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/14309696274721609144.

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碩士<br>南台科技大學<br>電子工程系<br>95<br>In this paper, we propose a 64-bit low power asynchronous comparator which has flexibility, high expandability, and robustness. It is an asynchronous serial structural design. When compared result is equal, this computing result can be transmitted in next step by high bit to low bit. If compared result is not equal, the circuit will be stop and save unnecessary power consumption. Our design was implemented by using the process of TSMC’s 0.35μm. The layout for the design was generated with SpringSoft Laker and verified by Mentor Calibre (for DRC and LVS checks). S

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