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Journal articles on the topic 'Comparator'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 July 2025

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1

Song, Bangyu, and Yi Zhao. "A comparative research of innovative comparators." Journal of Physics: Conference Series 2221, no. 1 (2022): 012021. http://dx.doi.org/10.1088/1742-6596/2221/1/012021.

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Abstract This paper studies four novel design comparators and gives a detailed analysis and summary of them. edge-pursuit comparator (EPC) improved energy efficiency and noise over conventional comparators by a circuit loop consisting of numbers of delay units. The triple-tail fully dynamic comparator minimizes the comparator’s total delay time and enhances the sample rate. The dynamic bias architecture of the double-tail latch-type comparator can provide a relatively high voltage gain while ensuring a low power consumption by stabilizing the static operating point. It also has advantages over

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2

Sharmila Vallem. "Design of a High speed Low Low-Power Latched Comparator for Medical Implants." Communications on Applied Nonlinear Analysis 32, no. 8s (2025): 87–104. https://doi.org/10.52783/cana.v32.3610.

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The latched dynamic comparator is a fundamental component in all ADC architectures. Thermal effects, kickback, and offset voltage influence it. The kickback noise of the latched comparator in medical implant ADCs can impact the resolution, precision, and settling period. The current study examines a latching comparator that aims to reduce kickback noise. This research presents a low-power latched comparator for medical implants functioning at 1 V. This investigation implements a comparator utilising the sampling switching approach. This method successfully minimises kick-back noise and clockin

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3

Sun, Yuan. "A brief review on novel comparator design." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 418–27. http://dx.doi.org/10.54097/hset.v27i.3785.

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This paper reviewed three different kinds of comparators to show their respective advantage range. The Dynamic-bias comparator extends its pre-amplifier part with a capacitor and has a smaller power with a smaller input referred noise than Elzakker’s comparator but has a higher delay. The Quad high-speed comparator introduced the Quad into the comparator’s latch part. It has a lower delay and also make the calculation of the output voltage easier for it only depends on the skew factor. The low-power dynamic bias has a cross-couple device on its pre-amplifier part which slows down the discharge

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4

Du, Chengze. "Performance analysis of high-speed, low-power comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 292–301. http://dx.doi.org/10.54097/hset.v27i.3770.

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This article mainly presents a summary of development of dynamic comparators and the optimization to conventional comparator in recent years. By comparing the design of two different comparators, the design method of less power consumption, high speed or small delay, and low input referred noise can be concluded. The Dynamic comparator is designed to have small delay and less power consumption compared with two-stage comparator. The dynamic-bias comparator spends less power for operation the circuit compared with double-tail comparator. The FIA comparator operates under the controlling of logi

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Li, Yichen. "The Performance analysis of Low-Power High-Speed comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 72–82. http://dx.doi.org/10.54097/hset.v27i.3723.

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Comparators are the essential block for planning high-speed analog and. This paper presents three inventive designs of the comparators in recent years. First, innovated by classic two-stage comparator, the comparator with a transconductance-enhanced latching stage is suitable for low-power, high-speed operation. Second, triple-latch feed-forward(TLFF) fully dynamic comparator guarantees the maximum possible gain and speed for a specific power across the entire input range. Finally, the comparator with a dynamic floating inverter maximizes efficiency by reusing the current.

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6

Liu, Yuchuan. "An Review of Dynamic CMOS Comparators." Highlights in Science, Engineering and Technology 44 (April 13, 2023): 113–20. http://dx.doi.org/10.54097/hset.v44i.7273.

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CMOS dynamic comparators contributes a major role on the implementation of mixed signal successive approximation register (SAR) type of analog to digital converters (ADC). High precision, dynamic range, low voltage operation, high speed, low power consumption, reliability and offset voltage are the critical factors to be considered while designing CMOS dynamic comparators. This paper reviewed the performance of some popular dynamic CMOS comparators such as StrongARM latch comparator, double- tail dynamic-latched comparator, dynamic bias comparator and triple stage somparator.

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Palsodkar, Prachi, Pravin Dakhole, and Prasanna Palsodkar. "Reduced Complexity Linearity Improved Threshold Quantized Comparator Based Flash ADC." Journal of Circuits, Systems and Computers 26, no. 03 (2016): 1750046. http://dx.doi.org/10.1142/s0218126617500463.

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This paper describes a standard cell-based new approach of comparator design for flash ADC. Conventional flash ADC comparator consumes up to 60% of the power due to resistive ladder network and analog comparators. Threshold inverter quantized (TIQ) comparators reported earlier have improved speed and provide low-power, low-voltage operation. But they need feature size variation and have non-linearity issues. Here, a new standard cell comparator is proposed which retains all advantages of TIQ comparator and provides improved linearity with reduced hardware complexity. A 4-bit ADC designed using

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8

Du, Qinghang. "Analysis and comparison of several types of low-power, low offset comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 120–32. http://dx.doi.org/10.54097/hset.v27i.3728.

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This paper studies several excellent works of comparator constructions of comparators and compares them with the Double-tail latch-type comparator. Based on the Elzakker comparator, the comparator with a dynamic bias reduced the use of energy by partly discharging the preamplifier's output nodes. Edge-Pursuit Comparator(EPC) demonstrates a new approach to reducing energy consumption by automatic energy optimization. Apart from the designs that optimize energy consumption. Low-Noise Self-Calibrating Dynamic Comparator provides the low-offset feature while in relatively low power consumption.

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9

Fan, Jiangfeng. "Performance Analysis of Low-Power CMOS Dynamic Comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 62–71. http://dx.doi.org/10.54097/hset.v27i.3722.

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This paper studies four structures of CMOS dynamic comparators introduced in recent years. Based on conventional double-tail comparator, a comparator with a tail capacitor prevents output nodes of preamplifier from completely discharging to reduce energy consumption. Another comparator with a cross-coupled pairs achieves the same purpose of the first design. A comparator adds a floating inverter amplifier (FIA) to realize both dynamic bias and current reuse, achieve low energy consumption and be insensitive to the VCM. The triple-latch feed-forward (TLFF) comparator decreases delay conspicuous

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10

Takai, Nobukazu, Kento Suzuki, and Yoshiki Sugawara. "Comparator Synthesis Using Distributed Genetic Algorithm and HSPICE Optimization." Applied Mechanics and Materials 888 (February 2019): 17–28. http://dx.doi.org/10.4028/www.scientific.net/amm.888.17.

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In this paper, we propose an automatic design method that determines comparator topology and satisfies desired specification of the comparator by combining distributed genetic algorithm and HSPICE optimization function.In the comparator synthesis, new topology is created using known circuit topology information.After creating the topology, optimization of element values of the comparator is executed by distributed genetic algorithm and HSPICE optimization.As a target value example, specification of HA163S02 is used.Simulation results indicate that the proposed method can design the comparator

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11

Gajawada, Varun sai, and Mohana J. "Construction of CMOS Logic Double Tail Comparator for Lower Power Consumption Compared with Dynamic Comparator." ECS Transactions 107, no. 1 (2022): 13873–85. http://dx.doi.org/10.1149/10701.13873ecst.

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The aim of the study is to construct and analyze innovative CMOS based double tail comparators and compare them with a dynamic comparator using VLSI technology. Materials and methods: The comparator is designed by using the tanner tool for simulation and verification. By varying the length of a transistors the power values were obtained. There are two groups in the study. CMOS double tail comparator is the experimental group and dynamic tail comparator is the control group. This experiment is performed for 20 different values of length. Results: The power consumption of a CMOS logic double tai

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RAMAMOORTHY, SARAVANAN, and HAIBO WANG. "ADDRESSING MEMORY EFFECT FOR RAIL-TO-RAIL COMPARATOR WITH NEAR-THRESHOLD SUPPLY VOLTAGE." Journal of Circuits, Systems and Computers 22, no. 06 (2013): 1350048. http://dx.doi.org/10.1142/s0218126613500485.

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Ultra-low voltage comparators with rail-to-rail input ranges are critical components in the design of low-voltage low-power analog to digital converters (ADCs). This paper investigates the memory effect of a commonly used comparator when its power supply is scaled down to near transistor threshold voltage levels. It also studies when such memory effects are most likely to occur during the conversion sequences of successive approximation register (SAR) ADCs. Subsequently an improved comparator design is presented to overcome the memory effect with near-threshold voltage power supply. The impact

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Garcia Arieta, Alfredo, Craig Simon, Gustavo Mendes Lima Santos, et al. "A Survey of the Regulatory Requirements for the Acceptance of Foreign Comparator Products by Participating Regulators and Organizations of the International Generic Drug Regulators Programme." Journal of Pharmacy & Pharmaceutical Sciences 22 (January 1, 2019): 28–36. http://dx.doi.org/10.18433/jpps30215.

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The acceptance of foreign comparator products is the most limiting factor for the development and regulatory assessment of generic medicines marketed globally. Bioequivalence studies have to be repeated with the local comparator products of each jurisdiction because it is unknown if the comparators of the different countries are the same product, with the consequent duplication of efforts by regulators and industry alike. The regulatory requirements on the acceptability of foreign comparator products of oral dosage forms differ between countries participating in the Bioequivalence Working Grou

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14

Wang, Sudong. "Review of Four Improving Designs of Dynamic Latch Comparator." Highlights in Science, Engineering and Technology 44 (April 13, 2023): 129–37. http://dx.doi.org/10.54097/hset.v44i.7287.

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In this paper, four disparate designs of dynamic latch comparators are discussed consecutively. By improving the design of the pre-amplifier stage, the double tail comparator provides a good power-speed trade-off. Further, Differential pair amplifiers are implemented in the second design, which has better comparison speed and energy dissipation. Next, a bulk-driven structure is employed on the comparator design to improve the comparison speed. Finally, a dynamic comparator utilizes a floating reservoir capacitor and a positive feedback bulk structure is introduced to achieve higher energy effi

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15

Gupta, Anshu, Lalita Gupta, and R. K. Baghel. "Low Power Continuous-Time Delta-Sigma Modulators Using the Three Stage OTA and Dynamic Comparator." International Journal of Engineering & Technology 7, no. 2.16 (2018): 38. http://dx.doi.org/10.14419/ijet.v7i2.16.11413.

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A second-order sigma delta modulator that uses an operational transconductance amplifier as integrator and latch comparator as quantizer. The proposed technique where a low power high gain OTA is used as integrator and another circuit called dynamic latch comparator with two tail transistors and two controlling switches are used to achieve high speed, low power and high resolution in second order delta sigma modulator. It enhances the power efficiency and compactness of the modulator by implementing these blocks as sub modules. A second order modulator has been designed to justify the effectiv

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16

Dai, Haolin. "4-bit Absolute-value Detector Based on Multisim." Applied and Computational Engineering 128, no. 1 (2025): 7–12. https://doi.org/10.54254/2755-2721/2025.20227.

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In many circuit systems, it is necessary to compare the amplitude of the signal, so it is necessary to design an absolute value comparator to compare the input values. This paper introduces a four-bit binary absolute value comparator, which can realize the size comparison of four-bit binary signed numbers. This paper introduces some basic working principles of the absolute value comparator through the truth table. The absolute value is obtained by using the adder to invert the input four-digit number and add 1. The three-bit comparator is realized by connecting the three comparators, and the f

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17

G., Naveen Balaji, Karthikeyan S., and Merlin Asha M. "0.18µm CMOS Comparator for High Speed Applications." International Journal of Trend in Scientific Research and Development 1, no. 5 (2017): 671–74. https://doi.org/10.31142/ijtsrd2356.

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In the electronics industry the Low Power Comparator using High Speed in Analog to Digital Converters. In electronic device Comparator are mostly used in Analog to Digital converter ADC . In ADC are used for the delay produced and power consumed by an ADC. I design a 0.18µm CMOS Comparator for High Speed Application. The advantage of programmable hysteresis to the comparators are also discussed. Tanner EDA is used for the design and simulation for the comparator circuits The difference between the proposed comparator to the existing double tail comparator result are produced. G. Naveen B

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Wang, Yao, Haibo Wang, and Guangjun Wen. "Design Techniques for Ultra-Low Voltage Comparator Circuits." Journal of Circuits, Systems and Computers 24, no. 01 (2014): 1550013. http://dx.doi.org/10.1142/s0218126615500139.

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This paper presents a novel low-voltage rail-to-rail comparator circuit and derives optimal transistor size ratios for both conventional latch-based and the proposed comparators which operate in transistor subthreshold region. The obtained analytical results serve well as guidelines for designing low-voltage comparators and the proposed circuit is significantly faster than existing rail-to-rail comparator designs in ultra-low voltage operation.

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19

Tang, Chengyun. "Performance analysis of comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 172–82. http://dx.doi.org/10.54097/hset.v27i.3742.

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This article reviews the innovative and improved structure of three comparators, and summarizes the optimization ideas to further optimize the design parameters of the comparators in the future. The Triple-Tail Dynamic Comparator proposes a multi-stage design to break connection between speed and noise. The Dynamic Bias Latch-Type (DB) Comparator takes an innovative approach to reducing energy consumption by stabilizing the source node voltage of the input pairs. The floating inverter amplififier (FIA)-based pre-amplififier further improves the energy efficiency based on the design of the low-

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20

Thai, Hong-Hai, Cong-Kha Pham, and Duc-Hung Le. "Design of a Low-Power and Low-Area 8-Bit Flash ADC Using a Double-Tail Comparator on 180 nm CMOS Process." Sensors 23, no. 1 (2022): 76. http://dx.doi.org/10.3390/s23010076.

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This paper presents a low-area 8-bit flash ADC that consumes low power. The flash ADC includes four main blocks—an analog multiplexer (MUX), a comparator, an encoder, and an SPI (Serial Peripheral Interface) block. The MUX allows the selection between eight analog inputs. The comparator block contains a TIQ (Threshold Inverter Quantization) comparator, a control circuit, and a proposed architecture of a Double-Tail (DT) comparator. The advantage of using the DT comparator is to reduce the number of comparators by half, which helps reduce the design area. The SPI block can provide a simple way

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Zhang, Yuxin. "Design analyst of low energy, high gm/Id, and high sensitivity comparator." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 183–90. http://dx.doi.org/10.54097/hset.v27i.3745.

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This paper analyses three innovative designs of comparators and those structures have better performance than the traditional comparator. The dynamic floating inverter amplifier improves energy efficiency by preventing full discharging and charging. The Dynamic Bias Latch-Type Comparator used a double-tails latch to decrease energy consumption. The charge-injection compensations comparator has better sensitivity and less noise by utilizing the feedback loop. Those methods have greatly increased voltage gain, energy efficiency, and gm/Id

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22

Kelly, Lauren E., Elin Haf Davies, Agnes Saint-Raymond, Paolo Tomasi, and Martin Offringa. "Important issues in the justification of a control treatment in paediatric drug trials." Archives of Disease in Childhood 101, no. 10 (2016): 962–67. http://dx.doi.org/10.1136/archdischild-2016-310644.

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ObjectiveThe value of comparative effectiveness trials in informing clinical and policy decisions depends heavily on the choice of control arm (comparator). Our objective is to identify challenges in comparator reasoning and to determine justification criteria for selecting a control arm in paediatric clinical trials.DesignA literature search was completed to identify existing sources of guidance on comparator selection. Subsequently, we reviewed a randomly selected sample of comparators selected for paediatric investigation plans (PIPs) adopted by the Paediatric Committee of the European Medi

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23

Zhou, Yibo. "Analysis of the Improved Conventional Dynamic Comparator and the Edge-Pursuit Comparator." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 385–98. http://dx.doi.org/10.54097/hset.v27i.3782.

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In order to understand and learn the comparator in detail, three kinds of comparator are analyzed in this paper. An improvement of the traditional dynamic double-tailed comparator. So as to get fast operation and low power in low supply voltages, the circuit of the traditional double-tailed comparator is modulated. Another one is an improved low-power comparator. During evaluation, we can activate its latch delayed in order to avoid excess power consumption and get sufficient preamplification gain. The most innovative design is named edge-pursuit comparator (EPC) which is a new energy-efficien

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Dharmireddy, Ajay Kumar, D. Sowjanya, D. Aravind, G. Sowmya, A. Chandu, and Rao G. Venkateswara. "Low Kickback Noise and High-Speed MultiStage Comparator for High-Speed SAR ADC's." International Journal of Microsystems and IoT 2, no. 2 (2024): 614–21. https://doi.org/10.5281/zenodo.10809165.

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In this paper, proposes the design of a high-speed, low-kickback, three-stage comparator built on CMOS technology. This 1.2V supply-operated comparator circuit develops for use in high-speed ADCs. There are three parts to the proposed comparator circuit: a preamplifier, a latch, and a regeneration stage. The input signal amplifies in the preamplifier stage, producing a differential output signal. Once the movement from the preamplifier (PA) stage strengthens, it is stored in the latch stage until the regeneration stage is ready to utilize—simulations in CMOS technology to test the sugges

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Chen, Zhenxiang, Yuheng Ni, and Zhenghao Xiong. "The Analysis of High-Speed Low-Power Dynamic Comparators." Journal of Physics: Conference Series 2187, no. 1 (2022): 012022. http://dx.doi.org/10.1088/1742-6596/2187/1/012022.

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Abstract This article reviews 5 different articles on optimizing comparators and focuses on their innovations. Many innovative methods are used to get a higher comparison speed, lower power consumption and degraded noise comparator. Many novel methods such as connecting the conventional two-stage dynamic comparator to a transconductance-enhanced latching stage, adding a charge pump to the Miyahara’s comparator, engendering two propagating edges in two inverter loops and measuring the distance between the two edges to compare different input voltage and using an inverter-based input pair which

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Chen, Yiming. "Innovative Techniques in Comparator Designs." Journal of Physics: Conference Series 2221, no. 1 (2022): 012022. http://dx.doi.org/10.1088/1742-6596/2221/1/012022.

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Abstract This paper presents four innovative designs of comparators proposed these years. A latch-type dynamic bias adds a tail capacitor to prevent fully discharging at the pre-amplifier output nodes to reduce energy consumption. The comparator is analysed and then compared with floating inverter amplifier (FIA) type. The pre-amplifier of the FIA type adopts an inverter-based input pair by a floating reservoir capacitor, greatly boosting gm/Id and improving the energy efficiency. The edge-pursuit comparator (EPC) provides a new perspective when designing comparators. According to the input di

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27

Zhu, Haomin. "Research on Four Different Designs of Comparator." Journal of Physics: Conference Series 2260, no. 1 (2022): 012003. http://dx.doi.org/10.1088/1742-6596/2260/1/012003.

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Abstract Comparators contribute a significant role to analogue to digital converters (ADC). This paper describes and evaluates four excellent comparator optimisation schemes in recent years and analyses their advantages and disadvantages, providing ideas for the following comparator research direction. In addition, this paper introduces the design steps of each comparator optimisation scheme. It shows how the designer completes the final optimisation scheme step by step from the practical problems, which provides a specific reference for the comparator designers in the future. A double-tail la

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Arunabala, Dr C., P. V. Sai Ranjitha, Bomminayuni Likhitha Gunturu Sravya, Bonagiri Navyasree, and Arumalla Mounika. "Design of Diversified Low Power and High-Speed Comparators using 45nm Cmos Technology." International Journal of Innovative Technology and Exploring Engineering 11, no. 5 (2022): 27–31. http://dx.doi.org/10.35940/ijitee.e9849.0411522.

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At Present, portable battery-operated devices are enhancing due to low power consumption and high-speed applications, The designed circuit with feedback are used to design novel circuits. If the comparator having feedback are without clock signal. The comparators are mainly designed to minimize the power consumption and with good accuracy because of clock signal, if the clock signal is there, it is used to drive the circuit with low current. But in the existed design the circuit is with high power and current. These drawbacks are overcome by using the projected designed comparator. The Project

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Latimer, Nicholas R., Aathish Chandrika Bhanu, and David G. T. Whitehurst. "Inconsistencies in Nice Guidance for Acupuncture: Reanalysis and Discussion." Acupuncture in Medicine 30, no. 3 (2012): 182–86. http://dx.doi.org/10.1136/acupmed-2012-010152.

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Background Acupuncture received a positive recommendation in the National Institute for Health and Clinical Excellence (NICE) clinical guideline for low back pain (LBP). However, no such recommendation was forthcoming in the NICE clinical guideline for osteoarthritis (OA). Importantly, the two guidelines adopted different treatment comparators in their economic analyses of acupuncture; in the LBP guideline ‘usual care’ was used (with no consideration of placebo/sham interventions), whereas ‘sham acupuncture’ was the comparator in the OA guideline. Objective To analyse the implications of using

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Lu, Xiaohui. "Multisim-Based Digital Comparator Design and Performance Optimization." Applied and Computational Engineering 127, no. 1 (2025): 16–23. https://doi.org/10.54254/2755-2721/2025.20276.

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Nowadays, as many electronic products are moving towards increased portability and high reliability, higher demands are being placed on the various performance parameters of digital integrated circuits. Currently, digital integrated circuits are developing in the direction of low power consumption. Digital comparators are widely used in many areas of digital integrated circuits. Power consumption has an impact on many performance parameters of digital integrated circuits, so it is important to optimize power consumption during the design of digital integrated circuits. Therefore, a digital com

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Dr., C. Arunabala, Ranjitha P.V.Sai, Likhitha Gunturu Sravya Bomminayuni, Navyasree Bonagiri, and Mounika Arumalla. "Design of Diversified Low Power and High-Speed Comparators using 45nm Cmos Technology." International Journal of Innovative Technology and Exploring Engineering (IJITEE) 11, no. 5 (2022): 27–31. https://doi.org/10.35940/ijitee.E9849.0411522.

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<strong>Abstract:</strong> At Present, portable battery-operated devices are enhancing due to low power consumption and high-speed applications, The designed circuit with feedback are used to design novel circuits. If the comparator having feedback are without clock signal. The comparators are mainly designed to minimize the power consumption and with good accuracy because of clock signal, if the clock signal is there, it is used to drive the circuit with low current. But in the existed design the circuit is with high power and current. These drawbacks are overcome by using the projected desig

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Priya, Nadendla Bindu, and Muralidharan Jayabhalan. "A 5 Bit 600MS/S Asynchronous Digital Slope ADC with Modified Strong Arm Comparator." International Journal of Engineering and Advanced Technology 9, no. 1s5 (2019): 41–43. http://dx.doi.org/10.35940/ijeat.a1012.1291s519.

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Strong arm comparator has some characteristics like it devours zero static power and yields rail to rail swing. It acquires a positive feedback allowed by two cross coupled pairs of comparators and results a low offset voltage in input differential stage. We modified a strong arm Comparator for high speed without relying on complex calibration Schemes. a 5-bit 600MS/s asynchronous digital slope analog to digital converter (ADS-ADC) with modified strong arm comparator designed in cadence virtuoso at 180nm CMOS technology. The design of SR-Latch using Pseudo NMOS NOR Gate optimizes the speed. Th

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Sharath kumar, L Yeshwanth, Nallam Balaji Ram Ganesh, and Voruganti Saketh. "Design of Area efficient comparator architecture using 5T XOR GATE." international journal of engineering technology and management sciences 7, no. 3 (2023): 494–98. http://dx.doi.org/10.46647/ijetms.2023.v07i03.69.

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The use of comparators in computation-based designs is extensive, making optimization crucial. While some comparator designs use dynamic logic to achieve low-power consumption, the limitations of low-speed and poor-noise margin make this approach challenging. The proposed comparator design offers a new solution that is both area-efficient and has a high operating speed while consuming low-power. It was designed using 180nm technology in Tanner Tool, and its results were observed. Overall, this work presents a promising new solution for optimizing digital comparators and improving the efficienc

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Sathishkumar, Arumugam, and Siddhan Saravanan. "A Low-Noise Dynamic Comparator with Offset Calibration for CMOS Image Sensor Architecture." Journal of Circuits, Systems and Computers 28, no. 02 (2018): 1950022. http://dx.doi.org/10.1142/s0218126619500221.

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A low-noise, high-speed, low-input-capacitance switched dynamic comparator (SDC) CMOS image sensor architecture is presented in this paper. The comparator design occupying less area and consuming lesser power is suitable for bank of comparators in CMOS image readouts. The proposed dynamic comparator eliminates the stacking issue related to the conventional comparator and reduces the offset noise further. The need for low-noise, low-power, area-efficient and high-speed flash analog-to-digital converters (ADCs) in many applications today motivated us to design a comparator for ADC. The rail-to-r

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Kulothungan, Brindha, and Manjula Jothilingam. "A low power and high speed 45 nm CMOS dynamic comparator with low offset." A low power and high speed 45nm CMOS dynamic comparator with low offset 14, no. 4 (2023): 2293–300. https://doi.org/10.11591/ijpeds.v14.i4.pp2293-2300.

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The development of efficient data converters necessitates the design of low-power and high-speed comparators with low offset. Data converters, such as analog to digital converters (ADCs) and digital to analog converters (DACs), are critical components in applications like wireless communication, multimedia, and sensor interfaces. To enhance the performance of these data converters, improving the speed and power efficiency of comparators becomes crucial. Designing dynamic comparators with low power consumption and high-speed capabilities greatly enhances the sampling rate and accuracy of data c

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Ahmadi, Muhammad, and Won Namgoong. "Comparator Power Minimization Analysis for SAR ADC Using Multiple Comparators." IEEE Transactions on Circuits and Systems I: Regular Papers 62, no. 10 (2015): 2369–79. http://dx.doi.org/10.1109/tcsi.2015.2466831.

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Chen, Chao-Kun, I.-Ling Cheng, Yu-Hung Chen, and Chih-Cheng Lai. "Efficacy and Safety of Sitafloxacin in the Treatment of Acute Bacterial Infection: A Meta-analysis of Randomized Controlled Trials." Antibiotics 9, no. 3 (2020): 106. http://dx.doi.org/10.3390/antibiotics9030106.

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This meta-analysis aimed to assess the efficacy and safety of sitafloxacin in treating acute bacterial infection. PubMed, Embase, and Cochrane databases were searched up to August 13, 2019. Only randomized controlled trials (RCTs) evaluating sitafloxacin and comparators in the treatment of acute bacterial infections were included. The outcomes were clinical and microbiological responses and the risk of adverse event (AE). Five RCTs were enrolled, including 375 and 381 patients who received sitafloxacin and the comparator, respectively. Overall, the clinical response rate of sitafloxacin in the

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Mukhopadhyay, Abhijit Kumar. "A Low Power Digital Binary Magnitude Comparator Design for Very Large Scale Integration Applications." Advanced Science, Engineering and Medicine 12, no. 6 (2020): 825–30. http://dx.doi.org/10.1166/asem.2020.2655.

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This paper reports two designs of low power digital binary magnitude comparator based on static complementary CMOS logic style. The designs make use of recently reported latest XNOR gate designs. The comparator designs proposed here are easily scalable for higher order bits and thus highly suitable for VLSI applications. Mathematical equations establishing the relation between input bit width and transistor count of the magnitude comparators have also been derived in this paper. For a 64 bit magnitude comparator, the designs proposed in this paper outperform an existing design by 12.17% and 10

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Shreesha, Kumara K., and B. Ramesh K. "Design and Implementation of Comparator circuit using Advanced Logic Technologies." Journal of VLSI Design and its Advancement 7, no. 2 (2024): 31–37. https://doi.org/10.5281/zenodo.11608424.

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<em>In the ever-evolving landscape of digital systems, the need for efficient and high-performance comparators has become increasingly vital. This paper presents the design and implementation of an N-bit comparator circuit, where N represents the number of bits for comparison. The comparator is a crucial component in digital systems, finding applications in areas such as arithmetic operations, data sorting, and decision-making processes. The proposed N-bit comparator leverages advanced logic technologies to achieve enhanced speed, reduced power consumption, and improved reliability. The design

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G.Lakshmi, Vara Prasad, N.suresh, R.Venkatesan, Jai Kumar V., and chakravarthy A.Arun. "A WELL-ORGANIZED VLSI STRUCTURE OF MEDIAN FILTER USING 8 BIT DATA COMPARATOR." International Journal of Computational Intelligence in Control 11, no. 2 (2019): 85–92. https://doi.org/10.5281/zenodo.7485582.

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Information mining, data sets, ATM and correspondence exchanging, logical registering, booking, man-made brainpower, advanced mechanics, picture, video, and flag handling all require arranging. The proposed work fosters a clever information comparator to monetarily sort/rank request networks by speed, power, and region. This study presents a region productive Middle Channel Comparator. This proposed framework was executed in Verilog HDL, mimicked by Model sim 6.4 c, and orchestrated by Xilinx. FPGA Austere 3 XC3S 200 TQ-144 executes the proposed framework. Six 8-digit comparators are proposed.

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Qi, Shaozhen. "A Review of Comparators Inprovment Design." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 407–17. http://dx.doi.org/10.54097/hset.v27i.3784.

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This paper reviews and analyzes the three proposed new comparators, as a indirection of future works. The first improved design is the pre-amplifier improved comparator that the input of the latch is changed to a PMOS transistor, and a pair of cross-coupled transistors are used in the preamplifier part to amplify the gain, which finally realizes the proposed circuit with better comparison speed, more less power dissipation. The switch separated latch comparator is another improved design that the latching stage with separate gate-biased cross-coupled transistors. Using this new transconductanc

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Dhanalakshmi, B., A. Shireesha, A. Ramya, T. Bharath Simha Reddy, G. Krishna Kishore, and Dr V. Madhurima. "High Speed and Area Efficient Scalable n-Bit Digital Comparator." International Journal for Research in Applied Science and Engineering Technology 12, no. 1 (2024): 1327–35. http://dx.doi.org/10.22214/ijraset.2024.58147.

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Abstract: The digital comparator is a crucial design element in various applications, including scientific computations. It is optimized for general-purpose computer architecture, memory addressing logic, queue buffers, and test circuits. High-speed comparators are essential for arithmetic operations, data sorting, and decision-making processes in digital systems. Area efficiency is crucial in integrated circuit design, as it minimizes the physical space a comparator occupies on a chip, reducing manufacturing costs and optimizing performance. The term "scalable" means the comparator can be ada

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Saima, Bashir, Najeeb-ud-din Hakim, and Rather G.M. "Comparator: Existing Architectures and A Novel Design Methodology." Journal of VLSI Design and its Advancement 7, no. 2 (2024): 1–9. https://doi.org/10.5281/zenodo.10897048.

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<em>By quality of its targeting a large variety of applications, comparators have received considerable research interest. This work examines the key advances in the circuit design of a low power comparator. Further, a new circuit employing an inverter to replace the comparator is proposed. The proposed threshold inverter quantisation based comparator is able to perform comparison at a very low power dissipation and less propagation delay. An authentic circuit simulator is employed to confirm the validity of the design, which calculates the delay of 160 ps and the power consumption of 3 &micro

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Brindha, Kulothungan, and Jothilingam Manjula. "A low power and high speed 45 nm CMOS dynamic comparator with low offset." International Journal of Power Electronics and Drive Systems (IJPEDS) 14, no. 4 (2023): 2293. http://dx.doi.org/10.11591/ijpeds.v14.i4.pp2293-2300.

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<p><span lang="EN-US">The development of efficient data converters necessitates the design of low-power and high-speed comparators with low offset. Data converters, such as analog to digital converters (ADCs) and digital to analog converters (DACs), are critical components in applications like wireless communication, multimedia, and sensor interfaces. To enhance the performance of these data converters, improving the speed and power efficiency of comparators becomes crucial. Designing dynamic comparators with low power consumption and high-speed capabilities greatly enhances the sa

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Fu, Xinmiao, Miao He, and Yuan Zhang. "Different improvement designs of conventional comparator." Journal of Physics: Conference Series 2113, no. 1 (2021): 012008. http://dx.doi.org/10.1088/1742-6596/2113/1/012008.

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Abstract Comparators play a significant role in the semiconductor industry and have become indispensable in the design of ADC. The delay and energy consumption are two important indicators of the comparator. Many designs have been made to reduce the delay and energy consumption, such as separated gata-biasing cross-coupled transistors for a new latching stage, and pMOS is used to replace nMOS in comparators. This paper analyzes the working principle of the proposed comparators designed for different needs reported on different papers. It compares their simulation results about key data such as

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Wei, Yuming, Xingyuan Tong, and Xin Xin. "A Fixed-Window Level-crossing ADC with a Single Comparator." Journal of Physics: Conference Series 2301, no. 1 (2022): 012026. http://dx.doi.org/10.1088/1742-6596/2301/1/012026.

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Abstract A fixed-window level-crossing analog-to-digital converter (LC-ADC) with a single comparator is proposed for the biomedical field. In this paper, a signal varying direction detection circuit is proposed to judge the trend of the input signal, instead of the low-precision comparator in the modified LC-ADC. The proposed LC-ADC utilizes only one continuous-time comparator instead of multiple comparators in traditional LC-ADC, leading to simplified implementation and significantly reducing the power consumption. The post-layout simulation results show that the power consumption of the prop

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Hari Kishore, K., K. DurgaKoteswara Rao, G. Manvith, K. Biswanth, and P. Alekhya. "Area, power and delay efficient 2-bit magnitude comparator using modified gdi technique in tanner 180nm technology." International Journal of Engineering & Technology 7, no. 2.8 (2018): 222. http://dx.doi.org/10.14419/ijet.v7i2.8.10413.

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Of late, low power configuration took shape into the mostimportant concentrations in designing the latest VLSI circuits. By considering the same at the maximum priority, another outline of two-bit GDI based Magnitude or Digital Comparator are recommended and actualized with the assistance of Modified GDI transistors. Comparators are building blocks in advanced VLSI configuration circuits. In the current patterns the necessity for occupying less area in chip and low power compact devices. In this paper we introduced another Magnitude Comparator which willutilize low power, and gives a quick res

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Li, Jian Shuang, Xiao Rong Huang, Ming Zhao He, and Lian Fu Li. "Study of Air Temperature Correction for Optical Path Based on Large-Scale Laser Comparator." Key Engineering Materials 625 (August 2014): 85–90. http://dx.doi.org/10.4028/www.scientific.net/kem.625.85.

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Large-scale comparators of over 30m range are traceable devices of dimensional measurement in advance large-scale manufacture domain. High precision large-scale laser comparator is an open air laser interferometric measurement device, mainly made up of length measurement system, guiding rail system and control system. The length measurement system use laser interference system to get displacements, the main source of the measurement uncertainty of displacements comes from the air temperature measurement uncertainty. This paper put forward a novel air temperature compensation method by weightin

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G, Poornima. "Design of Low Power Double Tail Dynamic Comparator." International Journal for Research in Applied Science and Engineering Technology 12, no. 6 (2024): 426–35. http://dx.doi.org/10.22214/ijraset.2024.63031.

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Abstract: Dynamic regenerative comparators are being used more and more to enhance power and speed economy in analog-todigital converters. These converters must be extremely low-power, area-efficient, and high-speed. In this case, the DCs (DC) power is analyzed. A new DC is suggested, modifying the traditional double-tail comparator circuit for quick and low-power functioning even at low supply voltages, in accordance with the analysis that has been provided. Little transistors are added, and the construct is kept simple. Additionally, a new DC in line with on the suggested double-tail topolog

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Ploshinskii, A. V., V. N. Khazhuev, and I. V. Khakhamov. "Conductivity comparator." Measurement Techniques 28, no. 10 (1985): 904–7. http://dx.doi.org/10.1007/bf00861775.

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