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Journal articles on the topic 'Compiler design'

To see the other types of publications on this topic, follow the link: Compiler design.

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Published: 4 June 2021

Last updated: 12 February 2022

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1

JONES, ALEX K., SHUYI SHAO, YU ZHANG, and RAMI MELHEM. "SYMBOLIC EXPRESSION ANALYSIS FOR COMPILED COMMUNICATION." Parallel Processing Letters 18, no. 04 (December 2008): 567–87. http://dx.doi.org/10.1142/s0129626408003570.

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Compiled communication can benefit the parallel application design and performance in several ways such as analyzing the communication pattern to optimize a configurable network for performance improvement or to visualize the communication requirements to study and improve the application design. In this article we present symbolic expression analysis techniques in a MPI parallel compiler. Symbolic expression analysis allows the identification and representation of the communication pattern and also assists in the determination of communication phases in MPI parallel applications at compile-time. We demonstrate that using compiler analysis based on symbolic expression analysis to determine the communication pattern can provide an accurate visualization of the communication requirements. Using information from the compiler to program a circuit switching interconnect in multiprocessor systems has the potential to achieve more efficient communication with lower cost compared to packet/wormhole switching. For example, we demonstrate that our compiler approach provides an average of 2.6 times improvement in message delay over a threshold-based runtime system for our benchmarks with a maximum improvement of 9.7 times.

2

Sattar, Abdul, and Torben Lorenzen. "Develop a compiler in Java for a compiler design course." ACM SIGCSE Bulletin 39, no. 2 (June 2007): 80–82. http://dx.doi.org/10.1145/1272848.1272890.

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3

Webb, W. T., and K. G. Nichols. "Microprocessor design using silicon compiler." IEE Proceedings E Computers and Digital Techniques 138, no. 4 (1991): 232. http://dx.doi.org/10.1049/ip-e.1991.0030.

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4

Debray, Saumya. "Making compiler design relevant for students who will (most likely) never design a compiler." ACM SIGCSE Bulletin 34, no. 1 (March 2002): 341–45. http://dx.doi.org/10.1145/563517.563473.

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5

Quiñones, Carlos García, Carlos Madriles, Jesús Sánchez, Pedro Marcuello, Antonio González, and Dean M. Tullsen. "Mitosis compiler." ACM SIGPLAN Notices 40, no. 6 (June 12, 2005): 269–79. http://dx.doi.org/10.1145/1064978.1065043.

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6

Crowe, Malcolm, Clark Nicol, Michael Hughes, and David Mackay. "On converting a compiler into an incremental compiler." ACM SIGPLAN Notices 20, no. 10 (October 1985): 14–22. http://dx.doi.org/10.1145/382286.382376.

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7

Ward, A. C., and W. P. Seering. "The Performance of a Mechanical Design ‘Compiler’." Journal of Mechanical Design 115, no. 3 (September 1, 1993): 341–45. http://dx.doi.org/10.1115/1.2919197.

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A mechanical design “compiler” has been developed which, given an appropriate schematic, specifications, and utility function for a mechanical design, returns catalog numbers for an optimal implementation. The compiler has been successfully tested on a variety of mechanical and hydraulic power transmission designs, and a few temperature sensing designs. Times required have been at worst proportional to the logarithm of the number of possible combinations of catalog numbers.

8

Leupers, R. "Compiler design issues for embedded processors." IEEE Design & Test of Computers 19, no. 4 (July 2002): 51–58. http://dx.doi.org/10.1109/mdt.2002.1018133.

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9

Ruckert, Martin. "Teaching compiler construction and language design." ACM SIGCSE Bulletin 39, no. 1 (March 7, 2007): 435–39. http://dx.doi.org/10.1145/1227504.1227460.

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10

Srinivasan, S. "Compiler design for sets in Pascal." ACM SIGPLAN Notices 25, no. 1 (January 3, 1990): 23–24. http://dx.doi.org/10.1145/74105.74107.

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11

Berstis, V. "The V compiler: automatic hardware design." IEEE Design & Test of Computers 6, no. 2 (April 1989): 8–17. http://dx.doi.org/10.1109/54.19131.

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12

Hoare, C. A. R., He Jifeng, and A. Sampaio. "Normal form approach to compiler design." Acta Informatica 30, no. 8 (August 1993): 701–39. http://dx.doi.org/10.1007/bf01191809.

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13

Ferrari, Davide, Angela Sara Cacciapuoti, Michele Amoretti, and Marcello Caleffi. "Compiler Design for Distributed Quantum Computing." IEEE Transactions on Quantum Engineering 2 (2021): 1–20. http://dx.doi.org/10.1109/tqe.2021.3053921.

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14

Traver, V. Javier. "On Compiler Error Messages: What TheySayand What TheyMean." Advances in Human-Computer Interaction 2010 (2010): 1–26. http://dx.doi.org/10.1155/2010/602570.

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Programmers often encounter cryptic compiler error messages that are difficult to understand and thus difficult to resolve. Unfortunately, most related disciplines, including compiler technology, have not paid much attention to this important aspect that affects programmers significantly, apparently because it is felt that programmers should adapt to compilers. In this article, however, this problem is studied from the perspective of the discipline of human-computer interaction to gain insight into why compiler errors messages make the work of programmers more difficult, and how this situation can be alleviated. Additionally, because poorly designed error messages affect novice programmers more adversely, the problems faced by computer science students while learning to program are analyzed, and the obstacles originated by compilers are identified. Examples of actual compiler error messages are provided and carefully commented. Finally, some possible measures that can be taken are outlined, and some principles for compiler error message design are included.

15

Chen, Yang, Alex Groce, Chaoqiang Zhang, Weng-Keen Wong, Xiaoli Fern, Eric Eide, and John Regehr. "Taming compiler fuzzers." ACM SIGPLAN Notices 48, no. 6 (June 23, 2013): 197–208. http://dx.doi.org/10.1145/2499370.2462173.

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16

Cooper, Keith D., and Timothy J. Harvey. "Compiler-controlled memory." ACM SIGPLAN Notices 33, no. 11 (November 1998): 2–11. http://dx.doi.org/10.1145/291006.291010.

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17

Ward, A. C., and W. P. Seering. "Quantitative Inference in a Mechanical Design ‘Compiler’." Journal of Mechanical Design 115, no. 1 (March 1, 1993): 29–35. http://dx.doi.org/10.1115/1.2919320.

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This paper presents the ideas underlying a computer program that takes as input a schematic of a mechanical or hydraulic power transmission system, plus specifications and a utility function, and returns catalog numbers from predefined catalogs for the optimal selection of components implementing the design. Unlike programs for designing single components or systems, this program provides the designer with a high level “language” in which to compose new designs. It then performs some of the detailed design process for him. The process of “compilation,” or transformation from a high to a low level description, is based on a formalization of quantitative inferences about hierarchically organized sets of artifacts and operating conditions. This allows design compilation without the exhaustive enumeration of alternatives. The paper introduces the formalism, illustrating its use with examples. It then outlines some differences from previous work, and summarizes early tests and conclusions.

18

Guilan, Dai, Zhang Suqing, Tian Jinlan, and Jiang Weidu. "A study of compiler techniques for multiple targets in compiler infrastructures." ACM SIGPLAN Notices 37, no. 6 (June 2, 2002): 45–51. http://dx.doi.org/10.1145/571727.571735.

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19

Haveraaen, Magne, Karla Morris, Damian Rouson, Hari Radhakrishnan, and Clayton Carson. "High-Performance Design Patterns for Modern Fortran." Scientific Programming 2015 (2015): 1–14. http://dx.doi.org/10.1155/2015/942059.

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This paper presents ideas for using coordinate-free numerics in modern Fortran to achieve code flexibility in the partial differential equation (PDE) domain. We also show how Fortran, over the last few decades, has changed to become a language well-suited for state-of-the-art software development. Fortran’s new coarray distributed data structure, the language’s class mechanism, and its side-effect-free, pure procedure capability provide the scaffolding on which we implement HPC software. These features empower compilers to organize parallel computations with efficient communication. We present some programming patterns that support asynchronous evaluation of expressions comprised of parallel operations on distributed data. We implemented these patterns using coarrays and the message passing interface (MPI). We compared the codes’ complexity and performance. The MPI code is much more complex and depends on external libraries. The MPI code on Cray hardware using the Cray compiler is 1.5–2 times faster than the coarray code on the same hardware. The Intel compiler implements coarrays atop Intel’s MPI library with the result apparently being 2–2.5 times slower than manually coded MPI despite exhibiting nearly linear scaling efficiency. As compilers mature and further improvements to coarrays comes in Fortran 2015, we expect this performance gap to narrow.

20

Haluza, Pavel, and Jiří Rybička. "Design of methodology for incremental compiler construction." Acta Universitatis Agriculturae et Silviculturae Mendelianae Brunensis 59, no. 7 (2011): 137–46. http://dx.doi.org/10.11118/actaun201159070137.

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The paper deals with possibilities of the incremental compiler construction. It represents the compiler construction possibilities for languages with a fixed set of lexical units and for languages with a variable set of lexical units, too. The methodology design for the incremental compiler construction is based on the known algorithms for standard compiler construction and derived for both groups of languages. Under the group of languages with a fixed set of lexical units there belong languages, where each lexical unit has its constant meaning, e.g., common programming languages. For this group of languages the paper tries to solve the problem of the incremental semantic analysis, which is based on incremental parsing. In the group of languages with a variable set of lexical units (e.g., professional typographic system TEX), it is possible to change arbitrarily the meaning of each character on the input file at any time during processing. The change takes effect immediately and its validity can be somehow limited or is given by the end of the input. For this group of languages this paper tries to solve the problem case when we use macros temporarily changing the category of arbitrary characters.

21

Subha Sri Lakshmi, T. "Low Power PCI Controller using Design Compiler." CVR Journal of Science & Technology 18, no. 1 (June 1, 2020): 38–42. http://dx.doi.org/10.32377/cvrjst1807.

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22

Canedo, Arquimedes, Ben A. Abderazek, and Masahiro Sowa. "Design and implementation of a queue compiler." Microprocessors and Microsystems 33, no. 2 (March 2009): 129–38. http://dx.doi.org/10.1016/j.micpro.2008.09.001.

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23

Moreno‐Seco, Francisco, and Mikel L. Forcada. "Learning Compiler Design as a Research Activity." Computer Science Education 7, no. 1 (January 1996): 73–98. http://dx.doi.org/10.1080/0899340960070105.

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24

Wagner, J., and R. Leupers. "C compiler design for a network processor." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20, no. 11 (2001): 1302–8. http://dx.doi.org/10.1109/43.959859.

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25

Verma, Amit, and Nikita Bakshi. "Chronological Advancement in Compiler Design: A Review." Research in Computing Science 103, no. 1 (December 31, 2015): 99–109. http://dx.doi.org/10.13053/rcs-103-1-9.

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26

Wu, J., R. Das, J. Saltz, H. Berryman, and S. Hiranandan. "Distributed memory compiler design for sparse problems." IEEE Transactions on Computers 44, no. 6 (June 1995): 737–53. http://dx.doi.org/10.1109/12.391186.

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27

Beenker, F., R. Dekker, R. Stans, and M. Van der Star. "Implementing macro test in silicon compiler design." IEEE Design & Test of Computers 7, no. 2 (April 1990): 41–51. http://dx.doi.org/10.1109/54.53044.

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28

Amarasinghe, Saman, Michael l. Gordon, Michal Karczmarek, Jasper Lin, David Maze, Rodric M. Rabbah, and William Thies. "Language and Compiler Design for Streaming Applications." International Journal of Parallel Programming 33, no. 2-3 (June 2005): 261–78. http://dx.doi.org/10.1007/s10766-005-3590-6.

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29

Lidbury, Christopher, Andrei Lascu, Nathan Chong, and Alastair F. Donaldson. "Many-core compiler fuzzing." ACM SIGPLAN Notices 50, no. 6 (August 7, 2015): 65–76. http://dx.doi.org/10.1145/2813885.2737986.

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30

Hu, J. S., M. Kandemir, N. Vijaykrishnan, M. J. Irwin, H. Saputra, and W. Zhang. "Compiler-directed cache polymorphism." ACM SIGPLAN Notices 37, no. 7 (July 17, 2002): 165–74. http://dx.doi.org/10.1145/566225.513858.

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31

Ramsey, Norman, and Simon L. Peyton Jones. "The C—compiler infrastructure." ACM SIGPLAN Notices 39, no. 9 (September 19, 2004): 1. http://dx.doi.org/10.1145/1016848.1016851.

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32

Baker, Henry G. "The COMFY 6502 compiler." ACM SIGPLAN Notices 32, no. 11 (November 1997): 25–30. http://dx.doi.org/10.1145/270941.270947.

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33

Dumke, Reiner, Kerstin Neumann, and Kerstin Stoeffler. "The metric based compiler." ACM SIGPLAN Notices 27, no. 12 (December 1992): 29–38. http://dx.doi.org/10.1145/142181.142190.

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34

Li, Yan Xin, and Guang Yu Li. "Design of Mini-Message Bus Control System Compiler." Applied Mechanics and Materials 416-417 (September 2013): 895–99. http://dx.doi.org/10.4028/www.scientific.net/amm.416-417.895.

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This paper studies the application programming interface in configuration software. Based on comprehensively considering softwares application, a mini-message bus configuration languageMMBCL language is designed by using C language, whose compiler and development environment are fulfilled. The designing, syntax analysis, semantic analysis of MMBCL are deeply discussed. This configuration language is simple, similar to C language, easy to write, consistent with industrial control standard. And it has successfully applied to the industrial project and proves the efficiencies of the configuration language and the compiler.

35

zhicheng, Wang, Xu xiaowen, Lu zhiyong, and Zhou shigang. "A Compiler Design Technique for EMS Test CS115." Open Automation and Control Systems Journal 6, no. 1 (December 31, 2014): 1451–55. http://dx.doi.org/10.2174/1874444301406011451.

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36

Сурков, А. В., and A. V. Surkov. "Использование Synopsys Design Compiler для синтеза самосинхронных схем." Международный журнал "Программные продукты и системы" 44 (December 11, 2014): 24–30. http://dx.doi.org/10.15827/0236-235x.108.024-030.

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37

Necula, George C., and Peter Lee. "The design and implementation of a certifying compiler." ACM SIGPLAN Notices 39, no. 4 (April 2004): 612–25. http://dx.doi.org/10.1145/989393.989454.

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38

de Kruijf, Marc A., Karthikeyan Sankaralingam, and Somesh Jha. "Static analysis and compiler design for idempotent processing." ACM SIGPLAN Notices 47, no. 6 (August 6, 2012): 475–86. http://dx.doi.org/10.1145/2345156.2254120.

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39

林, 涵菲. "Design and Application of a Process-Visible Compiler." Software Engineering and Applications 04, no. 05 (2015): 89–95. http://dx.doi.org/10.12677/sea.2015.45012.

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40

Andrews, K., R. R. Henry, and W. K. Yamamoto. "Design and implementation of the UW Illustrated compiler." ACM SIGPLAN Notices 23, no. 7 (July 1988): 105–14. http://dx.doi.org/10.1145/960116.54001.

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41

Necula, George C., and Peter Lee. "The design and implementation of a certifying compiler." ACM SIGPLAN Notices 33, no. 5 (May 1998): 333–44. http://dx.doi.org/10.1145/277652.277752.

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42

Waite, William M., Assad Jarrahian, Michele H. Jackson, and Amer Diwan. "Design and implementation of a modern compiler course." ACM SIGCSE Bulletin 38, no. 3 (September 26, 2006): 18–22. http://dx.doi.org/10.1145/1140123.1140132.

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43

Chen, Liang‐Gee, Lih‐Gwo Jeng, and Dong‐Jye Lin. "Application‐specific chip design using behavioral silicon compiler." Journal of the Chinese Institute of Engineers 17, no. 1 (January 1994): 107–12. http://dx.doi.org/10.1080/02533839.1994.9677572.

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44

Wagner, Jens, and Rainer Leupers. "C Compiler Design for an Industrial Network Processor." ACM SIGPLAN Notices 36, no. 8 (August 2001): 155–64. http://dx.doi.org/10.1145/384196.384218.

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45

Acebal, César F., Raúl Izquierdo Castanedo, and Juan M. Cueva Lovelle. "Good design principles in a compiler university course." ACM SIGPLAN Notices 37, no. 4 (April 2002): 62–73. http://dx.doi.org/10.1145/510857.510870.

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46

Foster, Ian, and Stephen Taylor. "A compiler approach to scalable concurrent-program design." ACM Transactions on Programming Languages and Systems 16, no. 3 (May 1994): 577–604. http://dx.doi.org/10.1145/177492.177612.

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47

Bassil, Youssef. "Compiler Design for Legal Document TranslationIn Digital Government." International Journal of Engineering Trends and Technology 67, no. 3 (March 25, 2019): 100–104. http://dx.doi.org/10.14445/22315381/ijett-v67i3p219.

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48

Strolenberg, Chris W. H. "Technology-independent design using the ASA silicon compiler." Microelectronics Journal 23, no. 8 (December 1992): 651–64. http://dx.doi.org/10.1016/0026-2692(92)90132-k.

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49

Cristiá, Maximiliano, Diego A. Hollmann, and Claudia Frydman. "A multi-target compiler for CML-DEVS." SIMULATION 95, no. 1 (April 13, 2018): 11–29. http://dx.doi.org/10.1177/0037549718765080.

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Discrete Event System Specification (DEVS) is a modular and hierarchical formalism for system modeling and simulation. DEVS models can be mathematically described; simulation is performed by tools called concrete simulators. Concerning atomic DEVS models, each concrete simulator has its own input language which is, essentially, a general-purpose programming language (such as Java or C++). Hence, once engineers have written the mathematical model, they need to manually translate it into the input language of the concrete simulator of their choice. In this paper we present a multi-target compiler for atomic DEVS models written in CML-DEVS, a mathematics-based DEVS modeling language. This multi-target compiler is able to compile a CML-DEVS model to the input languages of the PowerDEVS and DEVS-Suite concrete simulators. In this way, the CML-DEVS compiler frees engineers from the manual translation of their mathematical models. In fact, the same mathematical model can be simulated on both simulators by simply recompiling the model. The CML-DEVS multi-target compiler can be easily extended to produce code for other concrete simulators.

50

Qiu, Yan Zhang, Liang Guo, and Sheng Hui Liu. "The Design of Embedded Multi-Channel Data Acquisition System." Applied Mechanics and Materials 182-183 (June 2012): 660–64. http://dx.doi.org/10.4028/www.scientific.net/amm.182-183.660.

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This paper analyzes the Flash Memory interface, SDRAM interface, Ethernet interface and Serial-port expansion circuit. The Embedded Multi-channel Data Acquisition System is designed by MCF5272 microprocessor. The main control system of MCF5272 includes SDRAM, Flash and BDM interface and so on. At the software design, we main introduce the compile and develop of bootload and the compiler and debugging environment of μClinux build. On this base, the general methods and points of the embedded system hardware design were summarized.