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Dissertations / Theses on the topic 'Compiler'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 July 2025

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1

Harron, Thomas W. "Requirements compiler /." Connect to unofficial online version of: Requirements compiler, 2006. http://minds.wisconsin.edu/bitstream/1793/18753/1/HarronTom.pdf.

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2

Bendjeddou, Nadia. "The development of a new compiler-compiler front-end." Thesis, Aston University, 1989. http://publications.aston.ac.uk/10649/.

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The increasing cost of developing complex software systems has created a need for tools which aid software construction. One area in which significant progress has been made is with the so-called Compiler Writing Tools (CWTs); these aim at automated generation of various components of a compiler and hence at expediting the construction of complete programming language translators. A number of CWTs are already in quite general use, but investigation reveals significant drawbacks with current CWTs, such as lex and yacc. The effective use of a CWT typically requires a detailed technical understan

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3

Van, Dijk Jacques. "An Estelle compiler." Master's thesis, University of Cape Town, 1988. http://hdl.handle.net/11427/17736.

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The increasing development and use of computer networks has necessitated international standards to be defined. Central to the standardization efforts is the concept of a Formal Description Technique (FDT) which is used to provide a definition medium for communication protocols and services. This document describes the design and implementation of one of the few existing compilers for the one such FDT, the language "Estelle" ([ISO85], [ISO86], [ISO87]).

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4

Sarkar, Dipanwita. "Nanopass compiler infrastructure." [Bloomington, Ind.] : Indiana University, 2008. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:3337263.

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Thesis (Ph.D.)--Indiana University, Dept. of Computer Science, 2008.<br>Title from PDF t.p. (viewed on Jul 29, 2009). Source: Dissertation Abstracts International, Volume: 69-12, Section: B, page: 7627. Adviser: R. Kent Dybvig.

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5

Bone, David. "A syntax-directed compiler/compiler emitting LR(1) object-oriented code." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp01/MQ39110.pdf.

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6

Kim, Dongkeun. "Compiler-based pre-execution." College Park, Md. : University of Maryland, 2004. http://hdl.handle.net/1903/1957.

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Thesis (Ph. D.) -- University of Maryland, College Park, 2004.<br>Thesis research directed by: Electrical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.

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7

Cox, Russell Stensby. "An extension-oriented compiler." Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/45619.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Includes bibliographical references (leaves 107-110).<br>The thesis of this dissertation is that compilers can and should allow programmers to extend programming languages with new syntax, features, and restrictions by writing extension modules that act as plugins for the compiler. We call compilers designed around this idea exte

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8

Davis, Stephen Brooks. "Towards a liquid compiler." Thesis, Massachusetts Institute of Technology, 1993. http://hdl.handle.net/1721.1/34048.

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Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.<br>Includes bibliographical references (leaves 41-42).<br>by Stephen Brooks Davis.<br>M.S.

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9

Bierlee, Hendrik. "The MiniZinc-SAT Compiler." Thesis, Uppsala universitet, Institutionen för informationsteknologi, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-438608.

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Combinatorial (optimization) problems occur in nature and society. Constraint modeling languages such as MiniZinc allow the user to declaratively specify such problems in terms of its decision variables and constraints. Subsequently, the MiniZinc model can be compiled into an equivalent (Boolean) SAT formula to be solved by a SAT solver. This thesis reports on the design, implementation and experimental evaluation of the new MiniZinc-SAT compiler, which supports single or even mixed usage of three distinct integer variable encoding methods.

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10

Kienle, Holger M. "A SUIF Java compiler." [S.l.] : Universität Stuttgart , Fakultät Informatik, 1998. http://www.bsz-bw.de/cgi-bin/xvms.cgi?SWB6783619.

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11

Mercadier, Darius. "Usuba, Optimizing Bitslicing Compiler." Electronic Thesis or Diss., Sorbonne université, 2020. http://www.theses.fr/2020SORUS180.

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Le bitslicing est une technique utilisée pour implémenter des primitives cryptographiques efficaces et s'exécutant en temps constant. Cependant, écrire, optimiser, et sécuriser manuellement des programmes bitslicés est une tâche fastidieuse, nécessitant des connaissances en cryptographie, en microarchitecture des processeurs et en attaques par canaux cachés. Afin de remédier à ces difficultés, nous proposons Usuba, un langage dédié permettant d'implémenter des algorithmes de cryptographie symétrique. Usuba permet aux développeurs d'écrire des spécifications de haut niveau sans se soucier de le

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12

Tan, Jonathan S. "Compiler Optimization Effects on Register Collisions." DigitalCommons@CalPoly, 2018. https://digitalcommons.calpoly.edu/theses/1841.

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We often want a compiler to generate executable code that runs as fast as possible. One consideration toward this goal is to keep values in fast registers to limit the number of slower memory accesses that occur. When there are not enough physical registers available for use, values are ``spilled'' to the runtime stack. The need for spills is discovered during register allocation wherein values in use are mapped to physical registers. One factor in the efficacy of register allocation is the number of values in use at one time (register collisions). Register collision is affected by compiler op

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13

Aloisi, Giacomo. "OPoly: an OpenMP polyhedral compiler." Bachelor's thesis, Alma Mater Studiorum - Università di Bologna, 2021. http://amslaurea.unibo.it/23118/.

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In questa tesi introduciamo la polyhedral compilation, una moltitudine di tecniche volte a rappresentare programmi, specialmente quelli che coinvolgono cicli innestati e vettori, rappresentandoli attraverso poliedri parametrici e sfruttando alcune trasformazioni su di essi per analizzare e ottimizzare automaticamente i programmi dati. In particolare, descriviamo la nostra implementazione di un polyhedral compiler: OPoly. OPoly è un'applicazione realizzata in Python in grado di parallelizzare automaticamente cicli innestati che possono essere espressi attraverso un insieme di equazioni ri

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14

Hassan, Jawad. "Structured Text Compiler Targeting XML." Thesis, Växjö University, School of Mathematics and Systems Engineering, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:lnu:diva-6441.

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15

Ullah, Haseeb, and Amir Mofakhar. "An LLVM Compiler for CAL." Thesis, Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-16184.

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Massively parallel architectures are gaining momentum thanks to the opportunities for both high performance and low-power consumption. After being a matter for experiments in academia, manycores are now in production and industries with products that rely on high performance, for example, in the field of telecom and radar, are in the process of adopting them. In order to encourage adoption, there is a need for compiler technologies that can make appropriate use of the opportunities of these architectures. Programming languages with constructs that the compiler can easily identify as parallel a

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16

Fu, Chao-ying. "Compiler-Driven Value Speculation Scheduling." NCSU, 2001. http://www.lib.ncsu.edu/theses/available/etd-20010508-151111.

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<p>Modern microprocessors utilize several techniques for extracting instruction-level parallelism (ILP) to improve the performance. Current techniques employed in the microprocessor include register renaming to eliminate register anti- and output (false) dependences, branch prediction to overcome control dependences, and data disambiguation to resolve memory dependences. Techniques for value prediction and value speculation have been proposed to break register flow (true) dependences among operations, so that dependent operations can be speculatively executed without waiting for producer opera

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17

Deighan, John. "VPI PROLOG compiler project report." Master's thesis, This resource online, 1991. http://scholar.lib.vt.edu/theses/available/etd-01262010-020109/.

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18

Cheng, Chung-Cho Oliver. "A tool for compiler testing /." Online version of thesis, 1987. http://hdl.handle.net/1850/10181.

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19

Hong, Seong-Kwan. "Performance driven analog layout compiler." Diss., Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/15037.

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20

Emberson, Mark Alexander Hugh. "A dynamic compiler for Scheme." Thesis, University of Canterbury. Computer Science, 1995. http://hdl.handle.net/10092/9377.

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Traditionally, dynamically-typed languages have been difficult to compile efficiently. This thesis explores dynamic compilation, a recently developed technique for compiling dynamically-typed languages. A dynamic compiler compiles and optimizes programs as they execute, using information collected from the running program to perform optimizations that are impossible to perform in a conventional batch compiler. To explore these techniques we developed SKI, a dynamic compiler for Scheme. Tests on programs compiled by SKI, have shown that dynamic compilation techniques can give a substantial inc

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21

Stringer-Calvert, David William John. "Mechanical verification of compiler correctness." Thesis, University of York, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.245867.

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22

Bratt, Ian (Ian R. ). "Reptile : a distributed ILP compiler." Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/34372.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.<br>Includes bibliographical references (p. 69-71).<br>The past few years witnessed a dramatic shift in computer microprocessor design. Rather than continue with the traditional pursuit of increased sequential program performance, industry and academia alike chose to focus on distributed, multi-core designs. If multi-core designs are to maintain the decades-long trend of increased single threaded performance, compiler technology capable of converting a single threaded program into m

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23

Warren, Andrew S. "Towards a Genome Reverse Compiler." Thesis, Virginia Tech, 2007. http://hdl.handle.net/10919/35724.

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The Genome Reverse Compiler (GRC) is an annotation tool for prokaryotic genomes. Its name and philosophy are based on analogy with a high-level programming language compiler. In this analogy, the genome is a program in a certain low-level language that humans cannot understand. Given the sequence of any prokaryotic genome, GRC produces its corresponding "high-level program"--its annotation. GRC works in a completely automatic manner, using standard input and output formats. The goal is to provide an open-source, easy-to-run, very efficient annotation program.<br>Master of Science

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24

Briody, Brendan. "An XQuery to SQL compiler." [S.l. : s.n.], 2005. http://www.bsz-bw.de/cgi-bin/xvms.cgi?SWB11759115.

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25

Fourniotis, Pavlatos Panayis. "Compiler optimisation of typeless languages." Thesis, University of Cambridge, 1998. https://www.repository.cam.ac.uk/handle/1810/275469.

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We have written an optimising compiler for a typeless, imperative, modular programming language. The optimiser, which works on a 3-address intermediate representation generated from the source program, uses some novel techniques described in this thesis. The techniques are universally applicable, although some are particularly useful in typeless compilation. We present a new register allocation and assignment scheme. Unlike traditional "colouring" allocators, our method separates the problem into distinct allocation and assignment phases. The former is achieved by using an iterative process to

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26

Janaki, S. "A Parallelizing Compiler for Fortran." Thesis, Indian Institute of Science, 1999. https://etd.iisc.ac.in/handle/2005/79.

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With the advent of Distributed Memory Machines (DMMs) numerous work have been undertaken to ease the work of a programmer these systems. Data parallel languages like Fortran D, Vienna Fortran, High Performance Fortran and C+ allow the user to specify data distribution across processor with some directives, and the compiler for these language use the directives to compile the programme in to an SPMD code. There are number of old program which are still in use and rewriting them in to new data parallel languages is a costly effort. Most of the work on these parallelizing compilers concentrate o

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27

Janaki, S. "A Parallelizing Compiler for Fortran." Thesis, Indian Institute of Science, 1999. http://hdl.handle.net/2005/79.

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With the advent of Distributed Memory Machines (DMMs) numerous work have been undertaken to ease the work of a programmer these systems. Data parallel languages like Fortran D, Vienna Fortran, High Performance Fortran and C+ allow the user to specify data distribution across processor with some directives, and the compiler for these language use the directives to compile the programme in to an SPMD code. There are number of old program which are still in use and rewriting them in to new data parallel languages is a costly effort. Most of the work on these parallelizing compilers concentrate on

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28

Eberhart, Paul S. "A Compiler Target Model for Line Associative Registers." UKnowledge, 2019. https://uknowledge.uky.edu/ece_etds/138.

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LARs (Line Associative Registers) are very wide tagged registers, used for both register-wide SWAR (SIMD Within a Register )operations and scalar operations on arbitrary fields. LARs include a large data field, type tags, source addresses, and a dirty bit, which allow them to not only replace both caches and registers in the conventional memory hierarchy, but improve on both their functions. This thesis details a LAR-based architecture, and describes the design of a compiler which can generate code for a LAR-based design. In particular, type conversion, alignment, and register allocation are d

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29

Trudel, Marco. "Java sourcecode to Eiffel sourcecode compiler." Zurich : ETH, Swiss Federal Institute of Technology Zurich, Institute of Software Engineering, 2008. http://e-collection.ethbib.ethz.ch/show?type=dipl&nr=441.

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30

Royuela, Alcázar Sara. "High-level compiler analysis for OpenMP." Doctoral thesis, Universitat Politècnica de Catalunya, 2018. http://hdl.handle.net/10803/620642.

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Nowadays, applications from dissimilar domains, such as high-performance computing and high-integrity systems, require levels of performance that can only be achieved by means of sophisticated heterogeneous architectures. However, the complex nature of such architectures hinders the production of efficient code at acceptable levels of time and cost. Moreover, the need for exploiting parallelism adds complications of its own (e.g., deadlocks, race conditions,...). In this context, compiler analysis is fundamental for optimizing parallel programs. There is however a trade-off between complexity

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31

Alexandersson, Anders. "RubyComp : a Ruby to CIL compiler." Thesis, University West, Department of Technology, Mathematics and Computer Science, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:hv:diva-551.

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32

Gao, Lin Computer Science &amp Engineering Faculty of Engineering UNSW. "Compiler techniques for thread-level speculation." Awarded by:University of New South Wales. Computer Science & Engineering, 2009. http://handle.unsw.edu.au/1959.4/44749.

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Dual-core, quad-core and many-core processors are replacing the traditional single-core processors. To take advantage of these multicore processors, traditional sequential applications need to be parallelised. However, the compiler often fails to find enough thread-level parallelism from sequential applications, especially from general-purpose applications with the extensive use of pointers, indirectly-indexed structures, or complex control flows. The major challenge lies in identifying dependences in sequential applications so that independent threads can be extracted from the applications. T

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33

Gagnon, Étienne. "SableCC, an object-oriented compiler framework." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape10/PQDD_0007/MQ44169.pdf.

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34

Hu, Jianghong. "A datapath compiler with technology portability." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape4/PQDD_0021/MQ53433.pdf.

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35

Gao, Xiaoyang. "Integrated compiler optimizations for tensor contractions." Columbus, Ohio : Ohio State University, 2008. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1198874631.

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36

Baudendistel, Kurt. "Compiler development for fixed-point processors." Diss., Georgia Institute of Technology, 1992. http://hdl.handle.net/1853/15355.

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37

Gagnon, Etienne. "SableCC, an object-oriented compiler framework." Thesis, McGill University, 1998. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=20824.

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In this thesis, we introduce SableCC, an object-oriented framework that generates compilers (and interpreters) in the Java programming language. This framework is based on two fundamental design decisions. Firstly, the framework uses object-oriented techniques to automatically build a strictly-typed abstract syntax tree that matches the grammar of the compiled language and simplifies debugging. Secondly, the framework generates tree-walker classes using an extended version of the visitor design pattern which enables the implementation of actions on the nodes of the abstract syntax tree using i

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38

Qiu, ZhiPing. "Tack-a TTCNASN.1 compiler kit." Thesis, McGill University, 1992. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=56953.

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An important recent advance in the area of communications has been the development of standards for specifying test suites for Open System Interconnection (OSI) systems. In particular, the standardization and formalization of test suites has been achieved through the development of a formal specification language, Tree and Tabular Combined Notation (TTCN), and an associated data definition language, Abstract Syntax Notation One (ASN.1). This development of formal language for specifying test suites has provided a new challenge for compiler developers. That is, the development of a compiler tha

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39

Sampaio, Augusto. "An algebraic approach to compiler design." Thesis, University of Oxford, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.334903.

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40

Calnan, III Paul W. "EXTRACT: Extensible Transformation and Compiler Technology." Digital WPI, 2003. https://digitalcommons.wpi.edu/etd-theses/484.

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Code transformation is widely used in programming. Most developers are familiar with using a preprocessor to perform syntactic transformations (symbol substitution and macro expansion). However, it is often necessary to perform more complex transformations using semantic information contained in the source code. In this thesis, we developed EXTRACT; a general-purpose code transformation language. Using EXTRACT, it is possible to specify, in a modular and extensible manner, a variety of transformations on Java code such as insertion, removal, and restructuring. In support of this, we also d

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41

Coore, Daniel. "Automatic profiler-driven probabilistic compiler optimization." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/35396.

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42

Waingold, Elliot L. (Elliot Lee) 1977. "SIFt : a compiler for streaming applications." Thesis, Massachusetts Institute of Technology, 2000. http://hdl.handle.net/1721.1/86565.

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Thesis (S.B. and M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.<br>Includes bibliographical references (p. 79-81).<br>by Elliot L. Waingold.<br>S.B.and M.Eng.

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43

Eriksson, Simon, and Patrik Andersson. "Efficient IR for the OpenModelica Compiler." Thesis, Linköpings universitet, Programvara och system, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-148321.

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The OpenModelica compiler currently generates code directly from a syntax tree representation, which leads to inefficient code in several cases. This thesis work introduces a lower-level intermediate representation for the compiler which aims to simplify the compiler back end and enable more optimizations. The resulting design of the representation features flat primitive operations and control flow using basic blocks and terminators. Variables are mutable, unlike SSA-based representations. Introducing the IR did not significantly change the runtime performance of the test programs. The number

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44

Calnan, Paul W. "EXTRACT, Extensible Transformation and Compiler Technology." Link to electronic thesis, 2003. http://www.wpi.edu/Pubs/ETD/Available/etd-0429103-152947.

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45

Perna, Juan Ignacio. "A verified compiler for Handel-C." Thesis, University of York, 2010. http://etheses.whiterose.ac.uk/585/.

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The recent popularity of Field Programmable Gate Array (FPGA) technology has made the synthesis of Hardware Description Language (HDL) programs into FPGAs a very attractive topic for research. In particular, the correctness in the synthesis of an FPGA programming file from a source HDL program has gained significant relevance in the context of safety or mission-critical systems. The results presented here are part of a research project aiming at producing a verified compiler for the Handel-C language. Handel-C is a high level HDL based on the syntax of the C language extended with constructs t

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46

Lameed, Nurudeen. "Dynamic compiler optimization techniques for MATLAB." Thesis, McGill University, 2013. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=119604.

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MATLAB has gained widespread acceptance among engineers and scientists. Several aspects of the language such as dynamic loading and typing, safe updates, copy semantics for arrays, and support for higher-order functions contribute to its appeal, but at the same time provide many challenges to the compiler and virtual machine. MATLAB is a dynamic language. Traditional implementations of the language use interpreters and have been found to be too slow for large computations. More recently, researchers and software developers have been developing JIT compilers for MATLAB and other dynamic languag

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Manning, Joy Elizabeth. "For-Comprehension : An Encore Compiler Story." Thesis, Uppsala universitet, Institutionen för informationsteknologi, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-397321.

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Encore is an active object programming language that is being developed at Uppsala University. The programming language includes a for-loop construct with limited functionality. This thesis describes the implementation of a more extensive looping construct called for- comprehension, to replace the for-loop. The resulting for- comprehension is a powerful tool for iteration that allows for elegantly written loops and is ripe for further development.

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48

Tofte, Mads. "Compiler generators : what they can do, what they might do, and what they will probably never do /." Berlin : Springer, 1990. http://opac.nebis.ch/cgi-bin/showAbstract.pl?u20=3540514716.

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49

Zhuang, Xiaotong. "Compiler Optimizations for Multithreaded Multicore Network Processors." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/11566.

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Network processors are new types of multithreaded multicore processors geared towards achieving both fast processing speed and flexibility of programming. The architecture of network processors considers many special properties for packet processing, including multiple threads, multiple processor cores on the same chip, special functional units, simplified ISA and simplified pipeline, etc. The architectural peculiarities of network processors raise new challenges for compiler design and optimization. Due to very high clocking speeds, the CPU memory gap on such processors is huge, making regis

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DeVries, Derek J. "A vectorizing SUIF compiler, implementation and performance." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp04/mq29405.pdf.

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