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Relevant bibliographies by topics / Complementary Bipolar integrated circuits

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Academic literature on the topic 'Complementary Bipolar integrated circuits'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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Journal articles on the topic "Complementary Bipolar integrated circuits"

1

Kazior, Thomas E. "Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 372, no. 2012 (March 28, 2014): 20130105. http://dx.doi.org/10.1098/rsta.2013.0105.

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Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications.

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2

Lee, Changyeop, Gyuseong Cho, Troy Unruh, Seop Hur, and Inyong Kwon. "Integrated Circuit Design for Radiation-Hardened Charge-Sensitive Amplifier Survived up to 2 Mrad." Sensors 20, no. 10 (May 12, 2020): 2765. http://dx.doi.org/10.3390/s20102765.

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According to the continuous development of metal-oxide semiconductor (MOS) fabrication technology, transistors have naturally become more radiation-tolerant through steadily decreasing gate-oxide thickness, increasing the tunneling probability between gate-oxide and channel. Unfortunately, despite this radiation-hardened property of developed transistors, the field of nuclear power plants (NPPs) requires even higher radiation hardness levels. Particularly, total ionizing dose (TID) of approximately 1 Mrad could be required for readout circuitry under severe accident conditions with 100 Mrad around a reactor in-core required. In harsh radiating environments such as NPPs, sensors such as micro-pocket-fission detectors (MPFD) would be a promising technology to be operated for detecting neutrons in reactor cores. For those sensors, readout circuits should be fundamentally placed close to sensing devices for minimizing signal interferences and white noise. Therefore, radiation hardening ability is necessary for the circuits under high radiation environments. This paper presents various integrated circuit designs for a radiation hardened charge-sensitive amplifier (CSA) by using SiGe 130 nm and Si 180 nm fabrication processes with different channel widths and transistor types of complementary metal-oxide-semiconductor (CMOS) and bipolar CMOS (BiCMOS). These circuits were tested under γ–ray environment with Cobalt-60 of high level activity: 490 kCi. The experiment results indicate amplitude degradation of 2.85%–34.3%, fall time increase of 201–1730 ns, as well as a signal-to-noise ratio (SNR) of 0.07–11.6 dB decrease with irradiation dose increase. These results can provide design guidelines for radiation hardening operational amplifiers in terms of transistor sizes and structures.

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3

Ellinger, Frank, David Fritsche, Gregor Tretter, Jan Dirk Leufker, Uroschanit Yodprasit, and C. Carta. "Review of Millimeter-Wave Integrated Circuits With Low Power Consumption for High Speed Wireless Communications." Frequenz 71, no. 1-2 (January 1, 2017): 1–9. http://dx.doi.org/10.1515/freq-2016-0119.

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Abstract In this paper we review high-speed radio-frequency integrated circuits operating up to 210 GHz and present selected state-of-the-art circuits with leading-edge performance, which we have designed at our chair. The following components are discussed employing bipolar complementary metal oxide semiconductors (BiCMOS) technologies: a 200 GHz amplifier with 17 dB gain and around 9 dB noise figure consuming only 18 mW, a 200 GHz down mixer with 5.5 dB conversion gain and 40 mW power consumption, a 190 GHz receiver with 47 dB conversion gain and 11 dB noise figure and a 60 GHz power amplifier with 24.5 dBm output power and 12.9 % power added efficiency (PAE). Moreover, we report on a single-core flash CMOS analogue-to-digital converter (ADC) with 3 bit resolution and a speed of 24 GS/s. Finally, we discuss a 60 GHz on-off keying (OOK) BiCMOS transceiver chip set. The wireless transmission of data with 5 Gb/s at 42 cm distance between transmitter and receiver was verified by experiments. The complete transceiver consumes 396 mW.

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4

Hossain, Maruf, Ina Ostermay, Nils G. Weimann, Franz Josef Schmueckle, Johannes Borngraeber, Chafik Meliani, Marco Lisker, et al. "Performance study of a 248 GHz voltage controlled hetero-integrated source in InP-on-BiCMOS technology." International Journal of Microwave and Wireless Technologies 9, no. 2 (November 13, 2015): 259–68. http://dx.doi.org/10.1017/s1759078715001634.

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This paper presents the performance study of a 248 GHz voltage-controlled hetero-integrated signal source using indium phosphide (InP)-on-bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. The source consists of a voltage controlled oscillator (VCO) in 0.25 µm BiCMOS technology and a frequency multiplier in 0.8 µm transferred-substrate InP-heterojunction bipolar transistor technology, which is integrated on top of the BiCMOS monolithic microwave integrated circuit in a wafer-level based benzocyclobutene bonding process. The vertical transitions from BiCMOS to InP in this process exhibit broadband properties with insertion losses below 0.5 dB up to 325 GHz. The VCO operates at 82.7 GHz with an output power of 6 dBm and the combined circuit delivers −9 dBm at 248 GHz with 1.22% tuning range. The phase noise of the combined circuit is −85 dBc/Hz at 1 MHz offset. The measured output return loss of the hetero-integrated source is >10 dB within a broad frequency range. This result shows the potential of the hetero integrated process for THz frequencies.

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5

Božanić, Mladen, and Saurabh Sinha. "Emerging Transistor Technologies Capable of Terahertz Amplification: A Way to Re-Engineer Terahertz Radar Sensors." Sensors 19, no. 11 (May 29, 2019): 2454. http://dx.doi.org/10.3390/s19112454.

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This paper reviews the state of emerging transistor technologies capable of terahertz amplification, as well as the state of transistor modeling as required in terahertz electronic circuit research. Commercial terahertz radar sensors of today are being built using bulky and expensive technologies such as Schottky diode detectors and lasers, as well as using some emerging detection methods. Meanwhile, a considerable amount of research effort has recently been invested in process development and modeling of transistor technologies capable of amplifying in the terahertz band. Indium phosphide (InP) transistors have been able to reach maximum oscillation frequency (fmax) values of over 1 THz for around a decade already, while silicon-germanium bipolar complementary metal-oxide semiconductor (BiCMOS) compatible heterojunction bipolar transistors have only recently crossed the fmax = 0.7 THz mark. While it seems that the InP technology could be the ultimate terahertz technology, according to the fmax and related metrics, the BiCMOS technology has the added advantage of lower cost and supporting a wider set of integrated component types. BiCMOS can thus be seen as an enabling factor for re-engineering of complete terahertz radar systems, for the first time fabricated as miniaturized monolithic integrated circuits. Rapid commercial deployment of monolithic terahertz radar chips, furthermore, depends on the accuracy of transistor modeling at these frequencies. Considerations such as fabrication and modeling of passives and antennas, as well as packaging of complete systems, are closely related to the two main contributions of this paper and are also reviewed here. Finally, this paper probes active terahertz circuits that have already been reported and that have the potential to be deployed in a re-engineered terahertz radar sensor system and attempts to predict future directions in re-engineering of monolithic radar sensors.

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6

McDermott, H. "Cochlear Implant for Simultaneous Multichannel Stimulation." Annals of Otology, Rhinology & Laryngology 96, no. 1_suppl (January 1987): 67–69. http://dx.doi.org/10.1177/00034894870960s133.

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A new cochlear implant is described that can stimulate up to three bipolar electrode pairs simultaneously. It uses a scala tympani electrode array comprising 20 separate platinum ring electrodes. The bipolar mode of stimulation is used to minimize the spread of current in the cochlea. Nearly all of the electronics of the device are integrated into a single custom-designed large-scale integrated circuit. A prototype of the chip has been fabricated using an advanced complementary metal oxide semiconductor technology. Preliminary test results indicate that the device functions according to its specifications. The implant, which is still under development, will use a single transcutaneous inductive link to receive both controlling data and electric power from an external speech processor.

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Soref, Richard. "Applications of Silicon-Based Optoelectronics." MRS Bulletin 23, no. 4 (April 1998): 20–24. http://dx.doi.org/10.1557/s0883769400030220.

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Silicon-based optoelectronics is a diversified technology that has grown steadily but not exponentially over the past decade. Some applications—such as smart-pixel signal processing and chip-to-chip optical interconnects—have enjoyed impressive growth, whereas other applications have remained quiescent. A few important applications such as optical diagnosis of leaky metal-oxide-semiconductor-field-effect-transistor circuits, have appeared suddenly. Over the years, research and development has unveiled some unique and significant aspects of Si-based optoelectronics. The main limitation of this technology is the lack of practical silicon light sources—Si lasers and efficient Si light-emitting devices (LEDs)—though investigators are “getting close” to the LED.Silicon-based optoelectronics refers to the integration of photonic and electronic components on a Si chip or wafer. The photonics adds value to the electronics, and the electronics offers low-cost mass-production benefits. The electronics includes complementary-metal-oxide semiconductors (CMOS), very large-scale integration (VLSI), bipolar CMOS, SiGe/Si heterojunction bipolar transistors, and heterostructure field-effect transistors. In this discussion, we will use a loose definition of optoelectronics that includes photonic and optoelectronic integrated circuits (PICs and OEICs), Si optical benches, and micro-optoelectromechanical (MOEM) platforms. Optoelectronic chips and platforms are subsystems of computer systems, communication networks, etc. Silicon substrates feature a superior native oxide, in addition to excellent thermal, mechanical, and economic properties. Silicon wafers “shine” as substrates for PICs and OEICs.

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Tsai, Jung Hui, Shao Yen Chiu, Wen Shiung Lour, Chien Ming Li, Yi Zhen Wu, Ning Xing Su, and Yin Shan Huang. "InGaP/GaAs pnp Heterojunction Bipolar Transistor with δ-Doped Sheet between Base-Emitter Junction." Advanced Materials Research 47-50 (June 2008): 383–86. http://dx.doi.org/10.4028/www.scientific.net/amr.47-50.383.

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In this article, a novel InGaP/GaAs pnp δ-doped heterojunction bipolar transistor is first demonstrated. Though the valence band discontinuity at InGaP/GaAs heterojunction is relatively large, the addition of a δ-doped sheet between two spacer layers at the emitter-base junction effectively eliminates the potential spike and increases the confined barrier for electrons, simultaneously. Experimentally, a high current gain of 25 and an offset voltage of 100 mV are achieved. The offset voltage is much smaller than the conventional InGaP/GaAs pnp HBT. The proposed device could be used for linear amplifiers and low-power complementary integrated circuit applications.

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9

Sotner, Roman, Jan Jerabek, Ladislav Polak, Roman Prokop, and Vilem Kledrowetz. "Integrated Building Cells for a Simple Modular Design of Electronic Circuits with Reduced External Complexity: Performance, Active Element Assembly, and an Application Example." Electronics 8, no. 5 (May 22, 2019): 568. http://dx.doi.org/10.3390/electronics8050568.

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This paper introduces new integrated analog cells fabricated in a C035 I3T25 0.35-μm ON Semiconductor process suitable for a modular design of advanced active elements with multiple terminals and controllable features. We developed and realized five analog cells on a single integrated circuit (IC), namely a voltage differencing differential buffer, a voltage multiplier with current output in full complementary metal–oxide–semiconductor (CMOS) form, a voltage multiplier with current output with a bipolar core, a current-controlled current conveyor of the second generation with four current outputs, and a single-input and single-output adjustable current amplifier. These cells (sub-blocks of the manufactured IC device), designed to operate in a bandwidth of up to tens of MHz, can be used as a construction set for building a variety of advanced active elements, offering up to four independently adjustable internal parameters. The performances of all individual cells were verified by extensive laboratory measurements, and the obtained results were compared to simulations in the Cadence IC6 tool. The definition and assembly of a newly specified advanced active element, namely a current-controlled voltage differencing current conveyor transconductance amplifier (CC-VDCCTA), is shown as an example of modular interconnection of the selected cells. This device was implemented in a newly synthesized topology of an electronically linearly tunable quadrature oscillator. Features of this active element were verified by simulations and experimental measurements.

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Rong, Liang, Shan Jie Jia, Kui Hua Wu, Chun Mei Fu, and Qing Mao Fu. "The Effect of Dead Zone Mode on Electric Vehicle PWM Speed Control System." Advanced Materials Research 986-987 (July 2014): 1337–41. http://dx.doi.org/10.4028/www.scientific.net/amr.986-987.1337.

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To realize the electric vehicle braking energy recycling and driving smooth, bipolar PWM modulation mode is often adopted. To avoid the bridge arm shoot-through, a dead zone needs to be set in the complementary upper and lower bridge arm driving signal. Using hardware circuit dead zone setting has the advantages of simple setting and high reliability, is often used in the integrated driving module, however different dead zone mode has different influence on the inverter output voltage. This paper carried analysis on motor speed nonlinear problems caused by output voltage jump around a specific duty ratio in hardware dead zone setting mode, and gives the improvement of hardware circuit. Simulation and experimental results indicate that the method can well solve the output voltage jump in the vicinity of a specific duty ratio problem.

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Dissertations / Theses on the topic "Complementary Bipolar integrated circuits"

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Ting, Goodwin. "An integrated BiCMOS driver chip for medium power applications /." Online version of thesis, 1991. http://hdl.handle.net/1850/11291.

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Lee, Wai Kit. "Modeling the distributed RC effects of BiCMOS technology at high frequency operations /." View abstract or full-text, 2006. http://library.ust.hk/cgi/db/thesis.pl?ECED%202006%20LEE.

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Hirschman, Karl D. "Process development of an analog/digital mixed-mode BiCMOS system at RIT /." Online version of thesis, 1992. http://hdl.handle.net/1850/11238.

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Guidash, R. Michael. "Development of a modular 2-micron BiCMOS process from an existing 2-micron n-well CMOS process /." Online version of thesis, 1991. http://hdl.handle.net/1850/11234.

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La, Pietra Andrew R. "Establishing a bipolar fabrication service for analog circuit realization at the Rochester Institute of Technology /." Online version of thesis, 1991. http://hdl.handle.net/1850/11272.

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Long, John R. (John Robert) Carleton University Dissertation Engineering Electrical. "High frequency integrated circuit design in BICMOS for monolithic timing recovery." Ottawa, 1992.

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7

Seth, Sachin. "Using complementary silicon-germanium transistors for design of high-performance rf front-ends." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/44721.

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The objective of the research presented in this dissertation is to explore the achievable dynamic range limits in high-performance RF front-ends designed using SiGe HBTs, with a focus on complementary (npn + pnp) SiGe technologies. The performance requirements of RF front-ends are high gain, high linearity, low dc power consumption, very low noise figure, and compactness. The research presented in this dissertation shows that all of these requirements can easily be met by using complementary SiGe HBTs. Thus, a strong case is made in favor of using SiGe technologies for designing high dynamic range RF front-ends. The contributions from this research are summarized as follows: 1. The first-ever comparison study and comprehensive analysis of small-signal linearity (IIP3) for npn and pnp SiGe HBTs on SOI. 2. A novel comparison of large-signal robustness of npn and pnp SiGe HBTs for use in high-performance RF front-ends. 3. A systematic and rigorous comparison of SiGe HBT compact models for high-fidelity distortion modeling. 4. The first-ever feasibility study of using weakly-saturated SiGe HBTs for use in severely power constrained RF front-ends. 5. A novel X-band Low Noise Amplifier (LNA) using weakly-saturated SiGe HBTs. 6. Design and comprehensive analysis of RF switches with enhanced large-signal linearity. 7. Development of novel methods to reduce crosstalk noise in mixed-signal circuits and the first-ever analysis of crosstalk noise across temperature. 8. Design of a very high-linearity cellular band quadrature modulator for use in base-station applications using first-generation complementary SiGe HBTs.

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8

Diestelhorst, Ryan Matthew. "The design of SiGe integrated circuit components for extreme environment systems and sensors." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/50262.

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A background investigation of the total-dose radiation tolerance of a third generation complementary SiGe:C BiCMOS technology platform was performed. Tolerance was quantified under proton and X-ray radiation sources for both the npn and pnp HBT, as well as for an operational amplifier built with these devices. Furthermore, a technique known as junction isolation radiation hardening was proposed and tested with the goal of improving the SEE sensitivity of the npn by reducing the charge collected by the subcollector in the event of a direct ion strike. Three independent systems were designed, including: 1) a charge amplification channel developed as part of a remote electronics unit for the lunar environment, 2) variable bias circuitry for a self-healing radar receiver, and 3) an ultra-fast x-ray detector for picosecond scale time-domain measurements of evolving chemical reactions. The first two projects capitalized on the wide-temperature performance and radiation tolerance of the SiGe HBT, allowing them to operate under extreme environmental conditions reliably and consistently. The third design makes use of the high-frequency capabilities of the HBT, particularly in emitter-coupled logic (ECL) configurations. Findings concerning the performance of these systems and implications for future research are discussed.

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Barthélemy, Hervé. "Conception et application de nouveaux circuits analogiques mettant en oeuvre une boucle translineaire mixte a huit transistors." Paris 11, 1996. http://www.theses.fr/1996PA112234.

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Une nouvelle boucle translineaire mixte composee de huit transistors bipolaires (quatre npn et quatre pnp) est introduite. L'etude des invariances de la structure, a partir de la theorie des graphes, a permis de definir les differentes polarisations utilisables pour celle-ci. Nous en avons aussi deduit la position des miroirs de courant qu'il est possible de connecter sur cette boucle. Une polarisation particuliere parmi celles comprenant deux sources de courant a entierement ete traitee. Les proprietes dynamiques des circuits qui resultent des differentes polarisations sont ensuite analysees. Plusieurs nouveaux circuits deduits des analyses precedentes sont presentes: convoyeur de courant de seconde generation a resistance de sortie negative, convoyeur de courant de seconde generation a haute impedance d'entree, convoyeur de courant de troisieme generation ayant une faible distorsion pour une faible consommation. La boucle permet aussi de synthetiser une resistance flottante dont la valeur est controlee en courant. Les possibilites de realiser des convoyeurs quasi-parfait a partir de convoyeurs deja existants sont ensuite presentees et les limitations correspondantes analysees dans le cas particulier des circuits amplificateurs et differentiateurs. La derniere partie du memoire presente l'etude theorique, la realisation et les resultats de mesure relatifs a un oscillateur sinusoidal controle en courant dont la frequence est reglable entre 20mhz et 90mhz. Cet oscillateur utilise, entre autres, la resistance flottante realisee a partir de la boucle mixte a huit transistors precedente. Cette architecture a en particulier permis de controler l'amplitude du signal sans modifier la frequence. Il comprend aussi un circuit limiteur d'amplitude compose de quatre diodes. Cet oscillateur a ete realise par sgs-thomson en technologie bicmos 2m sous forme de circuit integre

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Kenyon, Eleazar Walter. "Low-noise circuitry for extreme environment detection systems implemented in SiGe BiCMOS technology." Thesis, Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/44873.

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This work evaluates two SiGe BiCMOS technology platforms as candidates for implementing extreme environment capable circuitry, with an emphasis on applications requiring high sensitivity and low noise. In Chapter 1, applications requiring extreme environment sensing circuitry are briefly reviewed and the motivation for undertaking this study is outlined. A case is then presented for the use of SiGe BiCMOS technology to meet this need, documenting the benefits of operating SiGe HBTs at cryogenic temperatures. Chapter 1 concludes with a brief description of device radiation effects in bipolar and CMOS devices, and a basic overview of noise in semiconductor devices and electronic components. Chapter 2 further elaborates on a specific application requiring low-noise circuitry capable of operating at cryogenic temperatures and proposes a number of variants of band-gap reference circuits for use in said system. Detailed simulation and theoretical analysis of the proposed circuits are presented and compared with measurements, validating the techniques used in the proposed designs and emphasizing the need for further understanding of device level low-temperature noise phenomena. Chapter 3 evaluates the feasibility of using a SiGe BiCMOS process, whose response to ionizing radiation was previously uncharacterized, for use in unshielded electronic systems needed for exploration of deep space planets or moons, specifically targeting Europa mission requirements. Measured total ionizing dose (TID) responses for both CMOS and bipolar SiGe devices are presented and compared to similar technologies. The mechanisms responsible for device degradation are outlined, and an explanation of unexpected results is proposed. Finally, Chapter 4 summarizes the work presented and understanding provided by this thesis, concluding by outlining future research needed to build upon this study and fully realize SiGe based extreme environment capable precision electronic systems.

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Books on the topic "Complementary Bipolar integrated circuits"

1

Bipolar/BiCMOS Circuits and Technology Meeting (1994 Minneapolis, Minn.). Proceedings of the 1994 Bipolar/BiCMOS Circuits and Technology Meeting. Piscataway, NJ: IEEE Order Dept., 1994.

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Bipolar/BiCMOS, Circuits and Technology Meeting (1992 Minneapolis Minn ). Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting. New York, NY: IEEE, 1992.

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A, Bellaouar, and Elmasry Mohamed I. 1943-, eds. Digital BiCMOS integrated circuit design. Boston: Kluwer Academic, 1993.

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1948-, Maejima Hideo, ed. High-performance BiCMOS technology and its applications to VLSIs. New York: Gordon and Breach Science Publishers, 1990.

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Bipolar/BiCMOS Circuits and Technology Meeting (2000 Minneapolis, Minn.). Proceedings of the 2001 Bipolar/BiCMOS Circuits and Technology Meeting: September 30-October 2, 2001. Piscataway, New Jersey: IEEE, 2001.

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Bipolar/BiCMOS Circuits and Technology Meeting (2002 Minneapolis, Minn.). Proceedings of the 2002 Bipolar/BiCMOS Circuits and Technology Meeting: [Minneapolis, Minnesota] September 29-October 1, 2002. Piscataway, N.J: IEEE, 2002.

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Bipolar/BiCMOS Circuits and Technology Meeting (1998 Minneapolis, Minn.). Proceedings of the 1998 Bipolar/BiCMOS Circuits and Technology Meeting: September 27-29, 1998. Piscataway, New Jersey: IEEE, 1998.

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8

International, Symposium on BI/CMOS (1st 1987 Philadelphia Pa ). Proceedings of the First International Symposium on BI/CMOS. Pennington, N.J. (10 S. Main St., Pennington 08534-2896): Electrochemical Society, 1989.

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Bipolar/BiCMOS Circuits and Technology Meeting (2000 Minneapolis, Minn.). Proceedings of the 2000 Bipolar/BiCMOS Circuits and Technology Meeting: September 24-26, 2000. Piscataway, New Jersey: IEEE, 2000.

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Ryter, Roland. Analysis and development of high voltage bipolar transistors for BiCMOS smart power applications. Konstanz: Hartung-Gorre, 1996.

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Book chapters on the topic "Complementary Bipolar integrated circuits"

1

Embabi, Sherif H. K., Abdellatif Bellaouar, and Mohamed I. Elmasry. "Bipolar CML Integrated Circuits." In Digital BiCMOS Integrated Circuit Design, 207–50. Boston, MA: Springer US, 1993. http://dx.doi.org/10.1007/978-1-4615-3174-6_6.

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2

Morant, M. J. "Bipolar Circuits for Digital ICs." In Integrated Circuit Design and Technology, 71–90. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4899-7198-2_5.

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Encinas, J. B. "Linear bipolar silicon PLL integrated circuits." In Phase Locked Loops, 102–23. Boston, MA: Springer US, 1993. http://dx.doi.org/10.1007/978-1-4615-3064-0_7.

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Krimmel, Eberhard F., Rudolf Hezel, Uwe Nohl, and Rainer Bohrer. "Silicon Nitride in Bipolar Device-Based Integrated Circuits." In Si Silicon, 239–42. Berlin, Heidelberg: Springer Berlin Heidelberg, 1991. http://dx.doi.org/10.1007/978-3-662-09901-8_19.

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Chang, Zhong Yuan, and Willy M. C. Sansen. "Noise in Integrated Circuits: — Mechanisms and Models." In Low-Noise Wide-Band Amplifiers in Bipolar and CMOS Technologies, 7–54. Boston, MA: Springer US, 1991. http://dx.doi.org/10.1007/978-1-4757-2126-3_2.

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Senani, R., D. R. Bhaskar, S. S. Gupta, and V. K. Singh. "Current-Feedback Op-Amps, Their Applications, Bipolar/CMOS Implementations and Their Variants." In Integrated Circuits for Analog Signal Processing, 61–84. New York, NY: Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4614-1383-7_3.

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Asbeck, P. M. "Heterojunction Bipolar Transistor Technology for High-Speed Integrated Circuits." In Picosecond Electronics and Optoelectronics, 32–37. Berlin, Heidelberg: Springer Berlin Heidelberg, 1985. http://dx.doi.org/10.1007/978-3-642-70780-3_5.

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Senani, Raj, A. K. Singh, Pragati Kumar, and R. K. Sharma. "Nullors, Their Bipolar and CMOS Implementations and Applications in Analog Circuit Synthesis and Design." In Integrated Circuits for Analog Signal Processing, 31–59. New York, NY: Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4614-1383-7_2.

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Renirie, W. C. M., K. J. Langen, and J. H. Huijsing. "Parallel Feedforward Class-AB Control Circuits for Low-Voltage Bipolar Rail-to-Rail Output Stages of Operational Amplifiers." In Low-Voltage Low-Power Analog Integrated Circuits, 37–48. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2283-6_4.

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Melville, Robert, Shahriar Moinian, Peter Feldmann, and Layne Watson. "Sframe: An Efficient System for Detailed DC Simulation of Bipolar Analog Integrated Circuits Using Continuation Methods." In Computer-Aided Design of Analog Circuits and Systems, 3–20. Boston, MA: Springer US, 1993. http://dx.doi.org/10.1007/978-1-4615-3252-1_2.

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Conference papers on the topic "Complementary Bipolar integrated circuits"

1

Drozdov, Dmitry G., Nikolay N. Prokopenko, Evgeny M. Savchenko, Andrey I. Grushin, and Pavel A. Dukanov. "Complementary JFETs Integrated into the Microwave Complementary Bipolar Double Self-Aligned Technology." In 2019 IEEE East-West Design & Test Symposium (EWDTS). IEEE, 2019. http://dx.doi.org/10.1109/ewdts.2019.8884448.

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2

Schwartz, W., H. Yasuda, Ph Steinmann, W. Boyd, W. Meinel, D. Hannaman, and S. Parsons. "BiCom3HV - A 36V Complementary SiGe Bipolar- and JFET-Technology." In 2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting. IEEE, 2007. http://dx.doi.org/10.1109/bipol.2007.4351835.

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3

Strachan, Andy. "Substrate Current Injection and Latchup in Complementary Vertical Bipolar Processes." In 2006 Bipolar/BiCMOS Circuits and Technology Meeting. IEEE, 2006. http://dx.doi.org/10.1109/bipol.2006.311112.

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4

Rodwell, Mark, Z. Griffith, N. Parthasarathy, U. Singisetti, V. Paidi, M. Urteaga, R. Pierson, P. Rowell, and B. Brar. "Frequency Limits of Bipolar Integrated Circuits." In 2006 IEEE MTT-S International Microwave Symposium Digest. IEEE, 2006. http://dx.doi.org/10.1109/mwsym.2006.249518.

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5

Fischer, G. G., J. Molina, and B. Tillack. "Comparative study of HBT ageing in a complementary SiGe:C BiCMOS technology." In 2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting - BCTM. IEEE, 2013. http://dx.doi.org/10.1109/bctm.2013.6798167.

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6

Lu, Yuan, Ramkumar Krithivasan, Wei-min Lance Kuo, Xiangtao Li, John D. Cressler, Hans Gustat, and Bernd Heinemann. "A 70 MHz - 4.1 GHz 5th-Order Elliptic gm-C Low-Pass Filter in Complementary SiGe Technology." In 2006 Bipolar/BiCMOS Circuits and Technology Meeting. IEEE, 2006. http://dx.doi.org/10.1109/bipol.2006.311118.

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7

Boissonnet, L., F. Judong, B. Vandelle, L. Rubaldo, P. Bouillon, D. Dutartre, A. Perrotin, et al. "A 0.13¿m thin SOI CMOS technology with low-cost SiGe:C HBTs and complementary high-voltage LDMOS." In 2006 Bipolar/BiCMOS Circuits and Technology Meeting. IEEE, 2006. http://dx.doi.org/10.1109/bipol.2006.311124.

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8

Cheng, Peng, Stephen Horst, Stanley Phillips, Sachin Seth, Richie Mills, John D. Cressler, Greg Cestra, Tracey Krakowski, Jeff A. Babcock, and Alan Buchholz. "An investigation of low-frequency noise in complementary SiGe HBTs on SOI." In 2010 IEEE Bipolar/BiCMOS Circuits and Technology Meeting - BCTM. IEEE, 2010. http://dx.doi.org/10.1109/bipol.2010.5667937.

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9

Lee, Zachary, Robert Zwingman, Jie Zheng, Will Cai, Paul Hurwitz, and Marco Racanelli. "A Modular 0.18 um Analog / RFCMOS Technology Comprising 32 GHz FT RF-LDMOS and 40V Complementary MOSFET Devices." In 2006 Bipolar/BiCMOS Circuits and Technology Meeting. IEEE, 2006. http://dx.doi.org/10.1109/bipol.2006.311116.

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10

Duvernay, J., F. Brossard, G. Borot, L. Boissonnet, B. Vandelle, L. Rubaldo, F. Deleglise, et al. "Development of a self-aligned pnp HBT for a complementary thin-SOI SiGeC BiCMOS technology." In 2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting. IEEE, 2007. http://dx.doi.org/10.1109/bipol.2007.4351833.

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