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Journal articles on the topic 'Complementary Bipolar integrated circuits'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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1

Kazior, Thomas E. "Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 372, no. 2012 (March 28, 2014): 20130105. http://dx.doi.org/10.1098/rsta.2013.0105.

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Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications.

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2

Lee, Changyeop, Gyuseong Cho, Troy Unruh, Seop Hur, and Inyong Kwon. "Integrated Circuit Design for Radiation-Hardened Charge-Sensitive Amplifier Survived up to 2 Mrad." Sensors 20, no. 10 (May 12, 2020): 2765. http://dx.doi.org/10.3390/s20102765.

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According to the continuous development of metal-oxide semiconductor (MOS) fabrication technology, transistors have naturally become more radiation-tolerant through steadily decreasing gate-oxide thickness, increasing the tunneling probability between gate-oxide and channel. Unfortunately, despite this radiation-hardened property of developed transistors, the field of nuclear power plants (NPPs) requires even higher radiation hardness levels. Particularly, total ionizing dose (TID) of approximately 1 Mrad could be required for readout circuitry under severe accident conditions with 100 Mrad around a reactor in-core required. In harsh radiating environments such as NPPs, sensors such as micro-pocket-fission detectors (MPFD) would be a promising technology to be operated for detecting neutrons in reactor cores. For those sensors, readout circuits should be fundamentally placed close to sensing devices for minimizing signal interferences and white noise. Therefore, radiation hardening ability is necessary for the circuits under high radiation environments. This paper presents various integrated circuit designs for a radiation hardened charge-sensitive amplifier (CSA) by using SiGe 130 nm and Si 180 nm fabrication processes with different channel widths and transistor types of complementary metal-oxide-semiconductor (CMOS) and bipolar CMOS (BiCMOS). These circuits were tested under γ–ray environment with Cobalt-60 of high level activity: 490 kCi. The experiment results indicate amplitude degradation of 2.85%–34.3%, fall time increase of 201–1730 ns, as well as a signal-to-noise ratio (SNR) of 0.07–11.6 dB decrease with irradiation dose increase. These results can provide design guidelines for radiation hardening operational amplifiers in terms of transistor sizes and structures.

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3

Ellinger, Frank, David Fritsche, Gregor Tretter, Jan Dirk Leufker, Uroschanit Yodprasit, and C. Carta. "Review of Millimeter-Wave Integrated Circuits With Low Power Consumption for High Speed Wireless Communications." Frequenz 71, no. 1-2 (January 1, 2017): 1–9. http://dx.doi.org/10.1515/freq-2016-0119.

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Abstract In this paper we review high-speed radio-frequency integrated circuits operating up to 210 GHz and present selected state-of-the-art circuits with leading-edge performance, which we have designed at our chair. The following components are discussed employing bipolar complementary metal oxide semiconductors (BiCMOS) technologies: a 200 GHz amplifier with 17 dB gain and around 9 dB noise figure consuming only 18 mW, a 200 GHz down mixer with 5.5 dB conversion gain and 40 mW power consumption, a 190 GHz receiver with 47 dB conversion gain and 11 dB noise figure and a 60 GHz power amplifier with 24.5 dBm output power and 12.9 % power added efficiency (PAE). Moreover, we report on a single-core flash CMOS analogue-to-digital converter (ADC) with 3 bit resolution and a speed of 24 GS/s. Finally, we discuss a 60 GHz on-off keying (OOK) BiCMOS transceiver chip set. The wireless transmission of data with 5 Gb/s at 42 cm distance between transmitter and receiver was verified by experiments. The complete transceiver consumes 396 mW.

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4

Hossain, Maruf, Ina Ostermay, Nils G. Weimann, Franz Josef Schmueckle, Johannes Borngraeber, Chafik Meliani, Marco Lisker, et al. "Performance study of a 248 GHz voltage controlled hetero-integrated source in InP-on-BiCMOS technology." International Journal of Microwave and Wireless Technologies 9, no. 2 (November 13, 2015): 259–68. http://dx.doi.org/10.1017/s1759078715001634.

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This paper presents the performance study of a 248 GHz voltage-controlled hetero-integrated signal source using indium phosphide (InP)-on-bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. The source consists of a voltage controlled oscillator (VCO) in 0.25 µm BiCMOS technology and a frequency multiplier in 0.8 µm transferred-substrate InP-heterojunction bipolar transistor technology, which is integrated on top of the BiCMOS monolithic microwave integrated circuit in a wafer-level based benzocyclobutene bonding process. The vertical transitions from BiCMOS to InP in this process exhibit broadband properties with insertion losses below 0.5 dB up to 325 GHz. The VCO operates at 82.7 GHz with an output power of 6 dBm and the combined circuit delivers −9 dBm at 248 GHz with 1.22% tuning range. The phase noise of the combined circuit is −85 dBc/Hz at 1 MHz offset. The measured output return loss of the hetero-integrated source is >10 dB within a broad frequency range. This result shows the potential of the hetero integrated process for THz frequencies.

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5

Božanić, Mladen, and Saurabh Sinha. "Emerging Transistor Technologies Capable of Terahertz Amplification: A Way to Re-Engineer Terahertz Radar Sensors." Sensors 19, no. 11 (May 29, 2019): 2454. http://dx.doi.org/10.3390/s19112454.

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This paper reviews the state of emerging transistor technologies capable of terahertz amplification, as well as the state of transistor modeling as required in terahertz electronic circuit research. Commercial terahertz radar sensors of today are being built using bulky and expensive technologies such as Schottky diode detectors and lasers, as well as using some emerging detection methods. Meanwhile, a considerable amount of research effort has recently been invested in process development and modeling of transistor technologies capable of amplifying in the terahertz band. Indium phosphide (InP) transistors have been able to reach maximum oscillation frequency (fmax) values of over 1 THz for around a decade already, while silicon-germanium bipolar complementary metal-oxide semiconductor (BiCMOS) compatible heterojunction bipolar transistors have only recently crossed the fmax = 0.7 THz mark. While it seems that the InP technology could be the ultimate terahertz technology, according to the fmax and related metrics, the BiCMOS technology has the added advantage of lower cost and supporting a wider set of integrated component types. BiCMOS can thus be seen as an enabling factor for re-engineering of complete terahertz radar systems, for the first time fabricated as miniaturized monolithic integrated circuits. Rapid commercial deployment of monolithic terahertz radar chips, furthermore, depends on the accuracy of transistor modeling at these frequencies. Considerations such as fabrication and modeling of passives and antennas, as well as packaging of complete systems, are closely related to the two main contributions of this paper and are also reviewed here. Finally, this paper probes active terahertz circuits that have already been reported and that have the potential to be deployed in a re-engineered terahertz radar sensor system and attempts to predict future directions in re-engineering of monolithic radar sensors.

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6

McDermott, H. "Cochlear Implant for Simultaneous Multichannel Stimulation." Annals of Otology, Rhinology & Laryngology 96, no. 1_suppl (January 1987): 67–69. http://dx.doi.org/10.1177/00034894870960s133.

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A new cochlear implant is described that can stimulate up to three bipolar electrode pairs simultaneously. It uses a scala tympani electrode array comprising 20 separate platinum ring electrodes. The bipolar mode of stimulation is used to minimize the spread of current in the cochlea. Nearly all of the electronics of the device are integrated into a single custom-designed large-scale integrated circuit. A prototype of the chip has been fabricated using an advanced complementary metal oxide semiconductor technology. Preliminary test results indicate that the device functions according to its specifications. The implant, which is still under development, will use a single transcutaneous inductive link to receive both controlling data and electric power from an external speech processor.

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7

Soref, Richard. "Applications of Silicon-Based Optoelectronics." MRS Bulletin 23, no. 4 (April 1998): 20–24. http://dx.doi.org/10.1557/s0883769400030220.

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Silicon-based optoelectronics is a diversified technology that has grown steadily but not exponentially over the past decade. Some applications—such as smart-pixel signal processing and chip-to-chip optical interconnects—have enjoyed impressive growth, whereas other applications have remained quiescent. A few important applications such as optical diagnosis of leaky metal-oxide-semiconductor-field-effect-transistor circuits, have appeared suddenly. Over the years, research and development has unveiled some unique and significant aspects of Si-based optoelectronics. The main limitation of this technology is the lack of practical silicon light sources—Si lasers and efficient Si light-emitting devices (LEDs)—though investigators are “getting close” to the LED.Silicon-based optoelectronics refers to the integration of photonic and electronic components on a Si chip or wafer. The photonics adds value to the electronics, and the electronics offers low-cost mass-production benefits. The electronics includes complementary-metal-oxide semiconductors (CMOS), very large-scale integration (VLSI), bipolar CMOS, SiGe/Si heterojunction bipolar transistors, and heterostructure field-effect transistors. In this discussion, we will use a loose definition of optoelectronics that includes photonic and optoelectronic integrated circuits (PICs and OEICs), Si optical benches, and micro-optoelectromechanical (MOEM) platforms. Optoelectronic chips and platforms are subsystems of computer systems, communication networks, etc. Silicon substrates feature a superior native oxide, in addition to excellent thermal, mechanical, and economic properties. Silicon wafers “shine” as substrates for PICs and OEICs.

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8

Tsai, Jung Hui, Shao Yen Chiu, Wen Shiung Lour, Chien Ming Li, Yi Zhen Wu, Ning Xing Su, and Yin Shan Huang. "InGaP/GaAs pnp Heterojunction Bipolar Transistor with δ-Doped Sheet between Base-Emitter Junction." Advanced Materials Research 47-50 (June 2008): 383–86. http://dx.doi.org/10.4028/www.scientific.net/amr.47-50.383.

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In this article, a novel InGaP/GaAs pnp δ-doped heterojunction bipolar transistor is first demonstrated. Though the valence band discontinuity at InGaP/GaAs heterojunction is relatively large, the addition of a δ-doped sheet between two spacer layers at the emitter-base junction effectively eliminates the potential spike and increases the confined barrier for electrons, simultaneously. Experimentally, a high current gain of 25 and an offset voltage of 100 mV are achieved. The offset voltage is much smaller than the conventional InGaP/GaAs pnp HBT. The proposed device could be used for linear amplifiers and low-power complementary integrated circuit applications.

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9

Sotner, Roman, Jan Jerabek, Ladislav Polak, Roman Prokop, and Vilem Kledrowetz. "Integrated Building Cells for a Simple Modular Design of Electronic Circuits with Reduced External Complexity: Performance, Active Element Assembly, and an Application Example." Electronics 8, no. 5 (May 22, 2019): 568. http://dx.doi.org/10.3390/electronics8050568.

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This paper introduces new integrated analog cells fabricated in a C035 I3T25 0.35-μm ON Semiconductor process suitable for a modular design of advanced active elements with multiple terminals and controllable features. We developed and realized five analog cells on a single integrated circuit (IC), namely a voltage differencing differential buffer, a voltage multiplier with current output in full complementary metal–oxide–semiconductor (CMOS) form, a voltage multiplier with current output with a bipolar core, a current-controlled current conveyor of the second generation with four current outputs, and a single-input and single-output adjustable current amplifier. These cells (sub-blocks of the manufactured IC device), designed to operate in a bandwidth of up to tens of MHz, can be used as a construction set for building a variety of advanced active elements, offering up to four independently adjustable internal parameters. The performances of all individual cells were verified by extensive laboratory measurements, and the obtained results were compared to simulations in the Cadence IC6 tool. The definition and assembly of a newly specified advanced active element, namely a current-controlled voltage differencing current conveyor transconductance amplifier (CC-VDCCTA), is shown as an example of modular interconnection of the selected cells. This device was implemented in a newly synthesized topology of an electronically linearly tunable quadrature oscillator. Features of this active element were verified by simulations and experimental measurements.

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10

Rong, Liang, Shan Jie Jia, Kui Hua Wu, Chun Mei Fu, and Qing Mao Fu. "The Effect of Dead Zone Mode on Electric Vehicle PWM Speed Control System." Advanced Materials Research 986-987 (July 2014): 1337–41. http://dx.doi.org/10.4028/www.scientific.net/amr.986-987.1337.

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To realize the electric vehicle braking energy recycling and driving smooth, bipolar PWM modulation mode is often adopted. To avoid the bridge arm shoot-through, a dead zone needs to be set in the complementary upper and lower bridge arm driving signal. Using hardware circuit dead zone setting has the advantages of simple setting and high reliability, is often used in the integrated driving module, however different dead zone mode has different influence on the inverter output voltage. This paper carried analysis on motor speed nonlinear problems caused by output voltage jump around a specific duty ratio in hardware dead zone setting mode, and gives the improvement of hardware circuit. Simulation and experimental results indicate that the method can well solve the output voltage jump in the vicinity of a specific duty ratio problem.

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11

Marcoux, J., J. Orchard-Webb, and J. F. Currie. "Complementary metal oxide semiconductor-compatible junction field-effect transistor characterization." Canadian Journal of Physics 65, no. 8 (August 1, 1987): 982–86. http://dx.doi.org/10.1139/p87-156.

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We report on the fabrication and electrical characterization of a vertical junction-gate field-effect transistor (JFET) that is compatible with all complementary metal oxide semiconductor (CMOS) technologies. It can be used as a buried load for an enhancement n-channel metal oxide semiconductor field-effect transistor (n-MOSFET), replacing the p-MOSFET within the standard CMOS inverter configuration and resulting in a 40% net area economy in standard cells. To be entirely CMOS process compatible, this JFET device differs from others in the literature in that dopant concentrations in the n substrates (1014) and in the p wells (1015) are substantially lower. For integrated-circuit applications, one seeks to use the JFET with the smallest area to minimize parasitic capacitances and to maximize switching speeds. However, at these concentration levels, the dc current–voltage characteristics depend critically on the lateral dimension of the JFET's square channel. Above 10 μm, the characteristics are pentode-like and similar to those of a classic MOSFET. Below 10 μm, the channel is naturally pinched-off, and for reverse gate bias, the small JFETs are triode-like. There is also a nonreciprocity between the source and the drain when the source-to-drain voltage polarity is changed, which is due to the distance between the channel and the electrode collecting the carriers. When its gate is forward-biased, the small JFETs behave as bipolar transistors. Depending on source-to-drain voltage polarities, I–V characteristics exhibit saturation effects caused by base-widening phenomena at the JFET's drain contact.

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12

Park, Ju-Chul, Stephen Krause, and Mohammed El-Ghor. "Effect of Thermal ramping rate on defect formation in oxygen-implanted silicon-on-insulator material." Proceedings, annual meeting, Electron Microscopy Society of America 50, no. 2 (August 1992): 1400–1401. http://dx.doi.org/10.1017/s0424820100131632.

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Integrated circuits on SIMOX (Separation by IMplantation of OXygen) have higher speed, radiation hardness, and higher temperature capability. Defects in the top Si layer inhibit bipolar applications and may affect CMOS(Complementary Metal-On-Semiconductor) device yield, operation and reliability. As-implanted SIMOX has many types of defects, including short stacking faults(SFs), multiply faulted defects(MFDs), and {113} defects. In annealed SIMOX, new defects form during the ramping cycle. The effect of thermal ramping rate on the development of new defects has received only limited study. In this work, the effects of rapid thermal annealing(RTA) and thermal ramp rate on defect density and structural change were studied.Two set of samples were prepared with different oxygen doses. First, one set of (100) Si wafers was implanted with a high dose of 1.8×l018cm−2 at 200 KeV at 620°C. A rapid thermal anneal(RTA) wafer was obtained from a lamp anneal for 1 minute at 1320°C using a ramp rate of 50°C/sec. A portion of this sample was then conventionally annealed in a tube furnace for 5 hours at 1320°C. Another set of (100) Si wafers was implanted with a low dose of 3×l015cm−2 at 25°C. Different samples were then annealed at 1250°C for 30 sec using three ramp rates of 50°C/sec, l°C/sec and 0.1°C/sec. Cross-sections of the samples were studied with conventional transmission electron microscopy (CTEM) at 200 KeV.

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13

Jeon, Jooyoung, and Myounggon Kang. "A Ruggedness Improved Mobile Radio Frequency Power Amplifier Module with Dynamic Impedance Correction by Software Defined Atomization." Electronics 8, no. 11 (November 8, 2019): 1317. http://dx.doi.org/10.3390/electronics8111317.

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A ruggedness improved multi-band radio frequency (RF) power amplifier (PA) module applicable to mobile handsets, which are required to survive against a serious load impedance change under extreme power and bias conditions, is presented. In this method, the load impedance of PA is adaptively adjusted with a digitally controlled impedance corrector to keep the PA safe by performing a load mismatch detection. The impedance mismatch detector, impedance corrector, and other RF switches were all integrated into a single integrated circuit (IC) using silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS). For the verification purpose, a 2-stage hetero junction bipolar transistor (HBT) PA module adopting this method was fabricated. At a frequency of 1915 MHz, a collector bias voltage of 4.2 V, and over a wider range of load impedance variation between a VSWR of 1 and a VSWR of 5.5, it did not fail. When this technique was not applied with a voltage standing wave ratio (VSWR) range of 1 to 4, it resulted in an acceptable RF performance degradation of 1% power added efficiency (PAE) in envelope tracking (ET) mode. Moreover, it survived at a bias voltage 1V larger than when the technique was not applied for the same mismatch condition.

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14

Lambrechts, Johannes W., and Saurabh Sinha. "Estimation of signal attenuation in the 60 GHZ band with an analog BiCMOS passive filter." International Journal of Microwave and Wireless Technologies 7, no. 6 (July 17, 2014): 645–53. http://dx.doi.org/10.1017/s1759078714000956.

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Prediction of millimeter(mm)-wave radio signals can be beneficial in recreating and repeating atmospheric conditions in a controlled, laboratory environment. A path-loss model has been proposed that accounts for free-space losses, oxygen absorption, reflection and diffraction losses, and rain-rate attenuation at mm-wave frequencies. Two variable passive low-pass-integrated circuit filter structures for attenuation in the 57–64 GHz unlicensed frequency band have been proposed, designed, simulated, prototyped in a 130-nm SiGe bipolar complementary metal-oxide semiconductor process, and measured. The filters are based on the Butterworth and Chebyshev low-pass filter topologies and investigate the possibility of using the structures to perform amplitude attenuation of mm-wave frequencies over a short distance. Both filters are designed and matched for direct coupling with equivalent circuit models of dipole antennas operating in this frequency band. Full integration therefore allows prediction of atmospheric losses on an analog, real-time, basis without the requirement of down-converting (sampling) to analyze high-frequency signals through a digital architecture. On-wafer probe measurements were performed to limit parasitic interference from bonding wires and enclosed packaging.

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15

Singh, Shakti, and James A. Cooper. "Bipolar Integrated Circuits in 4H-SiC." IEEE Transactions on Electron Devices 58, no. 4 (April 2011): 1084–90. http://dx.doi.org/10.1109/ted.2011.2107576.

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16

Baze, M. P., and A. H. Johnston. "Latchup Paths in Bipolar Integrated Circuits." IEEE Transactions on Nuclear Science 33, no. 6 (1986): 1499–504. http://dx.doi.org/10.1109/tns.1986.4334630.

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17

Rax, B. G., A. H. Johnston, and T. Miyahira. "Displacement damage in bipolar linear integrated circuits." IEEE Transactions on Nuclear Science 46, no. 6 (1999): 1660–65. http://dx.doi.org/10.1109/23.819135.

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18

Rencher, Mark. "Analog statistical simulation for bipolar integrated circuits." Analog Integrated Circuits and Signal Processing 1, no. 2 (October 1991): 157–64. http://dx.doi.org/10.1007/bf00161308.

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19

Tybrandt, Klas, Erik O. Gabrielsson, and Magnus Berggren. "Toward Complementary Ionic Circuits: ThenpnIon Bipolar Junction Transistor." Journal of the American Chemical Society 133, no. 26 (July 6, 2011): 10141–45. http://dx.doi.org/10.1021/ja200492c.

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20

BARNABY, H. J. "TOTAL DOSE EFFECTS IN LINEAR BIPOLAR INTEGRATED CIRCUITS." International Journal of High Speed Electronics and Systems 14, no. 02 (June 2004): 519–41. http://dx.doi.org/10.1142/s0129156404002491.

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Electronics systems that operate in space or strategic environments can be severely damaged by exposure to ionizing radiation. Space-based systems that utilize linear bipolar integrated circuits are particularly susceptible to radiation-induced damage because of the enhanced sensitivity of these circuits to the low rate of radiation exposure. The phenomenon of enhanced low-dose-rate sensitivity (ELDRS) demonstrates the need for a comprehensive understanding of the mechanisms of total dose effects in linear bipolar circuits. The majority of detailed bipolar total dose studies to date have focused on radiation effects mechanisms at either the process or transistor level. The goal of this text is to provide an overview of total dose mechanisms from the circuit perspective; in particular, the effects of transistor gain degradation on specific linear bipolar circuit parameters and the effects of circuit parameter degradation on select linear bipolar circuit applications.

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21

Zheng, Zheyang, Li Zhang, Wenjie Song, Sirui Feng, Han Xu, Jiahui Sun, Song Yang, Tao Chen, Jin Wei, and Kevin J. Chen. "Gallium nitride-based complementary logic integrated circuits." Nature Electronics 4, no. 8 (July 19, 2021): 595–603. http://dx.doi.org/10.1038/s41928-021-00611-y.

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22

Poulton, K., K. L. Knudesn, J. J. Corcoran, K. C. Wang, R. L. Pierson, R. B. Nubling, and M. C. F. Chang. "Thermal design and simulation of bipolar integrated circuits." IEEE Journal of Solid-State Circuits 27, no. 10 (1992): 1379–87. http://dx.doi.org/10.1109/4.156441.

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23

Buchner, Stephen, and Dale McMorrow. "Single-Event Transients in Bipolar Linear Integrated Circuits." IEEE Transactions on Nuclear Science 53, no. 6 (December 2006): 3079–102. http://dx.doi.org/10.1109/tns.2006.882497.

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24

Newcomer, F. M., R. van Berg, J. van der Spiegel, and H. H. Williams. "High-speed bipolar integrated circuits for SSC applications." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 283, no. 3 (November 1989): 806–9. http://dx.doi.org/10.1016/0168-9002(89)91463-0.

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25

Zetterling, Carl-Mikael, Anders Hallén, Raheleh Hedayati, Saleh Kargarrazi, Luigia Lanni, B. Gunnar Malm, Shabnam Mardani, et al. "Bipolar integrated circuits in SiC for extreme environment operation." Semiconductor Science and Technology 32, no. 3 (February 13, 2017): 034002. http://dx.doi.org/10.1088/1361-6641/aa59a7.

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26

Gotzfried, R., F. Beisswanger, and S. Gerlach. "Design of RF integrated circuits using SiGe bipolar technology." IEEE Journal of Solid-State Circuits 33, no. 9 (1998): 1417–22. http://dx.doi.org/10.1109/4.711341.

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27

Holden, A. J., C. G. Eddison, J. G. Metcalfe, and R. C. Hayes. "Bipolar heterojunction transistor integrated circuits: design, modelling and characterisation." Electronics Letters 22, no. 15 (1986): 815. http://dx.doi.org/10.1049/el:19860559.

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28

Liu, Yuanda, and Kah-Wee Ang. "Monolithically Integrated Flexible Black Phosphorus Complementary Inverter Circuits." ACS Nano 11, no. 7 (July 3, 2017): 7416–23. http://dx.doi.org/10.1021/acsnano.7b03703.

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29

Lanni, L., B. G. Malm, C. M. Zetterling, and M. Östling. "A 4H-SiC Bipolar Technology for High-temperature Integrated Circuits." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, HITEN (January 1, 2013): 000282–89. http://dx.doi.org/10.4071/hiten-wp13.

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A 4H-SiC bipolar technology suitable for high-temperature integrated circuits is tested with two interconnect systems based on Aluminium and Platinum. Successful operation of low-voltage bipolar transistor and digital integrated circuits based on emitter coupled logic (ECL) is reported from 27 up to 500 °C for both the metallization systems. When operated on −15 V supply voltage, Aluminium and Platinum OR-NOR gates showed stable noise margins of about 1 V and asymmetric propagation delays of about 200 and 700 ns in the whole temperature range for both OR and NOR output. The performance of Aluminium and Platinum interconnect were evaluated by performing accelerated electromigration tests at 300 °C with current density of about 1 MA/cm2 on contact chains consisting of 10 integrated resistors.

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Lanni, L., B. G. Malm, C. M. Zetterling, and M. Östling. "A 4H-SiC Bipolar Technology for High-Temperature Integrated Circuits." Journal of Microelectronics and Electronic Packaging 10, no. 4 (October 1, 2013): 155–62. http://dx.doi.org/10.4071/imaps.390.

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A 4H-SiC bipolar technology suitable for high-temperature integrated circuits is tested with two interconnect systems based on aluminum and platinum. Successful operation of low-voltage bipolar transistors and digital integrated circuits based on emitter coupled logic (ECL) is reported from 27°C up to 500°C for both the metallization systems. When operated on −15 V supply voltage, aluminum and platinum interconnect OR-NOR gates showed stable noise margins of about 1 V and asymmetric propagation delays of about 200 and 700 ns in the whole temperature range for both OR and NOR output. The performance of aluminum and platinum interconnects was evaluated by performing accelerated electromigration tests at 300°C with current density of about 1 MA/cm2 on contact chains consisting of 10 integrated resistors. Although in both cases the contact chains failed after less than one hour, different failure mechanisms were observed for the two metallization systems: electromigration for the aluminum system and poor step coverage and via filling for the platinum system.

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31

Asbeck, P. M., M. F. Chang, K. C. Wang, D. L. Miller, G. J. Sullivan, N. H. Sheng, E. Sovero, and J. A. Higgins. "Heterojunction bipolar transistors for microwave and millimeter-wave integrated circuits." IEEE Transactions on Electron Devices 34, no. 12 (December 1987): 2571–79. http://dx.doi.org/10.1109/t-ed.1987.23356.

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32

Johnston, A. H., R. T. Swimm, and D. O. Thorbourn. "Total Dose Effects on Bipolar Integrated Circuits at Low Temperature." IEEE Transactions on Nuclear Science 59, no. 6 (December 2012): 2995–3003. http://dx.doi.org/10.1109/tns.2012.2219592.

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Asbeck, P. M., M. F. Chang, K. C. Wang, D. L. Miller, G. J. Sullivan, N. H. Sheng, E. Sovero, and J. A. Higgins. "Heterojunction Bipolar Transistors for Microwave and Millimeter-Wave Integrated Circuits." IEEE Transactions on Microwave Theory and Techniques 35, no. 12 (December 1987): 1462–68. http://dx.doi.org/10.1109/tmtt.1987.1133876.

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34

Ahlgren, D. C., S. J. Jeng, D. Nguyen-Ngoc, K. Stein, D. Sunderland, M. Gilbert, J. Malinowski, et al. "Si-Ge heterojunction bipolar technology for high-speed integrated circuits." Canadian Journal of Physics 74, S1 (December 1, 1996): 159–66. http://dx.doi.org/10.1139/p96-851.

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This review discusses the fundamentals of SiGe epitaxial base heterojunction bipolar transistor (HBT) technology that have been developed for use in analog and mixed-signal applications in the 1–20 GHz range. The basic principles of operation of the graded base SiGe HBT are reviewed. These principles are then used to explore the design optimization for analog applications. Device results are presented that illustrate some important trade-offs in device design. A discussion of the use of UHV/CVD for the deposition of the epitaxial base profile is followed by an overview of the integrated process. This process, which has been installed on 200 mm wafers in IBM's Advanced Semiconductor Technology Center in Hopewell Junction, N.Y., also includes a full range of support devices. The process has demonstrated SiGe HBT performance, reliability, and yield in a CMOS fabrication with the addition of only one tool for UHV/CVD deposition of the epi-base and, with minimal additional process steps, can be used to fabricate full BiCMOS designs. This paper concludes with a discussion of high-performance circuits fabricated to date, including ECL ring'oscillators, power amplifiers, low-noise amplifiers, voltage-controlled oscillators, and finally a 12-bit DAC that features nearly 3000 SiGe HBT devices demonstrating medium-scale integration.

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Borel, T., F. Roig, A. Michez, B. Azais, S. Danzeca, N. J. H. Roche, F. Bezerra, P. Calvel, and L. Dusseau. "Atypical Effect of Displacement Damage on LM124 Bipolar Integrated Circuits." IEEE Transactions on Nuclear Science 65, no. 1 (January 2018): 71–77. http://dx.doi.org/10.1109/tns.2017.2772901.

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36

Rein, H. M. "Silicon bipolar integrated circuits for multigigabit-per-second lightwave communications." Journal of Lightwave Technology 8, no. 9 (1990): 1371–78. http://dx.doi.org/10.1109/50.59167.

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Blynskii, V. I., V. A. Emel’yanov, E. S. Golub, A. M. Lemeshevskaya, and S. V. Shvedov. "Spectral sensitivity of IR photodetectors in monolithic bipolar integrated circuits." Journal of Applied Spectroscopy 75, no. 4 (July 2008): 608–11. http://dx.doi.org/10.1007/s10812-008-9089-3.

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38

Crone, B., A. Dodabalapur, Y. Y. Lin, R. W. Filas, Z. Bao, A. LaDuca, R. Sarpeshkar, H. E. Katz, and W. Li. "Large-scale complementary integrated circuits based on organic transistors." Nature 403, no. 6769 (February 2000): 521–23. http://dx.doi.org/10.1038/35000530.

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Chen, Li, Si Li, Xuewei Feng, Lin Wang, Xin Huang, Benjamin C. K. Tee, and Kah-Wee Ang. "Gigahertz Integrated Circuits Based on Complementary Black Phosphorus Transistors." Advanced Electronic Materials 4, no. 9 (June 28, 2018): 1800274. http://dx.doi.org/10.1002/aelm.201800274.

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40

Kiely, P. A., G. W. Taylor, D. P. Docter, P. A. Evaldsson, T. A. Vang, B. Tell, and K. F. Brown-Goebeler. "Complementary transistor technology for use in optoelectronic integrated circuits." IEE Proceedings G Circuits, Devices and Systems 140, no. 4 (1993): 279. http://dx.doi.org/10.1049/ip-g-2.1993.0046.

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Kim, Dae-Hyeong, Won Mook Choi, Jong-Hyun Ahn, Hoon-Sik Kim, Jizhou Song, Yonggang Huang, Zhuangjian Liu, Chun Lu, Chan Ghee Koh, and John A. Rogers. "Complementary metal oxide silicon integrated circuits incorporating monolithically integrated stretchable wavy interconnects." Applied Physics Letters 93, no. 4 (July 28, 2008): 044102. http://dx.doi.org/10.1063/1.2963364.

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42

Barber, H. D. "Bipolar device technology challenge and opportunity." Canadian Journal of Physics 63, no. 6 (June 1, 1985): 683–92. http://dx.doi.org/10.1139/p85-105.

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Silicon bipolar device technologies provided 65% of the world's integrated circuits in 1983. Where low noise, high current, low or high voltage, high speed or low cost are required, bipolar technologies are used. This paper will review the present status of bipolar device technologies, which make possible 100-ps gate-propagation delays, 150-μm2 gate areas, 1-GHz bandwidth amplifiers, on-chip control of over 1-A, 350-V operation, 14-GHz fT's and 10-ns. analogue-to-8-bit digital conversion. These devices are realized because of advances in isolation techniques, chemical-vapor deposition, photolithography, diffusion, ion implantation, conductor–contact interconnection technology, etching processes, and materials preparation. This paper will discuss some of the fundamental problems, modelling difficulties, and technological barriers that will impact the future development of bipolar integrated circuits.

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van der Pol, Jacob A., Han J. Gerritsen, Rene T. H. Rongen, Peter P. M. C. Groeneveld, Peter W. Ragay, and Henk A. van den Hurk. "Reliability issues in 650V high voltage bipolar-CMOS-DMOS integrated circuits." Microelectronics Reliability 37, no. 10-11 (October 1997): 1723–26. http://dx.doi.org/10.1016/s0026-2714(97)00148-0.

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Johnston, A. H., R. T. Swimm, and D. O. Thorbourn. "Charge Yield at Low Electric Fields: Considerations for Bipolar Integrated Circuits." IEEE Transactions on Nuclear Science 60, no. 6 (December 2013): 4488–97. http://dx.doi.org/10.1109/tns.2013.2283515.

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Wills, G. N. "FAILURE ANALYSIS ON BIPOLAR INTEGRATED CIRCUITS ATTRIBUTES DAMAGE TO ELECTROSTATIC DISCHARGE." Quality and Reliability Engineering International 2, no. 4 (October 1986): 247–54. http://dx.doi.org/10.1002/qre.4680020407.

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Lee, Jeong-Youb, Shakti Singh, and James A. Cooper. "Demonstration and Characterization of Bipolar Monolithic Integrated Circuits in 4H-SiC." IEEE Transactions on Electron Devices 55, no. 8 (August 2008): 1946–53. http://dx.doi.org/10.1109/ted.2008.926681.

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Xu, Kaikai, Kingsley A. Ogudo, Jean-Luc Polleux, Carlos Viana, Zhengfei Ma, Zebin Li, Qi Yu, Guannpyng Li, and Lukas W. Snyman. "Light Emitting Devices in Si CMOS and RF Bipolar Integrated Circuits." LEUKOS 12, no. 4 (February 12, 2016): 203–12. http://dx.doi.org/10.1080/15502724.2015.1134333.

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Runge, K., W. I. Way, M. Bagheri, J. L. Gimlett, D. Clawin, N. K. Cheung, D. J. Millicker, D. Daniel, and C. Snapp. "Silicon bipolar integrated circuits for multi-Gb/second optical communication systems." IEEE Journal on Selected Areas in Communications 9, no. 5 (June 1991): 636–44. http://dx.doi.org/10.1109/49.87630.

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Johnston, A. H., G. M. Swift, and B. G. Rax. "Total dose effects in conventional bipolar transistors and linear integrated circuits." IEEE Transactions on Nuclear Science 41, no. 6 (December 1994): 2427–36. http://dx.doi.org/10.1109/23.340598.

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Johnston, A. H., B. G. Rax, and C. I. Lee. "Enhanced damage in linear bipolar integrated circuits at low dose rate." IEEE Transactions on Nuclear Science 42, no. 6 (1995): 1650–59. http://dx.doi.org/10.1109/23.488762.

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