Relevant bibliographies by topics / Complementary Mixed signal circuits

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Complementary Mixed signal circuits'

Author: Grafiati
Published: 4 June 2021
Last updated: 16 February 2022

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Journal articles on the topic "Complementary Mixed signal circuits"

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Zhao, Chun, Ce Zhou Zhao, and Bin Da. "A Novel Technique for Arithmetic Elements Standard Cell Library Establishment Based on Tanner Tools." Advanced Materials Research 569 (September 2012): 273–76. http://dx.doi.org/10.4028/www.scientific.net/amr.569.273.

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The economic and efficient accomplishment of an application-specific integrated circuit design depends heavily upon the choice of the library. Therefore, it is important to build library that full fills the design requirement. Tanner Tools is a set of software for designing integrated circuits. The great advantage of Tanner is that it can provide a complete circuit design tools in desktop computers. The paper aims to create a standard cell library establishment on the 0.5 micro complementary metal–oxide–semiconductor mixed signal process based on the Tanner Tools.
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Chen, Ethan, and Vanessa Chen. "Statistical RF/Analog Integrated Circuit Design Using Combinatorial Randomness for Hardware Security Applications." Mathematics 8, no. 5 (2020): 829. http://dx.doi.org/10.3390/math8050829.

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While integrated circuit technologies keep scaling aggressively, analog, mixed-signal, and radio-frequency (RF) circuits encounter challenges by creating robust designs in advanced complementary metal–oxide–semiconductor (CMOS) processes with the diminishing voltage headroom. The increasing random mismatch of smaller feature sizes in leading-edge technology nodes severely limit the benefits of scaling for (RF)/analog circuits. This paper describes the details of the combinatorial randomness by statistically selecting device elements that relies on the significant growth in subsets number of combinations. The randomness can be utilized to provide post-manufacturing reconfiguration of the selectable circuit elements to achieve required specifications for ultra-low-power systems. The calibration methodology is demonstrated with an ultra-low-voltage chaos-based true random number generator (TRNG) for energy-constrained Internet of things (IoT) devices in the secure communications.
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Zaleski, Dariusz, and Romuald Zielonko. "Two-functional µBIST for Testing and Self-Diagnosis of Analog Circuits in Electronic Embedded Systems." ACTA IMEKO 3, no. 4 (2014): 10. http://dx.doi.org/10.21014/acta_imeko.v3i4.150.

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The paper concerns the testing of analog circuits and blocks in mixed-signal Electronic Embedded Systems (EESs), using the Built-in Self-Test (BIST) technique. An integrated, two-functional, embedded microtester (µBIST) based on reuse of signal blocks already present in an EES, such as microprocessors, memories, ADCs, DACs, is presented. The novelty of the µBIST solution is its extended functionality. It can perform 2 testing functions: functional testing and fault diagnosis on the level of localization of a faulty element. For functional testing the Complementary Signals (CSs), and for fault diagnosis the Simulation Before Test (SBT) vocabulary techniques have been used. In the fault vocabulary the graphical signatures in the form of identification curves in multidimensional spaces have been applied.
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Rajendran, Selvakumar, Arvind Chakrapani, Srihari Kannan, and Abdul Quaiyum Ansari. "A Research Perspective on CMOS Current Mirror Circuits: Configurations and Techniques." Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) 14, no. 4 (2021): 377–97. http://dx.doi.org/10.2174/2352096514666210127140831.

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Background: Immense growth in the field of VLSI technology is fuelled by its feasibility to realize analog circuits in μm and nm technology. The current mirror (CM) is a basic building block used to enhance performance characteristics by constructing complex analog/mixed-signal circuits like amplifier, data converters and voltage level converters. In addition, the current mirror finds diverse applications from biasing to current-mode signal processing. Methods: In this paper, the Complementary Metal Oxide Semiconductor (CMOS) technologybased current mirror (CM) circuits are discussed with their advantages and disadvantages accompanied by the performance analysis of different parameters. It also briefs various techniques which are employed for improvising the current mirror performance like gain boosting and bandwidth extension. Besides, this paper lists the CMs that use different types of MOS devices like Floating Gate MOS, Bulk-driven MOS, and Quasi-Floating Gate MOS. As a result, the paper performs a detailed review of CMOS Current mirrors and their techniques. Results: Basic CM circuits that can act as building blocks in the VLSI circuits are simulated using 0.25 μm, BSIM and Level 1 technology. In addition, various devices based CMs are investigated and compared. Conclusion: The comprehensive discussion shows that the current mirror plays a significant role in analog/mixed-signal circuits design to realize complex systems for low-power biomedical and wireless applications.
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Ito, A., M. D. Church, Choong-Sun Rhee, et al. "A fully complementary BiCMOS technology for 10 V mixed-signal circuit applications." IEEE Transactions on Electron Devices 41, no. 7 (1994): 1149–60. http://dx.doi.org/10.1109/16.293342.

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Elmezayen, Mohamed R., Wei Hu, Amr M. Maghraby, Islam T. Abougindia, and Suat U. Ay. "Accurate Analysis and Design of Integrated Single Input Schmitt Trigger Circuits." Journal of Low Power Electronics and Applications 10, no. 3 (2020): 21. http://dx.doi.org/10.3390/jlpea10030021.

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Schmitt trigger (ST) circuits are widely used integrated circuit (IC) blocks with hysteretic input/output (I/O) characteristics. Like the I/O characteristics of a living neuron, STs reject noise and provide stability to systems that they are deployed in. Indeed, single-input/single-output (SISO) STs are likely candidates to be the core unit element in artificial neural networks (ANNs) due not only to their similar I/O characteristics but also to their low power consumption and small silicon footprints. This paper presents an accurate and detailed analysis and design of six widely used complementary metal-oxide-semiconductor (CMOS) SISO ST circuits. The hysteresis characteristics of these ST circuits were derived for hand calculations and compared to original design equations and simulation results. Simulations were carried out in a well-established, 0.35 μm/3.3 V, analog/mixed-signal CMOS process. Additionally, simulations were performed using a wide range of supplies and process variations, but only 3.3 V supply results are presented. Most of the new design equations provide better accuracy and insights, as broad assumptions of original derivations were avoided.
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Francis, A. Matthew, Jim Holmes, Nick Chiolino, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. "High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, HiTEC (2016): 000242–48. http://dx.doi.org/10.4071/2016-hitec-242.

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Abstract In the last decade, significant effort has been expended towards the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field effect transistors and metal-oxide-semiconductor field effect transistors have been pursued and demonstrated. More recently1,2, advances in low-power complementary MOS devices have enabled the development of highly-integrated digital, analog and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) for extended periods (up to 100 hours) of several building block circuits will be presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at these extreme temperatures for any period of time. Based on these results, Venus nominal temperature (470°C) SPICE m°dels and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller in SiC-CMOS, with an eye for Venus as well as terrestrial applications.
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Holmes, Jim, A. Matthew Francis, Ian Getreu, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. "Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application." Journal of Microelectronics and Electronic Packaging 13, no. 4 (2016): 143–54. http://dx.doi.org/10.4071/imaps.527.

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In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circuits for extended periods (up to 100 h) are presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at extreme temperatures for any period. Based on these results, Venus nominal temperature (470°C) transistor models and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller. A 16-bit microcontroller, based on the OpenMSP 16-bit core, is demonstrated through physical design and simulation in SiC-CMOS, with an eye for Venus as well as terrestrial applications.
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D., Vaithiyanathan, Megha Singh Kurmi, Alok Kumar Mishra, and Britto Pari J. "Performance analysis of multi-scaling voltage level shifter for low-power applications." World Journal of Engineering 17, no. 6 (2020): 803–9. http://dx.doi.org/10.1108/wje-02-2020-0043.

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Purpose In complementary metal-oxide-semiconductor (CMOS) logic circuits, there is a direct square proportion of supply voltage on dynamic power. If the supply voltage is high, then more amount of energy will be consumed. Therefore, if a low voltage supply is used, then dynamic power will also be reduced. In a mixed signal circuit, there can be a situation when lower voltage circuitry has to drive large voltage circuitry. In such a case, P-type metal-oxide-semiconductor of high-voltage circuitry may not be switched off completely by applying a low voltage as input. Therefore, there is a need for level shifter where low-voltage and high-voltage circuits are connected. In this paper the multi-scaling voltage level shifter is presented which overcomes the contention problems and suitable for low-power applications. Design/methodology/approach The voltage level shifter circuit is essential for digital and analog circuits in the on-chip integrated circuits. The modified voltage level shifter and reported energy-efficient voltage level shifter have been optimally designed to be functional in all process voltage and temperature corners for VDDH = 5V, VDDL = 2V and the input frequency of 5 MHz. The modified voltage level shifter and reported shifter circuits are implemented using Cadence Virtuoso at 90 nm CMOS technology and the comparison is made based on speed and power consumed by the circuit. Findings The voltage level shifter circuit discussed in this paper removes the contention problem that is present in conventional voltage level shifter. Moreover, it has the capability for up and down conversion and reduced power and delay as compared to conventional voltage level shifter. The efficiency of the circuit is improved in two ways, first, the current of the pull-up device is reduced and second, the strength of the pull-down device is increased. Originality/value The modified level shifter is faster for switching low input voltage to high output voltage and also high input voltage to low output voltage. The average power consumption for the multi-scaling voltage level shifter is 259.445 µW. The power consumption is very less in this technique and it is best suitable for low-power applications.
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Kodate, Junichi, Mitsuru Harada, and Tsuneo Tsukahara. "Suppression of Substrate Crosstalk in Mixed-Signal Complementary MOS Circuits Using High-Resistivity SIMOX (Separation by IMplanted OXygen) Wafers." Japanese Journal of Applied Physics 39, Part 1, No. 4B (2000): 2256–60. http://dx.doi.org/10.1143/jjap.39.2256.

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Dissertations / Theses on the topic "Complementary Mixed signal circuits"

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Xuan, Xiangdong. "Analysis and design of reliable mixed-signal CMOS circuits." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-08032004-185515/unrestricted/xuan%5Fxiangdong%5F200412%5Fphd.pdf.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.<br>Singh, Adit, Committee Member ; Chatterjee, Abhijit, Committee Chairl May, Gary, Committee Member ; Keezer, David, Committee Member ; Swaminathan, Madhavan, Committee Member. Vita. Includes bibliographical references.
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Buchanan, Brent E. "A mixed-signal CMOS VLSI image convolution circuit using error spectrum shaping." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15420.

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Tabler, John A. "An integrated adaptive bias solution for zero passive component count high-performance mixed-signal ICs." Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/13339.

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al-Sarʻāwī, Said Fares. "Design techniques for low power mixed analog-digital circuits with application to smart wireless systems /." Title page, contents and abstract only, 2003. http://web4.library.adelaide.edu.au/theses/09PH/09pha461.pdf.

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Bartholomew, David Ray. "Design of a High Speed Mixed Signal CMOS Mutliplying Circuit." Diss., CLICK HERE for online access, 2004. http://contentdm.lib.byu.edu/ETD/image/etd362.pdf.

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Ozalevli, Erhan. "Exploiting Floating-Gate Transistor Properties in Analog and Mixed-Signal Circuit Design." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/14048.

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With the downscaling trend in CMOS technology, it has been possible to utilize the advantages of high element densities in VLSI circuits and systems. This trend has readily allowed digital circuits to predominate VLSI implementations due to their ease of scaling. However, high element density in integrated circuit technology has also entailed a decrease in the power consumption per functional circuit cell for the use of low-power and reconfigurable systems in portable equipment. Analog circuits have the advantage over digital circuits in designing low-power and compact VLSI circuits for signal processing systems. Also, analog circuits have been employed to utilize the wide dynamic range of the analog domain to meet the stringent signal-to-noise-and-distortion requirements of some signal processing applications. However, the imperfections and mismatches of CMOS devices can easily deteriorate the performance of analog circuits when they are used to realize precision and highly linear elements in the analog domain. This is mainly due to the lack of tunability of the analog circuits that necessitates the use of special trimming or layout techniques. These problems can be alleviated by making use of the analog storage and capacitive coupling capabilities of floating-gate transistors. In this research, tunable resistive elements and analog storages are built using floating-gate transistors to be incorporated into signal processing applications. Tunable linearized resistors are designed and implemented in CMOS technology, and are employed in building a highly linear amplifier, a transconductance multiplier, and a binary-weighted resistor digital-to-analog converter. Moreover, a tunable voltage reference is designed by utilizing the analog storage feature of the floating-gate transistor. This voltage reference is used to build low-power, compact, and tunable/reconfigurable voltage-output digital-to-analog converter and distributed arithmetic architecture.
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Vakili-Amini, Babak. "A Mixed-Signal Low-Noise Sigma-Delta Interface IC for Integrated Sub-Micro-Gravity Capacitive SOI Accelerometers." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/10437.

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This dissertation presents the design and development of a mixed-signal low noise second-order integrated circuit (IC) for the open-loop and closed-loop operation of integrated capacitive micro- and nano-gravity accelerometers. The micromechanical accelerometers are fabricated in thick (less than 100 m) silicon-on-insulator (SOI) substrates. The IC provides the 1-bit digital output stream and has the versatility of interfacing sensors with different sensitivities while maintaining minimum power consumption (less than 5 mW) and maximum dynamic range (90 dB). A fully-differential sampled-data scheme is deployed with the ability of low-frequency noise reduction through the use of correlated double sampling (CDS) scheme. In this work, the measured resolution of the closed-loop CMOS-SOI accelerometer system, in the presence of high background accelerations, is in the micro-g (g: gravity) range. In this design, a second-order SC modulator is cascaded with the accelerometer and the front-end amplifier. The accelerometer operates in air and is designed for non-peaking response with a BW-3dB of 500 Hz. A 22 dB improvement in noise and hence dynamic range is achieved with a sampling clock of 40 kHz corresponding to a low oversampling ratio (OSR) of 40. The interface IC consumed a current of 1.5 mA from a supply of 3 V.
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Moen, Kurt Andrew. "Predictive modeling of device and circuit reliability in highly scaled CMOS and SiGe BiCMOS technology." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/44700.

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The advent of high-frequency silicon-based technologies has enabled the design of mixed-signal circuits that incorporate analog, RF, and digital circuit components to build cost-effective system-on-a-chip solutions. Emerging applications provide great incentive for continued scaling of transistor performance, requiring careful attention to mismatch, noise, and reliability concerns. If these mixed-signal technologies are to be employed within space-based electronic systems, they must also demonstrate reliability in radiation-rich environments. SiGe BiCMOS technology in particular is positioned as an excellent candidate to satisfy all of these requirements. The objective of this research is to develop predictive modeling tools that can be used to design new mixed-signal technologies and assess their reliability on Earth and in extreme environments. Ultimately, the goal is to illuminate the interaction of device- and circuit-level reliability mechanisms and establish best practices for modeling these effects in modern circuits. To support this objective, several specific areas have been targeted first, including a TCAD-based approach to identify performance-limiting regions in SiGe HBTs, measurement and modeling of carrier transport parameters that are essential for predictive TCAD, and measurement of device-level single-event transients to better understand the physical origins and implications for device design. These tasks provide the foundation for the bulk of this research, which addresses circuit-level reliability challenges through the application of novel mixed-mode TCAD techniques. All of the individual tasks are tied together by a guiding theme: to develop a holistic understanding of the challenges faced by emerging broadband technologies by coordinating results from material, device, and circuit studies.
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Terlemez, Bortecene. "Oscillation Control in CMOS Phase-Locked Loops." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4841.

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Recent advances in voltage-controlled oscillator (VCO) design and the trend of CMOS processing indicate that the oscillator control is quickly becoming one of the forefront problems in high-frequency and low-phase-noise phase-locked loop (PLL) design. This control centric study explores the limitations and challenges in high-performance analog charge-pump PLLs when they are extended to multiple gigahertz applications. Several problems with performance enhancement and precise oscillator control using analog circuits in low-voltage submicron CMOS processes, coupled with the fact that analog (or semi-digital) oscillators having various advantages over their digitally controlled counterparts, prompted the proposal of the digitally-controlled phase-locked loop. This research, then, investigates a class of otherwise analog PLLs that use a digital control path for driving a current-controlled oscillator. For this purpose, a novel method for control digitization is described where trains of pulses code the phase/frequency comparison information rather than the duration of the pulses: Pulse-Stream Coded Phase-Locked Loop (psc-PLL). This work addresses issues significant to the design of future PLLs through a comparative study of the proposed digital control path topology and improved cutting-edge charge-pump PLLs.
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Figueroa, Toro Miguel E. "Adaptive signal processing and correlational learning in mixed-signal VLSI /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6856.

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Books on the topic "Complementary Mixed signal circuits"

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CMOS: Mixed signal circuit design. 2nd ed. IEEE Press, 2009.

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CMOS: Mixed signal circuit design. Wiley, 2002.

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Baker, R. Jacob. CMOS: Mixed signal circuit design. 2nd ed. John Wiley & Sons, 2009.

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Baker, R. Jacob. CMOS: Mixed signal circuit design. 2nd ed. IEEE Press, 2009.

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Adaptive techniques for mixed signal system on chip. Springer, 2007.

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Handkiewicz, Andrzej. Mixed-signal systems: A guide to CMOS circuit design. IEEE Press, 2002.

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service), SpringerLink (Online, ed. Variation Aware Analog and Mixed-Signal Circuit Design in Emerging Multi-Gate CMOS Technologies. Springer Netherlands, 2010.

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Southwest, Symposium on Mixed-Signal Design (2000 San Diego Calif ). 2000 Southwest Symposium on Mixed-Signal Design: SSMSD : February 27-29, 2000, San Diego, California, U.S.A. IEEE, 2000.

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University of Arizona Mixed-Signal Design Consortium. and IEEE Solid-State Circuits Society, eds. 2001 Southwest Symposium on Mixed-Signal Design: SSMSD : February 25-27, 2001, Austin, Texas, U.S.A. IEEE, 2001.

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Paulo, Martins Rui, and SpringerLink (Online service), eds. High-/Mixed-Voltage Analog and RF Circuit Techniques for Nanoscale CMOS. Springer US, 2012.

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Book chapters on the topic "Complementary Mixed signal circuits"

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Abdinia, Sahel, Arthur H. M. van Roermund, and Eugenio Cantatore. "Complementary OTFT Technology." In Analog Circuits and Signal Processing. Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-21188-6_2.

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Elbadry, Mohammad, and Ramesh Harjani. "QVCO with Complementary Coupling." In Analog Circuits and Signal Processing. Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-13788-9_3.

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Schneider, Birger. "Mixed-Signal Test." In Test and Design-for-Testability in Mixed-Signal Integrated Circuits. Springer US, 2004. http://dx.doi.org/10.1007/978-0-387-23521-9_2.

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Abdinia, Sahel, Arthur H. M. van Roermund, and Eugenio Cantatore. "Analogue and Mixed-Signal Circuit Design." In Analog Circuits and Signal Processing. Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-21188-6_5.

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Zhao, Bin, and James A. Hutchby. "Mixed-Signal Technologies and Integrated Circuits." In Guide to State-of-the-Art Electron Devices. John Wiley & Sons, Ltd, 2013. http://dx.doi.org/10.1002/9781118517543.ch12.

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Loukusa, Veikko. "Behavioral Testing of Mixed-Signal Circuits." In Test and Design-for-Testability in Mixed-Signal Integrated Circuits. Springer US, 2004. http://dx.doi.org/10.1007/978-0-387-23521-9_6.

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Salmani, Hassan. "Hardware Trojans in Analog and Mixed-Signal Integrated Circuits." In Trusted Digital Circuits. Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-79081-7_9.

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Kundert, Ken. "Top-Down Design of Mixed-Signal Circuits." In Analog Circuit Design. Springer US, 2000. http://dx.doi.org/10.1007/978-1-4757-3198-9_9.

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Bizzarri, Federico, Angelo Brambilla, Giambattista Gruosso, and Giancarlo Storti Gajani. "Steady State Simulation of Mixed Analog/Digital Circuits." In Integrated Circuits for Analog Signal Processing. Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4614-1383-7_11.

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Eick, Michael, and Helmut Graeb. "Towards Automatic Structural Analysis of Mixed-Signal Circuits." In Analog/RF and Mixed-Signal Circuit Systematic Design. Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-36329-0_1.

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Conference papers on the topic "Complementary Mixed signal circuits"

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Mousnier, M., G. Bascoul, T. Lombardi, et al. "Thermal Transient Phenomenon Analysis for Design Debug." In ISTFA 2018. ASM International, 2018. http://dx.doi.org/10.31399/asm.cp.istfa2018p0368.

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Abstract Thermal issues management is a daily design challenge for teams working with analog mixed-signal technologies such as “SmartMOS”, with the integration of analog circuitry, high power density devices and logic control. A case study based on an NXP new product introduction will illustrate the use of Thermography as a complementary technique to standard Design debug activities, leading to the demonstration of a thermal crosstalk phenomenon in the analyzed analog mixed signal device. Based on InfraRed Thermography principle and specific Trigger Delay and Thermal Mapping modes, a transient thermal event was fully characterized, in addition to more common techniques such as Design and Layout study, electrical characterization, simulation, Microprobing, and Thermal Laser Stimulation. The added value of the thermography, as well as the limitations of the technique, will be discussed in that paper.
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Estores, Rommel, Pascal Vercruysse, Karl Villareal, Eric Barbian, Ralph Sanchez, and Rich Ackerman. "Failure Analysis Enhancement by Incorporating a Compact Scan Diagnosis System." In ISTFA 2014. ASM International, 2014. http://dx.doi.org/10.31399/asm.cp.istfa2014p0436.

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Abstract The failure analysis community working on highly integrated mixed signal circuitry is entering an era where simultaneously System-On-Chip technologies, denser metallization schemes, on-chip dissipation techniques and intelligent packages are being introduced. These innovations bring a great deal of defect accessibility challenges to the failure analyst. To contend in this era while aiming for higher efficiency and effectiveness, the failure analysis environment must undergo a disruptive evolution. The success or failure of an analysis will be determined by the careful selection of tools, data and techniques in the applied analysis flow. A comprehensive approach is required where hardware, software, data analysis, traditional FA techniques and expertise are complementary combined [1]. This document demonstrates this through the incorporation of advanced scan diagnosis methods in the overall analysis flow for digital functionality failures and supporting the enhanced failure analysis methodology. For the testing and diagnosis of the presented cases, compact but powerful scan test FA Lab hardware with its diagnosis software was used [2]. It can therefore easily be combined with the traditional FA techniques to provide stimulus for dynamic fault localizations [3]. The system combines scan chain information, failure data and layout information into one viewing environment which provides real analysis power for the failure analyst. Comprehensive data analysis is performed to identify failing cells/nets, provide a better overview of the failure and the interactions to isolate the fault further to a smaller area, or to analyze subtle behavior patterns to find and rationalize possible faults that are otherwise not detected. Three sample cases will be discussed in this document to demonstrate specific strengths and advantages of this enhanced FA methodology.
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Alon, Elad. "Mixed-Signal Electrical Interfaces." In 2019 IEEE Custom Integrated Circuits Conference (CICC). IEEE, 2019. http://dx.doi.org/10.1109/cicc.2019.8780299.

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"T1B: Digital and Mixed-Signal Circuits." In 2018 31st IEEE International System-on-Chip Conference (SOCC). IEEE, 2018. http://dx.doi.org/10.1109/socc.2018.8618574.

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"Session TPM3-6: Mixed-signal circuits." In 2009 6th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology. IEEE, 2009. http://dx.doi.org/10.1109/ecticon.2009.5136936.

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Jagan, N., S. Prasad, and P. H. Rao. "Electromagnetic noise mitigation in mixed signal systems using complementary split ring resonator." In 2013 IEEE Applied Electromagnetics Conference (AEMC). IEEE, 2013. http://dx.doi.org/10.1109/aemc.2013.7045058.

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Tapson, Jonathan. "Mixed signal phase sensitive detection." In 2010 IEEE International Symposium on Circuits and Systems - ISCAS 2010. IEEE, 2010. http://dx.doi.org/10.1109/iscas.2010.5537264.

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Kobayashi, Haruo, Nene Kushita, Minh Tri Tran, et al. "Analog / Mixed-Signal / RF Circuits for Complex Signal Processing." In 2019 IEEE 13th International Conference on ASIC (ASICON). IEEE, 2019. http://dx.doi.org/10.1109/asicon47005.2019.8983548.

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Sadiku, Matthew N. O., Elie M. Issa, John O. Attia, and Omonowo D. Momoh. "Substrate coupling in mixed signal integrated circuits." In SOUTHEASTCON 2011. IEEE, 2011. http://dx.doi.org/10.1109/secon.2011.5752974.

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Amer, H. H., and A. E. Salama. "Effective pseudorandom testing of mixed-signal circuits." In Proceedings of the 15th International Conference on Microelectronics. IEEE, 2003. http://dx.doi.org/10.1109/icm.2003.238010.

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Reports on the topic "Complementary Mixed signal circuits"

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Nicklaw, Christopher, Mark Maurer, Chuck Tabbert, and Randall Milanowski. Hierarchical CAD Tools for Radiation Hardened Mixed Signal Electronic Circuits. Defense Technical Information Center, 2005. http://dx.doi.org/10.21236/ada429971.

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