Relevant bibliographies by topics / Complementary Semiconductors Integrated circuits

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Complementary Semiconductors Integrated circuits'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'Complementary Semiconductors Integrated circuits.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "Complementary Semiconductors Integrated circuits"

1

Garner, C. Michael. "Lithography for enabling advances in integrated circuits and devices." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 370, no. 1973 (August 28, 2012): 4015–41. http://dx.doi.org/10.1098/rsta.2011.0052.

Full text
Abstract:
Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.
APA, Harvard, Vancouver, ISO, and other styles
2

Takeda, Yasunori, Tomohito Sekine, Rei Shiwaku, Tomohide Murase, Hiroyuki Matsui, Daisuke Kumaki, and Shizuo Tokito. "Printed Organic Complementary Inverter with Single SAM Process Using a p-type D-A Polymer Semiconductor." Applied Sciences 8, no. 8 (August 9, 2018): 1331. http://dx.doi.org/10.3390/app8081331.

Full text
Abstract:
The demonstration of the complementary integrated circuit using printing processes is indispensable for realizing electronic devices using organic thin film transistors. Although complementary integrated circuits have advantages such as low power consumption and a wide output voltage range, complementary integrated circuits fabricated by the printing method have problems regarding driving voltage and performance. Studies on fabrication processes of electronic circuits for printing technology, including optimization and simplification, are also important research topics. In this study, the fabrication process of the printed complementary integrated circuit was simplified by applying a p-type donor-acceptor (D-A) polymer semiconductor, which is not strongly affected by the electrode work function. An inverter circuit and the ring oscillator circuit were demonstrated using this process. The fabricated ring oscillator array showed excellent performance, with low voltage operation and low performance variation.
APA, Harvard, Vancouver, ISO, and other styles
3

Baeg, Kang-Jun, Dongyoon Khim, Dong-Yu Kim, Soon-Won Jung, Jae Bon Koo, In-Kyu You, Henry Yan, Antonio Facchetti, and Yong-Young Noh. "High speeds complementary integrated circuits fabricated with all-printed polymeric semiconductors." Journal of Polymer Science Part B: Polymer Physics 49, no. 1 (September 24, 2010): 62–67. http://dx.doi.org/10.1002/polb.22148.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Nam, SungWoo, Xiaocheng Jiang, Qihua Xiong, Donhee Ham, and Charles M. Lieber. "Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits." Proceedings of the National Academy of Sciences 106, no. 50 (November 25, 2009): 21035–38. http://dx.doi.org/10.1073/pnas.0911713106.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Francis, A. Matthew, Jim Holmes, Nick Chiolino, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. "High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, HiTEC (January 1, 2016): 000242–48. http://dx.doi.org/10.4071/2016-hitec-242.

Full text
Abstract:
Abstract In the last decade, significant effort has been expended towards the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field effect transistors and metal-oxide-semiconductor field effect transistors have been pursued and demonstrated. More recently1,2, advances in low-power complementary MOS devices have enabled the development of highly-integrated digital, analog and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) for extended periods (up to 100 hours) of several building block circuits will be presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at these extreme temperatures for any period of time. Based on these results, Venus nominal temperature (470°C) SPICE m°dels and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller in SiC-CMOS, with an eye for Venus as well as terrestrial applications.
APA, Harvard, Vancouver, ISO, and other styles
6

Holmes, Jim, A. Matthew Francis, Ian Getreu, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. "Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application." Journal of Microelectronics and Electronic Packaging 13, no. 4 (October 1, 2016): 143–54. http://dx.doi.org/10.4071/imaps.527.

Full text
Abstract:
In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circuits for extended periods (up to 100 h) are presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at extreme temperatures for any period. Based on these results, Venus nominal temperature (470°C) transistor models and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller. A 16-bit microcontroller, based on the OpenMSP 16-bit core, is demonstrated through physical design and simulation in SiC-CMOS, with an eye for Venus as well as terrestrial applications.
APA, Harvard, Vancouver, ISO, and other styles
7

Kazior, Thomas E. "Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 372, no. 2012 (March 28, 2014): 20130105. http://dx.doi.org/10.1098/rsta.2013.0105.

Full text
Abstract:
Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications.
APA, Harvard, Vancouver, ISO, and other styles
8

Zhao, Chun, Ce Zhou Zhao, and Bin Da. "A Novel Technique for Arithmetic Elements Standard Cell Library Establishment Based on Tanner Tools." Advanced Materials Research 569 (September 2012): 273–76. http://dx.doi.org/10.4028/www.scientific.net/amr.569.273.

Full text
Abstract:
The economic and efficient accomplishment of an application-specific integrated circuit design depends heavily upon the choice of the library. Therefore, it is important to build library that full fills the design requirement. Tanner Tools is a set of software for designing integrated circuits. The great advantage of Tanner is that it can provide a complete circuit design tools in desktop computers. The paper aims to create a standard cell library establishment on the 0.5 micro complementary metal–oxide–semiconductor mixed signal process based on the Tanner Tools.
APA, Harvard, Vancouver, ISO, and other styles
9

Chen, Ethan, and Vanessa Chen. "Statistical RF/Analog Integrated Circuit Design Using Combinatorial Randomness for Hardware Security Applications." Mathematics 8, no. 5 (May 20, 2020): 829. http://dx.doi.org/10.3390/math8050829.

Full text
Abstract:
While integrated circuit technologies keep scaling aggressively, analog, mixed-signal, and radio-frequency (RF) circuits encounter challenges by creating robust designs in advanced complementary metal–oxide–semiconductor (CMOS) processes with the diminishing voltage headroom. The increasing random mismatch of smaller feature sizes in leading-edge technology nodes severely limit the benefits of scaling for (RF)/analog circuits. This paper describes the details of the combinatorial randomness by statistically selecting device elements that relies on the significant growth in subsets number of combinations. The randomness can be utilized to provide post-manufacturing reconfiguration of the selectable circuit elements to achieve required specifications for ultra-low-power systems. The calibration methodology is demonstrated with an ultra-low-voltage chaos-based true random number generator (TRNG) for energy-constrained Internet of things (IoT) devices in the secure communications.
APA, Harvard, Vancouver, ISO, and other styles
10

Yu, Lili, Ahmad Zubair, Elton J. G. Santos, Xu Zhang, Yuxuan Lin, Yuhao Zhang, and Tomás Palacios. "High-Performance WSe2 Complementary Metal Oxide Semiconductor Technology and Integrated Circuits." Nano Letters 15, no. 8 (July 28, 2015): 4928–34. http://dx.doi.org/10.1021/acs.nanolett.5b00668.

Full text
APA, Harvard, Vancouver, ISO, and other styles
More sources

Dissertations / Theses on the topic "Complementary Semiconductors Integrated circuits"

1

Hildreth, Scott A. "Statistical SPICE parameter extraction for an N-Well CMOS process /." Online version of thesis, 1995. http://hdl.handle.net/1850/12177.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Li, Xiaoyong. "Low noise design techniques for radio frequency integrated circuits /." Thesis, Connect to this title online; UW restricted, 2004. http://hdl.handle.net/1773/6013.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Kwon, Ohsang. "On high performance multiplier design using dynamic CMOS circuits /." Full text (PDF) from UMI/Dissertation Abstracts International, 2000. http://wwwlib.umi.com/cr/utexas/fullcit?p3004310.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Gajera, Dipesh. "Process costing of microchip." Morgantown, W. Va. : [West Virginia University Libraries], 2006. https://eidr.wvu.edu/etd/documentdata.eTD?documentid=4726.

Full text
Abstract:
Thesis (M.S.)--West Virginia University, 2006.
Title from document title page. Document formatted into pages; contains vii, 92 p. : ill. (some col.). Includes abstract. Includes bibliographical references (p. 85-91).
APA, Harvard, Vancouver, ISO, and other styles
5

Lu, Yuanlin. "Power and performance optimization of static CMOS circuits with process variation." Auburn, Ala., 2007. http://repo.lib.auburn.edu/07M%20Dissertations/LU_YUANLIN_28.pdf.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Kanitkar, Hrishikesh. "Subthreshold circuits : design, implementation and application /." Online version of thesis, 2009. http://hdl.handle.net/1850/8926.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Chen, Yonggang Suhling J. C. Jaeger Richard C. "CMOS stress sensor circuits." Auburn, Ala., 2006. http://repo.lib.auburn.edu/2006%20Fall/Dissertations/CHEN_YONGGANG_42.pdf.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Bollinger, S. Wayne. "Hierarchical test generation for CMOS circuits." Diss., This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-07282008-134708/.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Ting, Goodwin. "An integrated BiCMOS driver chip for medium power applications /." Online version of thesis, 1991. http://hdl.handle.net/1850/11291.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Yee, Gin Sun. "Dynamic logic design and synthesis using clock-delayed domino /." Thesis, Connect to this title online; UW restricted, 1999. http://hdl.handle.net/1773/6039.

Full text
APA, Harvard, Vancouver, ISO, and other styles
More sources

Books on the topic "Complementary Semiconductors Integrated circuits"

1

Yusuf, Leblebici, ed. CMOS digital integrated circuits: Analysis and design. 2nd ed. Boston, MA: McGraw-Hill, 1998.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
2

Kang, Sung-Mo. CMOS digital integrated circuits: Analysis and design. 2nd ed. Boston, Mass: McGraw-Hill, 1999.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
3

Yusuf, Leblebici, ed. CMOS digital integrated circuits: Analysis and design. 3rd ed. Boston: McGraw-Hill, 2003.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
4

Kang, Sung-Mo. CMOS digital integrated circuits: Analysis and design. New York: McGraw-Hill, 1996.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
5

Sheng-Fu, Hsu, ed. Transient-induced latchup in CMOS integrated circuits. Singapore: Wiley, 2009.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
6

Design of analog CMOS integrated circuits. Boston, MA: McGraw-Hill, 2001.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
7

Shoji, Masakazu. Theory of CMOS digital circuits and circuit failures. Princeton, N.J: Princeton University Press, 1992.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
8

Shoji, Masakazu. Theory of CMOS digital circuits and circuit failures. Princeton, N.J: Princeton University Press, 1992.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
9

Anh, Do Manh, and Boon Chirn Chye, eds. Design of CMOS RF integrated circuits and systems. Singapore: World Scientific, 2010.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
10

A, Bellaouar, and Elmasry Mohamed I. 1943-, eds. Digital BiCMOS integrated circuit design. Boston: Kluwer Academic, 1993.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
More sources

Book chapters on the topic "Complementary Semiconductors Integrated circuits"

1

Palusinski, O. A., F. Szidarovszky, C. Marcjan, and M. Abdennadher. "Spectral Algorithm for Simulation of Integrated Circuits." In Semiconductors, 131–40. New York, NY: Springer New York, 1994. http://dx.doi.org/10.1007/978-1-4613-8407-6_9.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Kymissis, Ioannis. "The physics of organic semiconductors." In Integrated Circuits and Systems, 1–12. Boston, MA: Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-92134-1_2.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Le Coz, Yannick L., and Ralph B. Iverson. "Theory of a Stochastic Algorithm for Capacitance Extraction in Integrated Circuits." In Semiconductors, 107–14. New York, NY: Springer New York, 1994. http://dx.doi.org/10.1007/978-1-4613-8407-6_7.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Beinvogl, W., and A. Gutmann. "Submicron Patterning Techniques for Integrated Circuits." In Low-Dimensional Structures in Semiconductors, 89–108. Boston, MA: Springer US, 1991. http://dx.doi.org/10.1007/978-1-4899-0623-6_6.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Facchetti, Antonio. "Conjugated Semiconductors for Organic n-Channel Transistors and Complementary Circuits." In Organic Electronics II, 137–95. Weinheim, Germany: Wiley-VCH Verlag GmbH & Co. KGaA, 2012. http://dx.doi.org/10.1002/9783527640218.ch5.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Nojiri, Kazuo. "The Contribution of Dry Etching Technology to Progress in Semiconductor Integrated Circuits." In Dry Etching Technology for Semiconductors, 1–9. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-10295-5_1.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Anile, A. M., G. Mascali, and V. Romano. "Hydrodynamical Model for GaAs Semiconductors Based on the Maximum Entropy Principle with Application to Electronic Devices." In Modeling, Simulation, and Optimization of Integrated Circuits, 3–15. Basel: Birkhäuser Basel, 2003. http://dx.doi.org/10.1007/978-3-0348-8065-7_1.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Wasley, Nicholas Andrew. "Introduction." In Nano-photonics in III-V Semiconductors for Integrated Quantum Optical Circuits, 1–16. Cham: Springer International Publishing, 2013. http://dx.doi.org/10.1007/978-3-319-01514-9_1.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Wasley, Nicholas Andrew. "Experimental Methods." In Nano-photonics in III-V Semiconductors for Integrated Quantum Optical Circuits, 17–30. Cham: Springer International Publishing, 2013. http://dx.doi.org/10.1007/978-3-319-01514-9_2.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Wasley, Nicholas Andrew. "Disorder Limited Photon Propagation and Anderson Localisation in Photonic Crystal Waveguides." In Nano-photonics in III-V Semiconductors for Integrated Quantum Optical Circuits, 31–49. Cham: Springer International Publishing, 2013. http://dx.doi.org/10.1007/978-3-319-01514-9_3.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "Complementary Semiconductors Integrated circuits"

1

Yurt, A., E. Ramsay, F. H. Köklü, M. S. Ünlü, and B. B. Goldberg. "Chromatic Aberration Correction of Silicon Aplanatic Solid Immersion Lens for Photon Emission Microscopy of Integrated Circuits." In ISTFA 2011. ASM International, 2011. http://dx.doi.org/10.31399/asm.cp.istfa2011p0406.

Full text
Abstract:
Abstract We investigate a complementary objective lens design for correcting chromatic aberration in the use of a silicon aplanatic solid immersion lens for back-side photon emission microscopy of metal-oxide-semiconductor circuits. Our simulations demonstrate that the chromatic aberration due to material dispersion of aplanatic silicon solid immersion lenses can be reduced by more than an order of magnitude in the spectral window 1.5µm-2.1µm, providing new diffraction limited performance. On-axis and off-axis imaging performance of the proposed optical design is evaluated.
APA, Harvard, Vancouver, ISO, and other styles
2

Xu, Kaikai, and Guann-pyng Li. "The Path Forward: Silicon Electro-Optical Interface for Modern Complementary Metal-Oxide-Semiconductor Integrated Circuits (CMOS ICs)." In CIOMP-OSA Summer Session on Optical Engineering, Design and Manufacturing. Washington, D.C.: OSA, 2013. http://dx.doi.org/10.1364/sumsession.2013.th8.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Yee, Wai Mun, Mario Paniccia, Travis Eiles, and Valluri Rao. "Laser Voltage Probe (LVP): A Novel Optical Probing Technology for Flip-Chip Packaged Microprocessors." In ISTFA 2000. ASM International, 2000. http://dx.doi.org/10.31399/asm.cp.istfa2000p0003.

Full text
Abstract:
Abstract A novel optical probing technique to measure voltage waveforms from flip-chip packaged complementary metal-oxide-semiconductor (CMOS) integrated circuits (IC) is described. This infrared (IR) laser based technique allows signal waveform acquisition and high frequency timing measurement directly from active PN junctions through the silicon backside substrate on IC’s mounted in flip-chip, stand-alone, or multi-chip module packages as well as wire-bond packages on which the chip backside is accessible. The technique significantly improves silicon debug & failure analysis (FA) through-put time (TPT) as compared to backside electron-beam (E-beam) probing because of the elimination of backside trenching and probe hole generation operations.
APA, Harvard, Vancouver, ISO, and other styles
4

Niu, Baohua, Martin von Haartman, Patrick Pardy, and Mitch Sacks. "Differential Polarization Imaging and Probing [DPIP]: Seeing and Probing the “Invisible”." In ISTFA 2012. ASM International, 2012. http://dx.doi.org/10.31399/asm.cp.istfa2012p0190.

Full text
Abstract:
Abstract A novel method for obtaining diffraction limited high resolution images, and increased signal to noise ratio (SnR), for imaging and probing silicon based complementary metal oxide semiconductor field effect transistor (CMOS, and MOSFET) integrated circuits (IC), is presented. The improved imaging is based on the sub wavelength features’ asymmetric layout, which is dictated by the lithography design rules constrain in CMOS IC and their interactions with polarized light. This asymmetry in layout and the inherent stress engineering on the CMOS IC, produce both dichroism and birefringence in silicon (Si). An elegant design enabled us to obtain two images with orthogonal polarization detection to take advantages of the dichroism and birefringence in Si based CMOS IC. Differential Polarization Image (DPI) is obtained by subtracting the two orthogonal polarization resolved images. On infrared emission microscopes (IREM), DPI in optical imaging mode and DPI plus probing [DPIP] in emission mode, showed 2X or more in terms of optical resolution (imaging mode) and 2X or more SnR (emission-probing mode) improvements. Striking images in probing mode, revealing previously “invisible” emission, were demonstrated.
APA, Harvard, Vancouver, ISO, and other styles
5

Koren, Uziel. "Photonic integrated circuits." In Semiconductors '92, edited by John E. Bowers and Umesh K. Mishra. SPIE, 1992. http://dx.doi.org/10.1117/12.137705.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Yoo, Byungwook, Debarshi Basu, Taeho Jung, Daniel Fine, Brooks Jones, Antonio Facchetti, Michael Wasielewski, Tobin Marks, Klaus Dimmler, and Ananth Dodabalapur. "Organic complementary circuits using solution deposited active semiconductors." In 2006 64th Device Research Conference. IEEE, 2006. http://dx.doi.org/10.1109/drc.2006.305061.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Jensen, Joe E., William E. Stanchina, Robert A. Metzger, M. E. Hafizi, Ting-Ping Liu, and David B. Rensch. "High-speed InP-based HBT integrated circuits." In Semiconductors '92, edited by John E. Bowers and Umesh K. Mishra. SPIE, 1992. http://dx.doi.org/10.1117/12.142553.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Rashid, Shahriar, Brian Dupaix, Paul Watson, Wagdy Gaber, Vipul J. Patel, Aji Mattamana, Steven Dooley, Matthew LaRue, and Waleed Khalil. "A Wide-Band Complementary Digital Driver for Pulse Modulated Single-Ended and Differential S/C Bands Class-E PAs in 130 nm GaAs Technology." In 2016 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS). IEEE, 2016. http://dx.doi.org/10.1109/csics.2016.7751025.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Chang, H. D., J. H. Zhou, G. M. Liu, Z. H. Zeng, W. Zhao, B. Sun, S. K. Wang, X. L. Zhou, J. Q. Pan, and H. G. Liu. "InGaAs Complementary metal-oxide-semiconductor fabricated on GaAs Substrate using Al2O3 as gate oxide." In 2014 IEEE 12th International Conference on Solid -State and Integrated Circuit Technology (ICSICT). IEEE, 2014. http://dx.doi.org/10.1109/icsict.2014.7021653.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Quinsey, Ralph. "The Future of Compound Semiconductors." In 2007 IEEE Compound Semiconductor Integrated Circuits Symposium. IEEE, 2007. http://dx.doi.org/10.1109/csics07.2007.59.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Reports on the topic "Complementary Semiconductors Integrated circuits"

1

Carpenter, D. A., D. L. Golijanin, and D. Wherry. Development of XRMF techniques for measurement of multi-layer film thicknesses on semiconductors for VLSI and ULSI integrated circuits. Final CRADA report for CRADA number Y-1292-0130. Office of Scientific and Technical Information (OSTI), February 1997. http://dx.doi.org/10.2172/527526.

Full text
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the extended bibliographies on the topic 'Complementary Semiconductors Integrated circuits' for particular source types:
Journal articles Dissertations / Theses Books
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography