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Dissertations / Theses on the topic 'Complementary Semiconductors Integrated circuits'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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1

Hildreth, Scott A. "Statistical SPICE parameter extraction for an N-Well CMOS process /." Online version of thesis, 1995. http://hdl.handle.net/1850/12177.

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2

Li, Xiaoyong. "Low noise design techniques for radio frequency integrated circuits /." Thesis, Connect to this title online; UW restricted, 2004. http://hdl.handle.net/1773/6013.

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3

Kwon, Ohsang. "On high performance multiplier design using dynamic CMOS circuits /." Full text (PDF) from UMI/Dissertation Abstracts International, 2000. http://wwwlib.umi.com/cr/utexas/fullcit?p3004310.

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4

Gajera, Dipesh. "Process costing of microchip." Morgantown, W. Va. : [West Virginia University Libraries], 2006. https://eidr.wvu.edu/etd/documentdata.eTD?documentid=4726.

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Thesis (M.S.)--West Virginia University, 2006.
Title from document title page. Document formatted into pages; contains vii, 92 p. : ill. (some col.). Includes abstract. Includes bibliographical references (p. 85-91).

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5

Lu, Yuanlin. "Power and performance optimization of static CMOS circuits with process variation." Auburn, Ala., 2007. http://repo.lib.auburn.edu/07M%20Dissertations/LU_YUANLIN_28.pdf.

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6

Kanitkar, Hrishikesh. "Subthreshold circuits : design, implementation and application /." Online version of thesis, 2009. http://hdl.handle.net/1850/8926.

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7

Chen, Yonggang Suhling J. C. Jaeger Richard C. "CMOS stress sensor circuits." Auburn, Ala., 2006. http://repo.lib.auburn.edu/2006%20Fall/Dissertations/CHEN_YONGGANG_42.pdf.

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8

Bollinger, S. Wayne. "Hierarchical test generation for CMOS circuits." Diss., This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-07282008-134708/.

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9

Ting, Goodwin. "An integrated BiCMOS driver chip for medium power applications /." Online version of thesis, 1991. http://hdl.handle.net/1850/11291.

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10

Yee, Gin Sun. "Dynamic logic design and synthesis using clock-delayed domino /." Thesis, Connect to this title online; UW restricted, 1999. http://hdl.handle.net/1773/6039.

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11

Deshpande, Sandeep. "A cost quality model for CMOS IC design." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-12042009-020251/.

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12

Tabler, John A. "An integrated adaptive bias solution for zero passive component count high-performance mixed-signal ICs." Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/13339.

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13

Lee, Myunghee. "A quasi-monolithic optical receiver using a standard digital CMOS technology." Diss., Georgia Institute of Technology, 1996. http://hdl.handle.net/1853/14720.

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14

Hirschman, Karl D. "Process development of an analog/digital mixed-mode BiCMOS system at RIT /." Online version of thesis, 1992. http://hdl.handle.net/1850/11238.

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15

Guidash, R. Michael. "Development of a modular 2-micron BiCMOS process from an existing 2-micron n-well CMOS process /." Online version of thesis, 1991. http://hdl.handle.net/1850/11234.

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16

Wang, Fan Agrawal Vishwani D. "Soft error rate determination for nanometer CMOS VLSI circuits." Auburn, Ala, 2008. http://hdl.handle.net/10415/1517.

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17

Murji, Rizwan Deen M. Jamal. "Low-power CMOS radio frequency integrated circuits for frequency synthesis /." *McMaster only, 2005.

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18

Ramirez, Ortiz Rolando Carleton University Dissertation Engineering Electronics. "Circuit design rules for mixed static and dynamics CMOS logic circuits." Ottawa, 1999.

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19

Öziş, Hatice Dicle. "Image-reject receiver architectures for radio frequency integrated circuits /." Thesis, Connect to this title online; UW restricted, 2006. http://hdl.handle.net/1773/6052.

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20

Tsui, Hau Yiu. "A 5 GHz integrated low-power CMOS RF front-end IC design /." View abstract or full-text, 2004. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202004%20TSUI.

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21

Zhang, Xibo. "RF integrated circuit design options : from technology to layout /." View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20ZHANG.

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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003.
Includes bibliographical references (leaves 59-61). Also available in electronic version. Access restricted to campus users.

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22

Choi, Kyu-Won. "Hierarchical power optimization for ultra low-power digital systems." Diss., Available online, Georgia Institute of Technology, 2004:, 2003. http://etd.gatech.edu/theses/available/etd-04082004-180111/unrestricted/choi%5Fkyu-won%5F200312%5Fphd.pdf.

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23

Xuan, Xiangdong. "Analysis and design of reliable mixed-signal CMOS circuits." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-08032004-185515/unrestricted/xuan%5Fxiangdong%5F200412%5Fphd.pdf.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.
Singh, Adit, Committee Member ; Chatterjee, Abhijit, Committee Chairl May, Gary, Committee Member ; Keezer, David, Committee Member ; Swaminathan, Madhavan, Committee Member. Vita. Includes bibliographical references.

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24

Layton, Kent D. "Low-voltage analog CMOS architectures and design methods /." Diss., CLICK HERE for online access, 2007. http://contentdm.lib.byu.edu/ETD/image/etd2141.pdf.

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25

Amarchinta, Sumanth. "High performance subthreshold standard cell design and cell placement optimization /." Online version of thesis, 2009. http://hdl.handle.net/1850/10740.

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26

Woo, Sang Hyun. "Low noise RF CMOS receiver integrated circuits." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/50127.

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The objective of this research is to design and implement low-noise wideband RFIC components with CMOS technology for the direct-conversion architecture. This research proposes noise reduction techniques to improve the thermal noise and flicker noise contribution of a low noise amplifier (LNA) and a mixer. Of these techniques, the LNA is found to reduce noise, boost gain, and consume a relatively low amount of power without sacrificing the wideband and linearity advantages of a conventional common gate (CG) topology. The research concludes by investigating the proposed mixer topology, which senses and compensates local oscillator (LO) phase mismatches, the dominant cause of flicker noise.

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27

Li, Zhenbiao. "Radio frequency circuits for tunable multi-band CMOS receivers for wireless LAN applications." [Gainesville, Fla.] : University of Florida, 2004. http://purl.fcla.edu/fcla/etd/UFE0006637.

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28

Ng, Chik-wai, and 吳植偉. "Design techniques of advanced CMOS building blocks for high-performance power management integrated circuits." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2011. http://hub.hku.hk/bib/B45896926.

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29

Wang, Haihong. "Advanced transport models development for deep submicron low power CMOS device design /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

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30

Long, Ethan Schuyler. "The Role of Temperature in Testing Deep Submicron CMOS ASICs." PDXScholar, 2003. https://pdxscholar.library.pdx.edu/open_access_etds/34.

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Among the many efforts to improve the IC test process are tests that attempt to differentiate between healthy and defective or low reliability ICs by manipulating the operating conditions of the IC being tested. This thesis attempts to improve the common understanding of multiple and targeted temperature testing by evaluating work published on the subject to date and by presenting previously unpublished empirical observations. The empirical observations are made from SCAN and LBIST based MinVDD measurements, Static IDD measurements, as well as parametric measurements of transistor characteristics. The test vehicles used are 0.25μm and 0.18μm CMOS ASICs fabricated by LSI Logic. An IC’s performance is bound by a three dimensional space defined by VDD, frequency, and temperature. A model is presented to explain the boundaries of the performance region in terms of the ability of the IC’s constituent transistors to provide power and the Zero-Temperature-Coefficient (ZTC). Also, it is determined that multiple temperature testing can add new tests to current test suites to improve the resolution between healthy and defective ICs.

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31

Lee, Wai Kit. "Modeling the distributed RC effects of BiCMOS technology at high frequency operations /." View abstract or full-text, 2006. http://library.ust.hk/cgi/db/thesis.pl?ECED%202006%20LEE.

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32

Vadlamudi, Tripurasuparna Mohanty Saraju. "A nano-CMOS based universal voltage level converter for multi-V[subscript]DD SoCs." [Denton, Tex.] : University of North Texas, 2007. http://digital.library.unt.edu/permalink/meta-dc-3602.

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33

Sudirgo, Stephen. "The integration of Si-based resonant interband tunnel diodes with CMOS /." Online version of thesis, 2003. http://hdl.handle.net/1850/5192.

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34

Krom, Raymond T. "Gate-to-channel parasitic capacitance minimization and source-drain leakage evaluation in germanium PMOS /." Online version of thesis, 2008. http://hdl.handle.net/1850/9981.

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35

Wei, Xiaoyun Niu Guofu. "On-wafer S-parameter measurement using four-port technique and intermodulation linearity of RF CMOS." Auburn, Ala, 2008. http://hdl.handle.net/10415/1448.

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36

Liu, Kou-chen. "Si1-xGex/Si vertical MOSFETs and sidewall strained Si devices : design and fabrication /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

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37

Digvadekar, Ashish A. "A sub 1 V bandgap reference circuit /." Online version of thesis, 2005. https://ritdml.rit.edu/dspace/handle/1850/2595.

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38

Fang, Sher Jiun. "Complementary metal-oxide-semiconductor frequency conversion techniques for wideband code division multiple access /." Thesis, Connect to this title online; UW restricted, 2003. http://hdl.handle.net/1773/6114.

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39

al-Sarʻāwī, Said Fares. "Design techniques for low power mixed analog-digital circuits with application to smart wireless systems /." Title page, contents and abstract only, 2003. http://web4.library.adelaide.edu.au/theses/09PH/09pha461.pdf.

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40

Deodhar, Vinita Vasant. "Throughput-Centric Wave-Pipelined Interconnect Circuits for Gigascale Integration." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7503.

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The central thesis of this research is that VLSI interconnect design strategies should shift from using global wires that can support only a single binary transition during the latency of the line to global wires that can sustain multiple bits traveling simultaneously along the length of the line. It is shown in this thesis that such throughput-centric multibit transmission can be achieved by wave-pipelining the interconnects using repeaters. A holistic analysis of wave-pipelined interconnect circuits, along with the full-custom optimization of these circuits, is performed in this research. With the help of models and methodologies developed in this thesis, the design rules for repeater insertion are crafted to simultaneously optimize performance, power, and area of VLSI global interconnect networks through a simultaneous application of voltage scaling and wire sizing. A qualitative analysis of latency, throughput, signal integrity, power dissipation, and area is performed that compares the results of design optimizations in this work to those of conventional global interconnect circuits. The objective of this thesis is to study the circuit- and system-level opportunities of voltage scaling, wire sizing, and repeater insertion in wave-pipelined global interconnect networks that are implemented in deep submicron technologies.

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41

Carr, Richard D. "Analog preprocessing in a SNS 2 [mu] low-noise CMOS folding ADC." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1994. http://handle.dtic.mil/100.2/ADA293356.

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Thesis (M.S. in Electrical Engineering) Naval Postgraduate School, December 1994.
"December 1994." Thesis advisor(s): Phillip E. Pace, Douglas J. Fouts. Bibliography: p. 103. Also available online.

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42

Hu, Li. "Low power CMOS image sensor using adaptive address event representation /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20HU.

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43

Chan, Tat Fu. "Low power low phase noise CMOS LC quadrature voltage-controlled oscillators /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20CHANT.

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44

Song, Seung-chul. "Advanced oxynitride and silicon nitride gate dielectrics for ULSI CMOS technology /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

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45

Buchanan, Brent E. "A mixed-signal CMOS VLSI image convolution circuit using error spectrum shaping." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15420.

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46

Long, John R. (John Robert) Carleton University Dissertation Engineering Electrical. "High frequency integrated circuit design in BICMOS for monolithic timing recovery." Ottawa, 1992.

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47

Madan, Anuj. "Design and reliability of high dynamic range RF building blocks in SOI CMOS and SiGe BiCMOS technologies." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/45853.

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The objective of the proposed research is to understand the design and reliability of RF front-end building blocks using SOI CMOS and SiGe BiCMOS technologies for high dynamic-range applications. This research leads to a comprehensive understanding of dynamic range in SOI CMOS devices and contributes to knowledge leading to improvement in overall dynamic range and reliability of RF building blocks. While the performance of CMOS transistors has been improving naturally with scaling, this work aims to explore the possibilities of improvement in RF performance and reliability using standard layouts (that don't need process modifications). The total-ionizing dose tolerance of SOI CMOS devices has been understood with extensive measurements. Furthermore, the role of body contacts in SOI technology is understood for dynamic range performance improvement. In this work, CMOS low-noise amplifier design for high linearity WLAN applications and its integration with RF switch on the same chip is presented. The LNA and switches designed provide state-of-the-art performance in silicon based technologies. Further, the work aims to explore applications of SiGe HBT in the context of highly linear and reliable RF building blocks. The RF reliability of SiGe HBT based RF switches is investigated and compared with CMOS counterparts. The inverse-mode operation of SiGe HBT based switches is understood to give considerably higher linearity.

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48

Kong, Wan-Chul. "Low-power low-phase noise LC oscillators in silicon-on-sapphire CMOS technology /." Title page, table of contents and abstract only, 2004. http://web4.library.adelaide.edu.au/theses/09ENS/09ensk822.pdf.

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49

Cui, Yan Niu Guofu. "High frequency noise modeling and microscopic noise simulation for SiGe HBT and RF CMOS." Auburn, Ala., 2006. http://repo.lib.auburn.edu/Send%2012-15-07/CUI_YAN_8.pdf.

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50

La, Pietra Andrew R. "Establishing a bipolar fabrication service for analog circuit realization at the Rochester Institute of Technology /." Online version of thesis, 1991. http://hdl.handle.net/1850/11272.

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