Journal articles: 'Complementary Semiconductors Integrated circuits'

1

Garner, C. Michael. "Lithography for enabling advances in integrated circuits and devices." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 370, no. 1973 (August 28, 2012): 4015–41. http://dx.doi.org/10.1098/rsta.2011.0052.

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Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.

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Takeda, Yasunori, Tomohito Sekine, Rei Shiwaku, Tomohide Murase, Hiroyuki Matsui, Daisuke Kumaki, and Shizuo Tokito. "Printed Organic Complementary Inverter with Single SAM Process Using a p-type D-A Polymer Semiconductor." Applied Sciences 8, no. 8 (August 9, 2018): 1331. http://dx.doi.org/10.3390/app8081331.

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The demonstration of the complementary integrated circuit using printing processes is indispensable for realizing electronic devices using organic thin film transistors. Although complementary integrated circuits have advantages such as low power consumption and a wide output voltage range, complementary integrated circuits fabricated by the printing method have problems regarding driving voltage and performance. Studies on fabrication processes of electronic circuits for printing technology, including optimization and simplification, are also important research topics. In this study, the fabrication process of the printed complementary integrated circuit was simplified by applying a p-type donor-acceptor (D-A) polymer semiconductor, which is not strongly affected by the electrode work function. An inverter circuit and the ring oscillator circuit were demonstrated using this process. The fabricated ring oscillator array showed excellent performance, with low voltage operation and low performance variation.

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Baeg, Kang-Jun, Dongyoon Khim, Dong-Yu Kim, Soon-Won Jung, Jae Bon Koo, In-Kyu You, Henry Yan, Antonio Facchetti, and Yong-Young Noh. "High speeds complementary integrated circuits fabricated with all-printed polymeric semiconductors." Journal of Polymer Science Part B: Polymer Physics 49, no. 1 (September 24, 2010): 62–67. http://dx.doi.org/10.1002/polb.22148.

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Nam, SungWoo, Xiaocheng Jiang, Qihua Xiong, Donhee Ham, and Charles M. Lieber. "Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits." Proceedings of the National Academy of Sciences 106, no. 50 (November 25, 2009): 21035–38. http://dx.doi.org/10.1073/pnas.0911713106.

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5

Francis, A. Matthew, Jim Holmes, Nick Chiolino, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. "High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, HiTEC (January 1, 2016): 000242–48. http://dx.doi.org/10.4071/2016-hitec-242.

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Abstract In the last decade, significant effort has been expended towards the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field effect transistors and metal-oxide-semiconductor field effect transistors have been pursued and demonstrated. More recently1,2, advances in low-power complementary MOS devices have enabled the development of highly-integrated digital, analog and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) for extended periods (up to 100 hours) of several building block circuits will be presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at these extreme temperatures for any period of time. Based on these results, Venus nominal temperature (470°C) SPICE m°dels and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller in SiC-CMOS, with an eye for Venus as well as terrestrial applications.

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Holmes, Jim, A. Matthew Francis, Ian Getreu, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. "Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application." Journal of Microelectronics and Electronic Packaging 13, no. 4 (October 1, 2016): 143–54. http://dx.doi.org/10.4071/imaps.527.

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In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circuits for extended periods (up to 100 h) are presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at extreme temperatures for any period. Based on these results, Venus nominal temperature (470°C) transistor models and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller. A 16-bit microcontroller, based on the OpenMSP 16-bit core, is demonstrated through physical design and simulation in SiC-CMOS, with an eye for Venus as well as terrestrial applications.

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Kazior, Thomas E. "Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 372, no. 2012 (March 28, 2014): 20130105. http://dx.doi.org/10.1098/rsta.2013.0105.

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Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications.

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Zhao, Chun, Ce Zhou Zhao, and Bin Da. "A Novel Technique for Arithmetic Elements Standard Cell Library Establishment Based on Tanner Tools." Advanced Materials Research 569 (September 2012): 273–76. http://dx.doi.org/10.4028/www.scientific.net/amr.569.273.

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The economic and efficient accomplishment of an application-specific integrated circuit design depends heavily upon the choice of the library. Therefore, it is important to build library that full fills the design requirement. Tanner Tools is a set of software for designing integrated circuits. The great advantage of Tanner is that it can provide a complete circuit design tools in desktop computers. The paper aims to create a standard cell library establishment on the 0.5 micro complementary metal–oxide–semiconductor mixed signal process based on the Tanner Tools.

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9

Chen, Ethan, and Vanessa Chen. "Statistical RF/Analog Integrated Circuit Design Using Combinatorial Randomness for Hardware Security Applications." Mathematics 8, no. 5 (May 20, 2020): 829. http://dx.doi.org/10.3390/math8050829.

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While integrated circuit technologies keep scaling aggressively, analog, mixed-signal, and radio-frequency (RF) circuits encounter challenges by creating robust designs in advanced complementary metal–oxide–semiconductor (CMOS) processes with the diminishing voltage headroom. The increasing random mismatch of smaller feature sizes in leading-edge technology nodes severely limit the benefits of scaling for (RF)/analog circuits. This paper describes the details of the combinatorial randomness by statistically selecting device elements that relies on the significant growth in subsets number of combinations. The randomness can be utilized to provide post-manufacturing reconfiguration of the selectable circuit elements to achieve required specifications for ultra-low-power systems. The calibration methodology is demonstrated with an ultra-low-voltage chaos-based true random number generator (TRNG) for energy-constrained Internet of things (IoT) devices in the secure communications.

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10

Yu, Lili, Ahmad Zubair, Elton J. G. Santos, Xu Zhang, Yuxuan Lin, Yuhao Zhang, and Tomás Palacios. "High-Performance WSe2 Complementary Metal Oxide Semiconductor Technology and Integrated Circuits." Nano Letters 15, no. 8 (July 28, 2015): 4928–34. http://dx.doi.org/10.1021/acs.nanolett.5b00668.

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11

Smaal, Wiljan, Charlotte Kjellander, Yongbin Jeong, Ashutosh Tripathi, Bas van der Putten, Antonio Facchetti, Henry Yan, et al. "Complementary integrated circuits on plastic foil using inkjet printed n- and p-type organic semiconductors: Fabrication, characterization, and circuit analysis." Organic Electronics 13, no. 9 (September 2012): 1686–92. http://dx.doi.org/10.1016/j.orgel.2012.05.022.

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12

Altet, Josep, Enrique Barajas, Diego Mateo, Alexandre Billong, Xavier Aragones, Xavier Perpiñà, and Ferran Reverter. "BPF-Based Thermal Sensor Circuit for On-Chip Testing of RF Circuits." Sensors 21, no. 3 (January 26, 2021): 805. http://dx.doi.org/10.3390/s21030805.

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A new sensor topology meant to extract figures of merit of radio-frequency analog integrated circuits (RF-ICs) was experimentally validated. Implemented in a standard 0.35 μm complementary metal-oxide-semiconductor (CMOS) technology, it comprised two blocks: a single metal-oxide-semiconductor (MOS) transistor acting as temperature transducer, which was placed near the circuit to monitor, and an active band-pass filter amplifier. For validation purposes, the temperature sensor was integrated with a tuned radio-frequency power amplifier (420 MHz) and MOS transistors acting as controllable dissipating devices. First, using the MOS dissipating devices, the performance and limitations of the different blocks that constitute the temperature sensor were characterized. Second, by using the heterodyne technique (applying two nearby tones) to the power amplifier (PA) and connecting the sensor output voltage to a low-cost AC voltmeter, the PA’s output power and its central frequency were monitored. As a result, this topology resulted in a low-cost approach, with high linearity and sensitivity, for RF-IC testing and variability monitoring.

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13

Elmezayen, Mohamed R., Wei Hu, Amr M. Maghraby, Islam T. Abougindia, and Suat U. Ay. "Accurate Analysis and Design of Integrated Single Input Schmitt Trigger Circuits." Journal of Low Power Electronics and Applications 10, no. 3 (June 29, 2020): 21. http://dx.doi.org/10.3390/jlpea10030021.

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Schmitt trigger (ST) circuits are widely used integrated circuit (IC) blocks with hysteretic input/output (I/O) characteristics. Like the I/O characteristics of a living neuron, STs reject noise and provide stability to systems that they are deployed in. Indeed, single-input/single-output (SISO) STs are likely candidates to be the core unit element in artificial neural networks (ANNs) due not only to their similar I/O characteristics but also to their low power consumption and small silicon footprints. This paper presents an accurate and detailed analysis and design of six widely used complementary metal-oxide-semiconductor (CMOS) SISO ST circuits. The hysteresis characteristics of these ST circuits were derived for hand calculations and compared to original design equations and simulation results. Simulations were carried out in a well-established, 0.35 μm/3.3 V, analog/mixed-signal CMOS process. Additionally, simulations were performed using a wide range of supplies and process variations, but only 3.3 V supply results are presented. Most of the new design equations provide better accuracy and insights, as broad assumptions of original derivations were avoided.

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14

Dai, Ching-Liang, and Mao-Chen Liu. "Complementary Metal–Oxide–Semiconductor Microelectromechanical Pressure Sensor Integrated with Circuits on Chip." Japanese Journal of Applied Physics 46, no. 2 (February 8, 2007): 843–48. http://dx.doi.org/10.1143/jjap.46.843.

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15

Chen, Hongda, Zan Zhang, Beiju Huang, Luhong Mao, and Zanyun Zhang. "Progress in complementary metal–oxide–semiconductor silicon photonics and optoelectronic integrated circuits." Journal of Semiconductors 36, no. 12 (December 2015): 121001. http://dx.doi.org/10.1088/1674-4926/36/12/121001.

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16

Shoga, M., and D. Binder. "Theory of Single Event Latchup in Complementary Metal-Oxide Semiconductor Integrated Circuits." IEEE Transactions on Nuclear Science 33, no. 6 (1986): 1714–17. http://dx.doi.org/10.1109/tns.1986.4334671.

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17

Lee, Changyeop, Gyuseong Cho, Troy Unruh, Seop Hur, and Inyong Kwon. "Integrated Circuit Design for Radiation-Hardened Charge-Sensitive Amplifier Survived up to 2 Mrad." Sensors 20, no. 10 (May 12, 2020): 2765. http://dx.doi.org/10.3390/s20102765.

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According to the continuous development of metal-oxide semiconductor (MOS) fabrication technology, transistors have naturally become more radiation-tolerant through steadily decreasing gate-oxide thickness, increasing the tunneling probability between gate-oxide and channel. Unfortunately, despite this radiation-hardened property of developed transistors, the field of nuclear power plants (NPPs) requires even higher radiation hardness levels. Particularly, total ionizing dose (TID) of approximately 1 Mrad could be required for readout circuitry under severe accident conditions with 100 Mrad around a reactor in-core required. In harsh radiating environments such as NPPs, sensors such as micro-pocket-fission detectors (MPFD) would be a promising technology to be operated for detecting neutrons in reactor cores. For those sensors, readout circuits should be fundamentally placed close to sensing devices for minimizing signal interferences and white noise. Therefore, radiation hardening ability is necessary for the circuits under high radiation environments. This paper presents various integrated circuit designs for a radiation hardened charge-sensitive amplifier (CSA) by using SiGe 130 nm and Si 180 nm fabrication processes with different channel widths and transistor types of complementary metal-oxide-semiconductor (CMOS) and bipolar CMOS (BiCMOS). These circuits were tested under γ–ray environment with Cobalt-60 of high level activity: 490 kCi. The experiment results indicate amplitude degradation of 2.85%–34.3%, fall time increase of 201–1730 ns, as well as a signal-to-noise ratio (SNR) of 0.07–11.6 dB decrease with irradiation dose increase. These results can provide design guidelines for radiation hardening operational amplifiers in terms of transistor sizes and structures.

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18

Li, Yunpeng, Jiawei Zhang, Jin Yang, Yvzhuo Yuan, Zhenjia Hu, Zhaojun Lin, Aimin Song, and Qian Xin. "Complementary Integrated Circuits Based on n-Type and p-Type Oxide Semiconductors for Applications Beyond Flat-Panel Displays." IEEE Transactions on Electron Devices 66, no. 2 (February 2019): 950–56. http://dx.doi.org/10.1109/ted.2018.2887270.

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Aylapogu, Pramod Kumar, B. L. V. S. S. Aditya, G. Sony, Ch Prasanna, A. Satish, G. Sony, G. Sony, et al. "Estimation of power and delay in CMOS circuits using LCT." Indonesian Journal of Electrical Engineering and Computer Science 14, no. 2 (May 1, 2019): 990. http://dx.doi.org/10.11591/ijeecs.v14.i2.pp990-998.

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<p>With a rapid growth in semiconductor Industry, complex applications are being implemented using small size chips, with the use of Complementary Metal Oxide Semi-Conductors (CMOS). With the introduction of new Integrated Circuit (IC) technology, the speed of the circuits has been increased by around 30%. But it was observed that for every two years, the power dissipation of a circuit doubles. The main reason for this power dissipation is leakage currents in the circuit. To reduce these leakage currents, we can reduce the width of the device. In addition to this, we can use lector techniques that use Leakage Control Transistors (LCT) and High Threshold Leakage Control Transistors(HTLCT). In this paper, we present a circuit technique that uses 130 nano-meter CMOS VLSI circuits that use two extra transistors to mitigate the leakage currents. The estimation of power and delay will be discussed using LCT’s and HTLCT’s</p>

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20

Jeong, Kyungsoo, Duckhoon Ro, Gwanho Lee, Myounggon Kang, and Hyung-Min Lee. "A Radiation-Hardened Instrumentation Amplifier for Sensor Readout Integrated Circuits in Nuclear Fusion Applications." Electronics 7, no. 12 (December 12, 2018): 429. http://dx.doi.org/10.3390/electronics7120429.

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A nuclear fusion reactor requires a radiation-hardened sensor readout integrated circuit (IC), whose operation should be tolerant against harsh radiation effects up to MGy or higher. This paper proposes radiation-hardening circuit design techniques for an instrumentation amplifier (IA), which is one of the most sensitive circuits in the sensor readout IC. The paper studied design considerations for choosing the IA topology for radiation environments and proposes a radiation-hardened IA structure with total-ionizing-dose (TID) effect monitoring and adaptive reference control functions. The radiation-hardened performance of the proposed IA was verified through model-based circuit simulations by using compact transistor models that reflected the TID effects into complementary metal–oxide–semiconductor (CMOS) parameters. The proposed IA was designed with the 65 nm standard CMOS process and provides adjustable voltage gain between 3 and 15, bandwidth up to 400 kHz, and power consumption of 34.6 μW, while maintaining a stable performance over TID effects up to 1 MGy.

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Krusius, J. P. "Process modeling for submicron complementary metal‐oxide‐semiconductor very large scale integrated circuits." Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films 4, no. 3 (May 1986): 905–11. http://dx.doi.org/10.1116/1.574005.

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KAMIMURA, Hiroshi, and Masaharu SAKAGAMI. "Prediction Method for Total Dose Effects on Complementary Metal Oxide Semiconductor Integrated Circuits." Journal of Nuclear Science and Technology 27, no. 3 (March 1990): 215–21. http://dx.doi.org/10.1080/18811248.1990.9731173.

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23

Ellinger, Frank, David Fritsche, Gregor Tretter, Jan Dirk Leufker, Uroschanit Yodprasit, and C. Carta. "Review of Millimeter-Wave Integrated Circuits With Low Power Consumption for High Speed Wireless Communications." Frequenz 71, no. 1-2 (January 1, 2017): 1–9. http://dx.doi.org/10.1515/freq-2016-0119.

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Abstract In this paper we review high-speed radio-frequency integrated circuits operating up to 210 GHz and present selected state-of-the-art circuits with leading-edge performance, which we have designed at our chair. The following components are discussed employing bipolar complementary metal oxide semiconductors (BiCMOS) technologies: a 200 GHz amplifier with 17 dB gain and around 9 dB noise figure consuming only 18 mW, a 200 GHz down mixer with 5.5 dB conversion gain and 40 mW power consumption, a 190 GHz receiver with 47 dB conversion gain and 11 dB noise figure and a 60 GHz power amplifier with 24.5 dBm output power and 12.9 % power added efficiency (PAE). Moreover, we report on a single-core flash CMOS analogue-to-digital converter (ADC) with 3 bit resolution and a speed of 24 GS/s. Finally, we discuss a 60 GHz on-off keying (OOK) BiCMOS transceiver chip set. The wireless transmission of data with 5 Gb/s at 42 cm distance between transmitter and receiver was verified by experiments. The complete transceiver consumes 396 mW.

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24

Akturk, Akin, Neil Goldsman, Ahayi Ahyi, Sarit Dhar, Brendan Cusack, and Minseo Park. "SPICE Modeling of Advanced Silicon Carbide High Temperature Integrated Circuits." Materials Science Forum 858 (May 2016): 1070–73. http://dx.doi.org/10.4028/www.scientific.net/msf.858.1070.

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Due to the wide band-gap and high thermal conductivity of the 4H polytype of silicon carbide (SiC) as well as the maturity of this polytype’s fabrication processes, 4H-SiC offers an extremely attractive wide bandgap semiconductor technology for harsh environment applications spanning a variety of markets. To this end, 4H-SiC power electronics is gradually emerging as the technology of choice for next-generation power electronics; however, relatively limited progress has been made with regards to silicon carbide integrated circuits (ICs). We address this problem by developing fabrication and design methods for the SiC IC components themselves, as well as complementary SPICE type compact models for these components, and thereby facilitate the development of future SiC ICs and Process Design Kits (PDKs).

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D., Vaithiyanathan, Megha Singh Kurmi, Alok Kumar Mishra, and Britto Pari J. "Performance analysis of multi-scaling voltage level shifter for low-power applications." World Journal of Engineering 17, no. 6 (August 17, 2020): 803–9. http://dx.doi.org/10.1108/wje-02-2020-0043.

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Purpose In complementary metal-oxide-semiconductor (CMOS) logic circuits, there is a direct square proportion of supply voltage on dynamic power. If the supply voltage is high, then more amount of energy will be consumed. Therefore, if a low voltage supply is used, then dynamic power will also be reduced. In a mixed signal circuit, there can be a situation when lower voltage circuitry has to drive large voltage circuitry. In such a case, P-type metal-oxide-semiconductor of high-voltage circuitry may not be switched off completely by applying a low voltage as input. Therefore, there is a need for level shifter where low-voltage and high-voltage circuits are connected. In this paper the multi-scaling voltage level shifter is presented which overcomes the contention problems and suitable for low-power applications. Design/methodology/approach The voltage level shifter circuit is essential for digital and analog circuits in the on-chip integrated circuits. The modified voltage level shifter and reported energy-efficient voltage level shifter have been optimally designed to be functional in all process voltage and temperature corners for VDDH = 5V, VDDL = 2V and the input frequency of 5 MHz. The modified voltage level shifter and reported shifter circuits are implemented using Cadence Virtuoso at 90 nm CMOS technology and the comparison is made based on speed and power consumed by the circuit. Findings The voltage level shifter circuit discussed in this paper removes the contention problem that is present in conventional voltage level shifter. Moreover, it has the capability for up and down conversion and reduced power and delay as compared to conventional voltage level shifter. The efficiency of the circuit is improved in two ways, first, the current of the pull-up device is reduced and second, the strength of the pull-down device is increased. Originality/value The modified level shifter is faster for switching low input voltage to high output voltage and also high input voltage to low output voltage. The average power consumption for the multi-scaling voltage level shifter is 259.445 µW. The power consumption is very less in this technique and it is best suitable for low-power applications.

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Kumar, Aylapogu Pramod, B. L. V. S. S. Aditya, G. Sony, Ch Prasanna, and A. Satish. "Estimation of Power and Delay in CMOS Circuits using Leakage Control Transistor." Carpathian Journal of Electronic and Computer Engineering 11, no. 2 (December 1, 2018): 25–28. http://dx.doi.org/10.2478/cjece-2018-0014.

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Abstract With a rapid growth in semiconductor Industry, complex applications are being implemented using small size chips, with the use of Complementary Metal Oxide Semi-Conductors (CMOS). With the introduction of new Integrated Circuit (IC) technology, the speed of the circuits has been increased by around 30%. But it was observed that for every two years, the power dissipation of a circuit doubles. The main reason for this power dissipation is leakage currents in the circuit. To reduce these leakage currents, we can reduce the width of the device. In addition to this, we can use lector techniques that use Leakage Control Transistors (LCT) and High Threshold Leakage Control Transistors (HTLCT).In this paper; we present a circuit technique that uses 130 nano-meter CMOS VLSI circuits that use two extra transistors to mitigate the leakage currents. The proposed technique overcomes the limitations posed by the existing methods for leakage reductions an average leakage reductions is 82.5%.The estimation of power and delay will be discussed using LCT’s and HTLCT’s.

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Liu, Zilong, Xiaosuo Wu, Huifu Xiao, Xu Han, Wenping Chen, Miaomiao Liao, Ting Zhao, Hao Jia, Jianhong Yang, and Yonghui Tian. "On-chip optical parity checker using silicon photonic integrated circuits." Nanophotonics 7, no. 12 (October 30, 2018): 1939–48. http://dx.doi.org/10.1515/nanoph-2018-0140.

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AbstractThe optical parity checker plays an important role in error detection and correction for high-speed, large-capacity, complex digital optical communication networks, which can be employed to detect and correct the error bits by using a specific coding theory such as introducing error-detecting and correcting codes in communication channels. In this paper, we report an integrated silicon photonic circuit that is capable of implementing the parity checking for binary string with an arbitrary number of bits. The proposed parity checker consisting of parallel cascaded N micro-ring resonators (MRRs) is based on directed logic scheme, which means that the operands applied to MRRs to control the switching states of the MRRs are electrical signals, the operation signals are optical signals, and the final operation results are obtained at the output ports in the form of light. A 3-bit parity checker with an operation speed of 10 kbps, fabricated on a silicon-on-insulator (SOI) platform using a standard commercial complementary metal-oxide-semiconductor (CMOS) process, was experimentally and successfully demonstrated.

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SWARTZ, ROBERT G. "PERFORMANCE AT THE EDGE: GALLIUM ARSENIDE AND SILICON ICs FOR OPTICAL ELECTRONICS." International Journal of High Speed Electronics and Systems 02, no. 03 (September 1991): 147–62. http://dx.doi.org/10.1142/s0129156491000077.

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Compound semiconductor technology is rapidly entering the mainstream, and is quickly finding its way into consumer applications where high performance is paramount. But silicon integrated circuit technology is evolving up the performance curve, and CMOS in particular is consuming ever more market share. Nowhere is this contest more clearly evident than in optical communications. Here applications demand performance ranging from a few hundreds of megahertz to multi-gigahertz, from circuits containing anywhere from tens to tens of thousands of devices. This paper reviews the high performance electronics found in optical communication applications from a technology standpoint, illustrating merits and market trends for these competing, yet often complementary IC technologies.

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Chauhan, Manorama, Ravindra Singh Kushwah, Pavan Shrivastava, and Shyam Akashe. "Analysis and Simulation of a Low-Leakage Analog Single Gate and FinFET Circuits." International Journal of Nanoscience 13, no. 02 (April 2014): 1450012. http://dx.doi.org/10.1142/s0219581x14500124.

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In the world of Integrated Circuits, complementary metal–oxide–semiconductor (CMOS) has lost its ability during scaling beyond 50 nm. Scaling causes severe short channel effects (SCEs) which are difficult to suppress. FinFET devices undertake to replace usual Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) because of their better ability in controlling leakage and diminishing SCEs while delivering a strong drive current. In this paper, we present a relative examination of FinFET with the double gate MOSFET (DGMOSFET) and conventional bulk Si single gate MOSFET (SGMOSFET) by using Cadence Virtuoso simulation tool. Physics-based numerical two-dimensional simulation results for FinFET device, circuit power is presented, and classifying that FinFET technology is an ideal applicant for low power applications. Exclusive FinFET device features resulting from gate–gate coupling are conversed and efficiently exploited for optimal low leakage device design. Design trade-off for FinFET power and performance are suggested for low power and high performance applications. Whole power consumptions of static and dynamic circuits and latches for FinFET device, believing state dependency, show that leakage currents for FinFET circuits are reduced by a factor of over ~ 10X, compared to DGMOSFET and ~ 20X compared with SGMOSFET.

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Huang, Tsung-Ching, Ting Lei, Leilai Shao, Sridhar Sivapurapu, Madhavan Swaminathan, Zhenan Bao, Kwang-Ting Cheng, and Raymond Beausoleil. "Process Design Kit and Design Automation for Flexible Hybrid Electronics." Journal of Microelectronics and Electronic Packaging 16, no. 3 (July 1, 2019): 117–23. http://dx.doi.org/10.4071/imaps.925849.

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Abstract High-performance low-cost flexible hybrid electronics (FHE) are desirable for applications such as internet of things and wearable electronics. Carbon nanotube (CNT) thin-film transistor (TFT) is a promising candidate for high-performance FHE because of its high carrier mobility, superior mechanical flexibility, and material compatibility with low-cost printing and solution processes. Flexible sensors and peripheral CNT-TFT circuits, such as decoders, drivers, and sense amplifiers, can be printed and hybrid-integrated with thinned (<50 μm) silicon chips on soft, thin, and flexible substrates for a wide range of applications, from flexible displays to wearable medical devices. Here, we report (1) a process design kit (PDK) to enable FHE design automation for large-scale FHE circuits and (2) solution process-proven intellectual property blocks for TFT circuits design, including Pseudo-Complementary Metal-Oxide-Semiconductor (Pseudo-CMOS) flexible digital logic and analog amplifiers. The FHE-PDK is fully compatible with popular silicon design tools for design and simulation of hybrid-integrated flexible circuits.

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Moon, Dongwoo, Milim Lee, Changhyun Lee, Joung-Hu Park, and Changkun Park. "Wireless Transceiver for Three-Dimensional Integrated Circuits Using a Ring Oscillator." Journal of Circuits, Systems and Computers 29, no. 10 (December 9, 2019): 2050161. http://dx.doi.org/10.1142/s0218126620501613.

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In this paper, we propose an oscillation-type transceiver for wireless chip-to-chip communication (WCC). The proposed transceiver is composed of a ring oscillator, coils, inverter-type amplifier, voltage multiplier and comparator. The ring oscillator itself acts as the on–off keying (OOK) modulator. The envelope of the transferred OOK-modulated signal is detected in the voltage multiplier of the receiver. Given that the proposed transceiver uses an OOK-modulated oscillating signal, the noise immunity is improved compared to the typical pulse-type transceiver. To verify the functionality of the proposed transceiver, we design the transceiver using the 180-nm complementary metal-oxide-semiconductor process. From the measured results, we verify that the proposed transceiver recovers the entered digital signal up to a distance of 0.2[Formula: see text]mm between the primary and secondary coils. Additionally, the sensitivity to the bias voltage of the latch is nonexistent by virtue of removing the latch in the proposed transceiver.

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Zhu, Shiyang, T. Y. Liow, G. Q. Lo, and D. L. Kwong. "Fully complementary metal-oxide-semiconductor compatible nanoplasmonic slot waveguides for silicon electronic photonic integrated circuits." Applied Physics Letters 98, no. 2 (January 10, 2011): 021107. http://dx.doi.org/10.1063/1.3537964.

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Valenti, Lorenzo, Marcello Dalpasso, and Michele Favalli. "Efficient testing of multi‐output combinational cells in nano‐complementary metal oxide semiconductor integrated circuits." IET Computers & Digital Techniques 8, no. 2 (March 2014): 83–89. http://dx.doi.org/10.1049/iet-cdt.2013.0077.

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Kladovščikov, Leonid, Marijan Jurgo, and Romualdas Navickas. "Design of an Oscillation-Based BIST System for Active Analog Integrated Filters in 0.18 µm CMOS." Electronics 8, no. 7 (July 20, 2019): 813. http://dx.doi.org/10.3390/electronics8070813.

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In this paper, an oscillation-based built-in self-test system for active an analog integrated circuit is presented. This built-in self-test system was used to detect catastrophic and parametric faults, introduced during chip manufacturing. As circuits under test (CUT), second-order Sallen-Key, Akerberg-Mossberg and Tow-Thomas biquad filters were designed. The proposed test hardware detects parametric and catastrophic faults on changeable limits. The influence of both oscillation and test hardware on fault detection limits were investigated and analyzed. The proposed oscillation based self-test system was designed and simulated in 0.18 µm complementary metal-oxide semiconductor (CMOS) technology. Due to the easiness of implementation and configuration for testing of different active analog filters, such self-test systems can be effectively used in modern integrated circuits, made of a large number of devices and circuits, such as the multi-standard transceivers used in the core hardware of software-defined radios. Using the proposed test strategy, the fault tolerance limits for catastrophic faults varied from 96% to 100% for all injected faults in different structures of low pass filters (LPF). The detection range of parametric faults of passive components’ nominal value, depending on the used structure of the filter, did not exceed –0.74% – 0.72% in case of Sallen-Key, –3.31% – 1.00% in case of Akerberg-Mossberg and –2.39% – 1.44% in case of Tow-Thomas LPF.

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Houssa, Michel, Evgueni Chagarov, and Andrew Kummel. "Surface Defects and Passivation of Ge and III–V Interfaces." MRS Bulletin 34, no. 7 (July 2009): 504–13. http://dx.doi.org/10.1557/mrs2009.138.

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AbstractThe need for high-κ gate dielectrics and metal gates in advanced integrated circuits has reopened the door to Ge and III–V compounds as potential replacements for silicon channels, offering the possibility to further increase the performances of complementary metal oxide semiconductor (CMOS) circuits, as well as adding new functionalities. Yet, a fundamental issue related to high-mobility channels in CMOS circuits is the electrical passivation of their interfaces (i.e., achieving a low density of interface defects) approaching state-of-the-art Si-based devices. Here we discuss promising approaches for the passivation of Ge and III–V compounds and highlight insights obtained by combining experimental characterization techniques with first-principles simulations.

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Wang, Chien-Ping, Ying-Chun Shen, Peng-Chun Liou, Yu-Lun Chueh, Yue-Der Chih, Jonathan Chang, Chrong-Jung Lin, and Ya-Chin King. "Dynamic pH Sensor with Embedded Calibration Scheme by Advanced CMOS FinFET Technology." Sensors 19, no. 7 (April 2, 2019): 1585. http://dx.doi.org/10.3390/s19071585.

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In this work, we present a novel pH sensor using efficient laterally coupled structure enabled by Complementary Metal-Oxide Semiconductor (CMOS) Fin Field-Effect Transistor (FinFET) processes. This new sensor features adjustable sensitivity, wide sensing range, multi-pad sensing capability and compatibility to advanced CMOS technologies. With a self-balanced readout scheme and proposed corresponding circuit, the proposed sensor is found to be easily embedded into integrated circuits (ICs) and expanded into sensors array. To ensure the robustness of this new device, the transient response and noise analysis are performed. In addition, an embedded calibration operation scheme is implemented to prevent the proposed sensing device from the background offset from process variation, providing reliable and stable sensing results.

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Génin, J., and R. Charachon. "Experimental Basis and Design of a New Cochlear Prosthesis System." Annals of Otology, Rhinology & Laryngology 96, no. 1_suppl (January 1987): 76–79. http://dx.doi.org/10.1177/00034894870960s138.

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In a multichannel cochlear prosthesis, electrical interactions between electrodes impose severe limitations on dynamic range and selectivity. We present a theoretical model to cope with these limitations. Building a successful cochlear implant requires full custom-integrated circuits. We present the design of such a device, implemented in complementary metal oxide semiconductor technology. The area of the chip is 9 mm2 and it can stimulate 15 cochlear electrodes with current impulses.

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Zawawi, Ruhaifi Bin Abdullah, Hojong Choi, and Jungsuk Kim. "High PSRR Wide Supply Range Dual-Voltage Reference Circuit for Bio-Implantable Applications." Electronics 10, no. 16 (August 21, 2021): 2024. http://dx.doi.org/10.3390/electronics10162024.

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On-chip systems are challenging owing to the limited size of the components, such as the capacitor bank in the rectifier. With a small on-chip capacitor, the output voltage of the rectifier might ring if the circuit experiences significant changes in current. The reference circuit is the first block after the rectifier, and the entire system relies on its robustness. A fully integrated dual-voltage reference circuit for bio-implantable applications is presented. The proposed circuit utilizes nonlinear current compensation techniques that significantly decrease supply variations and reject high-supply ripples for various frequencies. The reference circuit was verified using a 0.35 µm complementary metal-oxide semiconductor (CMOS) process. Maximum PSRR values of −112 dB and −128 dB were obtained. With a supply range from 2.8 to 12 V, the proposed design achieves 0.916 and 1.5 mV/V line regulation for the positive and negative reference circuits, respectively.

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Prinzie, Jeffrey, Karel Appels, and Szymon Kulis. "Optimal Physical Implementation of Radiation Tolerant High-Speed Digital Integrated Circuits in Deep-Submicron Technologies." Electronics 8, no. 4 (April 14, 2019): 432. http://dx.doi.org/10.3390/electronics8040432.

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This paper presents a novel scalable physical implementation method for high-speed Triple Modular Redundant (TMR) digital integrated circuits in radiation-hard designs. The implementation uses a distributed placement strategy compared to a commonly used bulk 3-bank constraining method. TMR netlist information is used to optimally constrain the placement of both sequential cells and combinational cells. This approach significantly reduces routing complexity, net lengths and dynamic power consumption with more than 60% and 20% respectively. The technique was simulated in a 65 nm Complementary Metal-Oxide Semiconductor (CMOS) technology.

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Soref, Richard. "Applications of Silicon-Based Optoelectronics." MRS Bulletin 23, no. 4 (April 1998): 20–24. http://dx.doi.org/10.1557/s0883769400030220.

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Silicon-based optoelectronics is a diversified technology that has grown steadily but not exponentially over the past decade. Some applications—such as smart-pixel signal processing and chip-to-chip optical interconnects—have enjoyed impressive growth, whereas other applications have remained quiescent. A few important applications such as optical diagnosis of leaky metal-oxide-semiconductor-field-effect-transistor circuits, have appeared suddenly. Over the years, research and development has unveiled some unique and significant aspects of Si-based optoelectronics. The main limitation of this technology is the lack of practical silicon light sources—Si lasers and efficient Si light-emitting devices (LEDs)—though investigators are “getting close” to the LED.Silicon-based optoelectronics refers to the integration of photonic and electronic components on a Si chip or wafer. The photonics adds value to the electronics, and the electronics offers low-cost mass-production benefits. The electronics includes complementary-metal-oxide semiconductors (CMOS), very large-scale integration (VLSI), bipolar CMOS, SiGe/Si heterojunction bipolar transistors, and heterostructure field-effect transistors. In this discussion, we will use a loose definition of optoelectronics that includes photonic and optoelectronic integrated circuits (PICs and OEICs), Si optical benches, and micro-optoelectromechanical (MOEM) platforms. Optoelectronic chips and platforms are subsystems of computer systems, communication networks, etc. Silicon substrates feature a superior native oxide, in addition to excellent thermal, mechanical, and economic properties. Silicon wafers “shine” as substrates for PICs and OEICs.

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Krochin-Yepez, Pedro-Andrei, Ulrike Scholz, and Andre Zimmermann. "CMOS-Compatible Measures for Thermal Management of Phase-Sensitive Silicon Photonic Systems." Photonics 7, no. 1 (January 1, 2020): 6. http://dx.doi.org/10.3390/photonics7010006.

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To date, several photonic applications have been demonstrated without considerable thermal management efforts. However, in phase-sensitive photonic applications, thermal management becomes of utmost importance. Thermal management of photonic systems requires not only efficient heat dissipation, but also reduction of on-chip temperature gradients. Particularly in highly integrated systems, in which several components are integrated within a single photonic integrated circuit, the reduction of on-chip temperature gradients is necessary to guarantee the correct functionality of the system. Due to their high integration density as well as their extreme temperature sensitivity, optical phased arrays are ideal examples of a system, where thermal management is required. Ideally, thermal management solutions of such systems should not require additional power for operation. Therefore, it is desired to improve the heat dissipation and to reduce temperature gradients by structural modifications of the photonic circuit. Furthermore, to cope with the advantages of silicon photonics, thermal management solutions must be compatible with series fabrication processes. In this work, complementary metal–oxide–semiconductor (CMOS)-compatible measures for thermal management of silicon photonic integrated circuits are proposed and validated by characterization of in-house fabricated thermal demonstrators. The proposed concepts are extremely efficient not only in reducing temperature gradients, but also in improving the heat dissipation from integrated heat sources.

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Asghar, Malik Summair, Saad Arslan, and Hyungwon Kim. "A Low-Power Spiking Neural Network Chip Based on a Compact LIF Neuron and Binary Exponential Charge Injector Synapse Circuits." Sensors 21, no. 13 (June 29, 2021): 4462. http://dx.doi.org/10.3390/s21134462.

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To realize a large-scale Spiking Neural Network (SNN) on hardware for mobile applications, area and power optimized electronic circuit design is critical. In this work, an area and power optimized hardware implementation of a large-scale SNN for real time IoT applications is presented. The analog Complementary Metal Oxide Semiconductor (CMOS) implementation incorporates neuron and synaptic circuits optimized for area and power consumption. The asynchronous neuronal circuits implemented benefit from higher energy efficiency and higher sensitivity. The proposed synapse circuit based on Binary Exponential Charge Injector (BECI) saves area and power consumption, and provides design scalability for higher resolutions. The SNN model implemented is optimized for 9 × 9 pixel input image and minimum bit-width weights that can satisfy target accuracy, occupies less area and power consumption. Moreover, the spiking neural network is replicated in full digital implementation for area and power comparisons. The SNN chip integrated from neuron and synapse circuits is capable of pattern recognition. The proposed SNN chip is fabricated using 180 nm CMOS process, which occupies a 3.6 mm2 chip core area, and achieves a classification accuracy of 94.66% for the MNIST dataset. The proposed SNN chip consumes an average power of 1.06 mW—20 times lower than the digital implementation.

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Jendernalik, W., G. Blakiewicz, A. Handkiewicz, and M. Melosik. "Analogue CMOS ASICs in Image Processing Systems." Metrology and Measurement Systems 20, no. 4 (December 1, 2013): 613–22. http://dx.doi.org/10.2478/mms-2013-0052.

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Abstract In this paper a survey of analog application specific integrated circuits (ASICs) for low-level image processing, called vision chips, is presented. Due to the specific requirements, the vision chips are designed using different architectures best suited to their functions. The main types of the vision chip architectures and their properties are presented and characterized on selected examples of prototype integrated circuits (ICs) fabricated in complementary metal oxide semiconductor (CMOS) technologies. While discussing the vision chip realizations the importance of low-cost, low-power solutions is highlighted, which are increasingly being used in intelligent consumer equipment. Thanks to the great development of the automated design environments and fabrication methods, new, so far unknown applications of the vision chips become possible, as for example disposable endoscopy capsules for photographing the human gastrointestinal tract for the purposes of medical diagnosis.

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Song, Hang, Afreen Azhari, Xia Xiao, Eiji Suematsu, Hiromasa Watanabe, and Takamaro Kikkawa. "Microwave Imaging Using CMOS Integrated Circuits with Rotating 4 × 4 Antenna Array on a Breast Phantom." International Journal of Antennas and Propagation 2017 (2017): 1–13. http://dx.doi.org/10.1155/2017/6757048.

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A digital breast cancer detection system using 65 nm technology complementary metal oxide semiconductor (CMOS) integrated circuits with rotating 4 × 4 antenna array is presented. Gaussian monocycle pulses are generated by CMOS logic circuits and transmitted by a 4 × 4 matrix antenna array via two CMOS single-pole-eight-throw (SP8T) switching matrices. Radar signals are received and converted to digital signals by CMOS equivalent time sampling circuits. By rotating the 4 × 4 antenna array, the reference signal is obtained by averaging the waveforms from various positions to extract the breast phantom target response. A signal alignment algorithm is proposed to compensate the phase shift of the signals caused by the system jitter. After extracting the scattered signal from the target, a bandpass filter is applied to reduce the noise caused by imperfect subtraction between original and the reference signals. The confocal imaging algorithm for rotating antennas is utilized to reconstruct the breast image. A 1 cm3 bacon block as a cancer phantom target in a rubber substrate as a breast fat phantom can be detected with reduced artifacts.

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Lopez-Diaz, Daniel, Ingmar Kallfass, Axel Tessmann, Rainer Weber, Hermann Massler, Arnulf Leuther, Michael Schlechtweg, and Oliver Ambacher. "High-performance 60 GHz MMICs for wireless digital communication in 100 nm mHEMT technology." International Journal of Microwave and Wireless Technologies 3, no. 2 (March 3, 2011): 107–13. http://dx.doi.org/10.1017/s1759078711000109.

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Wireless data communication is pushing towards 60 GHz and will most likely be served by SiGe and Complementary Metal Oxide Semiconductor (CMOS) technologies in the consumer market. Nevertheless, some applications are imposing superior performance requirements on the analog frontend, and employing III-V compound semiconductors can provide significant advantages with respect to transmitter power and noise figure. In this paper, we present essential building blocks and a novel single-chip low complexity transceiver Monolithic Microwave Integrated Circuit (MMIC) with integrated antenna switches for 60 GHz communication, fabricated in a 100 nm metamorphic high electron mobility transistor (mHEMT) technology. This technology features a measured noise figure of <2.5 dB in low-noise amplifiers at 60 GHz and the realized medium power amplifiers achieve more than 20 dBm saturated output power. Integrated antenna switches with an insertion loss of less than 1.5 dB enable the integration of the transmit and the receive stages on a single chip. A single-chip transceiver with external subharmonic Local Oscillator (LO) supply for its I/Q down- and up-converter achieves a linear conversion gain in both, the Transmit (Tx) and the Receive (Rx) paths, of more than 10 dB.

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Sofeoul-Al-Mamun, Md, Mohammad Badrul Alam Miah, and Fuyad Al Masud. "A Novel Design and Implementation of 8-3 Encoder Using Quantum-dot Cellular Automata (QCA) Technology." European Scientific Journal, ESJ 13, no. 15 (May 31, 2017): 254. http://dx.doi.org/10.19044/esj.2017.v13n15p254.

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In recent years Quantum-dot Cellular Automata (QCA) has been considered one of the emerging nano-technology for future generation digital circuits and systems. QCA technology is a promising alternative to Complementary Metal Oxide Semiconductor (CMOS) technology. Thus, QCA offers a novel electronics paradigm for information processing and communication system. It has attractive features such as faster speed, higher scale integration, higher switching frequency, smaller size and low power consumption compared to the transistor based technology. It is projected as a promising nanotechnology for future Integrated Circuits (ICs). A quantum dot cellular automaton complex gate is composed from simple 3-input majority gate. In this paper, a 8-3 encoder circuit is proposed based on QCA logic gates: the 4-input Majority Voter (MV) OR gate. This 7-input gate can be configured into many useful gate structures such as a 4-input AND gate, a 4-input OR gate, 2-input AND and 2-input OR gates, 2-input complex gates, multi-input complex gates. The proposed circuit has a promising future in the area of nano-computing information processing system and can be stimulated with higher digital applications in QCA.

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Rathore, Pradeep Kumar, Brishbhan Singh Panwar, and Jamil Akhtar. "A novel CMOS-MEMS integrated pressure sensing structure based on current mirror sensing technique." Microelectronics International 32, no. 2 (May 5, 2015): 81–95. http://dx.doi.org/10.1108/mi-11-2014-0048.

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Purpose – The present paper aims to propose a basic current mirror-sensing circuit as an alternative to the traditional Wheatstone bridge circuit for the design and development of high-sensitivity complementary metal oxide semiconductor (CMOS)–microelectromechanical systems (MEMS)-integrated pressure sensors. Design/methodology/approach – This paper investigates a novel current mirror-sensing-based CMOS–MEMS-integrated pressure-sensing structure based on the piezoresistive effect in metal oxide field effect transistor (MOSFET). A resistive loaded n-channel MOSFET-based current mirror pressure-sensing circuitry has been designed using 5-μm CMOS technology. The pressure-sensing structure consists of three identical 10-μm-long and 50-μm-wide n-channel MOSFETs connected in current mirror configuration, with its input transistor as a reference MOSFET and output transistors are the pressure-sensing MOSFETs embedded at the centre and near the fixed edge of a silicon diaphragm measuring 100 × 100 × 2.5 μm. This arrangement of MOSFETs enables the sensor to sense tensile and compressive stresses, developed in the diaphragm under externally applied pressure, with respect to the input reference transistor of the mirror circuit. An analytical model describing the complete behaviour of the integrated pressure sensor has been described. The simulation results of the pressure sensor show high pressure sensitivity and a good agreement with the theoretical model has been observed. A five mask level process flow for the fabrication of the current mirror-sensing-based pressure sensor has also been described. An n-channel MOSFET with aluminium gate was fabricated to verify the fabrication process and obtain its electrical characteristics using process and device simulation software. In addition, an aluminium gate metal-oxide semiconductor (MOS) capacitor was fabricated on a two-inch p-type silicon wafer and its CV characteristic curve was also measured experimentally. Finally, the paper presents a comparative study between the current mirror pressure-sensing circuit with the traditional Wheatstone bridge. Findings – The simulated sensitivities of the pressure-sensing MOSFETs of the current mirror-integrated pressure sensor have been found to be approximately 375 and 410 mV/MPa with respect to the reference transistor, and approximately 785 mV/MPa with respect to each other. The highest pressure sensitivities of a quarter, half and full Wheatstone bridge circuits were found to be approximately 183, 366 and 738 mV/MPa, respectively. These results clearly show that the current mirror pressure-sensing circuit is comparable and better than the traditional Wheatstone bridge circuits. Originality/value – The concept of using a basic current mirror circuit for sensing tensile and compressive stresses developed in micro-mechanical structures is new, fully compatible to standard CMOS processes and has a promising application in the development of miniaturized integrated micro-sensors and sensor arrays for automobile, medical and industrial applications.

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Hettick, Mark, Hao Li, Der-Hsien Lien, Matthew Yeh, Tzu-Yi Yang, Matin Amani, Niharika Gupta, Daryl C. Chrzan, Yu-Lun Chueh, and Ali Javey. "Shape-controlled single-crystal growth of InP at low temperatures down to 220 °C." Proceedings of the National Academy of Sciences 117, no. 2 (December 31, 2019): 902–6. http://dx.doi.org/10.1073/pnas.1915786117.

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III–V compound semiconductors are widely used for electronic and optoelectronic applications. However, interfacing III–Vs with other materials has been fundamentally limited by the high growth temperatures and lattice-match requirements of traditional deposition processes. Recently, we developed the templated liquid-phase (TLP) crystal growth method for enabling direct growth of shape-controlled single-crystal III-Vs on amorphous substrates. Although in theory, the lowest temperature for TLP growth is that of the melting point of the group III metal (e.g., 156.6 °C for indium), previous experiments required a minimum growth temperature of 500 °C, thus being incompatible with many application-specific substrates. Here, we demonstrate low-temperature TLP (LT-TLP) growth of single-crystalline InP patterns at substrate temperatures down to 220 °C by first activating the precursor, thus enabling the direct growth of InP even on low thermal budget substrates such as plastics and indium-tin-oxide (ITO)–coated glass. Importantly, the material exhibits high electron mobilities and good optoelectronic properties as demonstrated by the fabrication of high-performance transistors and light-emitting devices. Furthermore, this work may enable integration of III–Vs with silicon complementary metal-oxide-semiconductor (CMOS) processing for monolithic 3D integrated circuits and/or back-end electronics.

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Hijioka, Ken-ichiro, Akira Tanabe, Yasushi Amamiya, and Yoshihiro Hayashi. "Extrasmall-Area Three-Dimensional Solenoid-Shaped Inductor Integrated into High-Speed Signal Processing Complementary Metal–Oxide–Semiconductor Ultralarge-Scale Integrated Circuits." Japanese Journal of Applied Physics 47, no. 4 (April 25, 2008): 2477–83. http://dx.doi.org/10.1143/jjap.47.2477.

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TOMIOKA, Hiroto, Michihiko SUHARA, and Tsugunori OKUMURA. "Broadband Equivalent Circuit Modeling of Self-Complementary Bow-Tie Antennas Monolithically Integrated with Semiconductors for Terahertz Applications." IEICE Transactions on Electronics E92-C, no. 2 (2009): 269–74. http://dx.doi.org/10.1587/transele.e92.c.269.

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Journal articles on the topic 'Complementary Semiconductors Integrated circuits'

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