Relevant bibliographies by topics / Complex Programmable Logic Device (CPLD)

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Complex Programmable Logic Device (CPLD)'

Author: Grafiati
Published: 4 June 2021
Last updated: 12 February 2022

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Journal articles on the topic "Complex Programmable Logic Device (CPLD)"

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Liu, Cheng, Zhe Li, and Jia Jia Hou. "Simulation and Application of PLD in Electric Power System Circuit." Applied Mechanics and Materials 241-244 (December 2012): 1931–35. http://dx.doi.org/10.4028/www.scientific.net/amm.241-244.1931.

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Programmable Logic Device(PLD) has been widely used in hardware circuit, and it has evolved into two types: Complex Programmable Logic Device(CPLD) and Field Programmable Gate Array(FPGA). This paper takes small current grounding in electric power system as background, uses xc95144, a representative CPLD of Xilinx Company in the signal collecting circuit to collect voltage and current signals, and do some other operations to spare circuit board area. This paper also tries to translate the schematic into VHDL-described text and do simulation to the text.
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Zhang, Shi Jun, and Zi Yang Xu. "Research of Automobile Driving Simulator Control System." Applied Mechanics and Materials 575 (June 2014): 771–74. http://dx.doi.org/10.4028/www.scientific.net/amm.575.771.

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This paper introduce a control system of automobile driving simulator, Using the CPLD (Complex Programmable Logic Device) technology can easily achieve detect the states of ignition equipment, steering equipment, clutch equipment, foot-brake equipment, hand-brake equipment, accelerator equipment, shift equipment etc and drive the instrumentation.
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Gołofit, Krzysztof, and Piotr Wieczorek. "Chaos-Based Physical Unclonable Functions." Applied Sciences 9, no. 5 (March 9, 2019): 991. http://dx.doi.org/10.3390/app9050991.

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The concept presented in this paper fits into the current trend of highly secured hardware authentication designs utilizing Physically Unclonable Functions (PUFs) or Physical Obfuscated Keys (POKs). We propose an idea that the PUF cryptographic keys can be derived from a chaotic circuit. We point out that the chaos theory should be explored for the sake of PUFs as a natural mechanism of amplifying random process variations of digital circuits. We prove the idea based on a novel design of a chaotic circuit, which utilizes time in a feedback loop as an analog continuous variable in a purely digital system. Our design is small and simple, and therefore feasible to implement in inexpensive reprogrammable devices (not equipped with digital clock manager, programmable delay line, phase locked loop, RAM/ROM memory, etc.). Preliminary tests proved that the chaotic circuit PUFs work in both advanced Field-Programmable Gate Arrays (FPGAs) as well as simple Complex Programmable Logic Devices (CPLDs). We showed that different PUF challenges (slightly different implementations based on variations in elements placement and/or routing) have provided significantly different keys generated within one CPLD/FPGA device. On the other hand, the same PUF challenges used in a different CPLD/FPGA instance (programmed with precisely the same bit-stream resulting in exactly the same placement and routing) have enhanced differences between devices resulting in different cryptographic keys.
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Cheng, Le Feng, Lin Fei Yin, Bin Zhou, Jing Jiang, and Tao Yu. "Development of New Multi-Function Power Quality On-Line Monitoring Device." Advanced Materials Research 971-973 (June 2014): 928–33. http://dx.doi.org/10.4028/www.scientific.net/amr.971-973.928.

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A power quality on-line monitoring device based on two CPUS is designed and implemented in this paper, which separated the data analysis from the peripheral control completely, used CPLD (Complex Programmable Logic Device) to generate control timing of peripheral devices, made full use of the DSP, so as to meet the requirements of power quality: monitoring precision and real time. The paper firstly introduces the monitor's sampling circuit, communication module circuit, storage module circuit and the flow chart of software. Then, the functions, features and designations of each module are described in detail.
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Kania, Dariusz. "Logic Decomposition for PAL-Based CPLDs." Journal of Circuits, Systems and Computers 24, no. 03 (February 10, 2015): 1550042. http://dx.doi.org/10.1142/s0218126615500425.

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The Programmable Array Logic (PAL)-based logic block is the core of the great majority of Complex Programmable Logic Devices (CPLDs). The purpose of this paper is to compare two models of decomposition dedicated to PAL-based devices. Non-standard usage of decomposition, which leads to the reduction of used PAL-based logic blocks in a programmable structure, is the aim of the presented methods. Each decomposition step is optimized for implementation in a PAL-based structure that is characterized by a PAL-based logic block. The essence of decomposition models is oriented towards minimizing the number of PAL-based logic blocks used and adjusting the designed circuit to fit the structures of PAL-based blocks best. In the experimental section, a comparison of two decomposition models with the classical implementation approach is presented. Results of the experiments prove that the proposed methods lead to a significant reduction of chip area in relation to the classical approach, especially if CPLD structures consist of PAL-based blocks containing a relatively small number of product terms.
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Liu, Li, and Qing Hong Wu. "Image Acquisition Method Based on TMS320DM642." Applied Mechanics and Materials 397-400 (September 2013): 2196–99. http://dx.doi.org/10.4028/www.scientific.net/amm.397-400.2196.

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A method of the image acquisition based on digital signal processor (DSP) is introduced. DSP, complex programmable logic device (CPLD) and contact image sensor (CIS) are combined in the hardware design, and the time-sequence analysis of the image acquisition process is also presented. Practical application indicates that this method has high accuracy and is rapid enough to satisfy the requirement of real-time acquisition.
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He, Yun Chao, Ming Deng, Qi Sheng Zhang, and Xin Jin. "The LED Dot Matrix Control Technology Based on 51 MCU and CPLD." Applied Mechanics and Materials 738-739 (March 2015): 1275–79. http://dx.doi.org/10.4028/www.scientific.net/amm.738-739.1275.

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This paper describes a kind of LED dot matrix control technology based on STC89C51 MCU and complex programmable logic device CPLD, highlighting LED dot matrix display principle and the hardware and software implementation. This design has a flexible and programmable features, to ensure the stability of the system under the premise to achieve a variety of control programs on the LED dot matrix. According to this program,the breadboard adds external data memory, which can be used to extend the external bus, and this design has been successfully used MCU experiment.
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Kubica, Marcin, and Dariusz Kania. "Graph of Outputs in the Process of Synthesis Directed at CPLDs." Mathematics 7, no. 12 (December 3, 2019): 1171. http://dx.doi.org/10.3390/math7121171.

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The paper focuses on the methodology of designing a cyber physical systems (CPS) physical layer using programmable devices. The CPS physical layer can be implemented in programmable devices, which leads to a reduction in their costs and increases their versatility. One of the groups of programmable devices are complex programmable logic devices (CPLDs), which are great for energy-saving, low-cost implementations but requiring flexibility. It becomes necessary to develop mathematical CPS design methods focused on CPLD. This paper presents an original technology mapping method for digital circuits in programmable array logic (PAL)-based CPLDs. The idea is associated with the process of multilevel optimization of circuits dedicated to minimization of the area of a final solution. In the technology mapping process, the method of a multioutput function was used in the graph of outputs form. This method is well known from previous papers and proposes optimization of a basic form of the graph of outputs to enable better use of the resources of a programmable structure. The possibilities for the graph of outputs were expanded in the form of sequential circuits. This work presents a new form of a graph that describes the process of mapping and is known as the graph of excitations and outputs. This graph enables effective technology mapping of sequential circuits. The paper presents a series of experiments that prove the efficiency of the proposed methods for technology mapping. Experiments were conducted for various sizes of PAL-based logic blocks and commercially available CPLDs. The presented results indicate the possibility of more effective implementation of the CPS physical layer.
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Han, Xiao Wei, Yi Zhen Sun, Xiao Xia Liu, and Chang Tong Li. "Design of Condenser Rubber Ball Cleaning Counting System Based on CPLD." Applied Mechanics and Materials 341-342 (July 2013): 684–89. http://dx.doi.org/10.4028/www.scientific.net/amm.341-342.684.

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The working condition of the condenser in power plant is an important factor that affects the economic operation of the power plant. Rubber ball cleaning is a main method to deal with the condenser fouling. The thesis, dealing with the problem of counting errors of rubber ball in the process of condenser cleaning, based on CPLD(Complex Programmable Logic Device) technology, designs a programme have rubber balls checking and counting automatically. The program takes use of the controlled laser sensors to count the number of rubber balls in every single pipe and the parallel processing capacity of CPLD,and have the number of different pipes counted and shown. Experiments have proved its constancy and accuracy.
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Son, Ki-Hwan, Jin-Ho Choi, Ki-Ryong Kwon, and Eung-Soo Kim. "Fabrication of Security System for Preventing an intruder Using a Complex Programmable Logic Device(CPLD)." Journal of Sensor Science and Technology 12, no. 1 (January 30, 2003): 44–50. http://dx.doi.org/10.5369/jsst.2003.12.1.044.

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Dissertations / Theses on the topic "Complex Programmable Logic Device (CPLD)"

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Cox, Corry. "IMPLEMENTING A TACTICAL TELEMETRY STYSTEM FOR MULTIPLE LAUNCH ROCKET SYSTEM (MLRS) STOCKPILE RELIABILITY TESTING." International Foundation for Telemetering, 2004. http://hdl.handle.net/10150/604935.

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International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, California
The Precision Fires Rocket and Missile Systems (PFRMS) Program Office continually undertakes Stockpile Reliability Testing (SRP) to ensure the validity of the accumulated weapons and increase the she lf life of these weapon systems. MLRS is a legacy weapon system that has been undergoing SRP testing for over 20 years. The PFRMS Program Office has a need for a miniature Tactical Telemetry System that will monitor the fuze performance of the MLRS Rocket during SRP testing. This paper will address a technical approach of how a small Tactical Telemetry System could be built to meet this requirement. The Tactical Telemetry system proposed in this paper will monitor fuze functions, operate across the wide environmental spectrum of the SRP tests, and physically fit in the nose area without altering the overall tactical rocket appearance or operation.
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Minhoni, Danilo Carlos Rossetto. "Detecção de movimento de objetos em tempo real utilizando dispositivos de lógica programável complexa." Universidade de São Paulo, 2006. http://www.teses.usp.br/teses/disponiveis/18/18133/tde-30112006-150543/.

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Um sistema que realiza a detecção de movimento procura, numa seqüência de imagens, sinais que confirmem a existência de movimentação no ambiente monitorado. Uma vez realizada a detecção do movimento, pode-se realizar o rastreamento (tracking) do objeto na cena em questão. A detecção e o rastreamento de objetos, em tempo real, são técnicas que estão despertando grande interesse por parte de pesquisadores e empresas pois, estas técnicas, podem ser utilizadas em diversas áreas que se estendem desde a engenharia e computação até áreas como a geologia e medicina. Sendo assim, seguindo-se a idéia básica de detecção e rastreamento, encontram-se diversas aplicações para estas técnicas como: sistemas de vigilância, análise de movimentos humanos, sistemas de detecção e rastreamento de pedestres ou veículos, dentre outras. Neste trabalho é mostrado um sistema que foi desenvolvido para armazenamento de imagens em tons de cinza de uma seqüência de vídeo e um posterior processamento dessas imagens para detecção de características que indiquem movimento. O processamento se resume em integrar o sinal de vídeo, que está armazenado nas memórias, nas direções horizontal e vertical gerando os histogramas de intensidade horizontal e vertical. Comparando os histogramas de quadros diferentes da seqüência de vídeo será possível detectar a presença de movimento e a região da imagem onde este ocorreu. Devido à necessidade de um processamento rápido das imagens e no interesse de produzir um sistema dedicado com hardware reduzido, utilizou-se de dispositivos de lógica programável complexa (CPLDs).
A system that performs movement detection in a sequence of images looks for signs that confirm the occurrence of the movement in the controlled environment. Once the movement of the object is detected it is possible to perform the tracking of the object. Real time object detection and tracking techniques are of great interests to researchers and industries because these techniques can be used in several areas going from engineering and computing to geology and medicine. There is a wide field of applications of detection and tracking techniques, such as: surveillance systems, human movement analysis, pedestrians or vehicle detection. This work presents an implementation able to store a gray level image from a video sequence and from these images detect in real time a object movement in the scene. The detection will be performed integrating an image from the video sequence in the horizontal and vertical directions in order to obtain the intensities histograms in these directions. Comparing the histograms with those of a different frame of the video sequence it will be possible to detect the presence of movement and locate where in the image the movement occurs. Due to real time digital image processing requirements and in order to produce a reduce dedicated hardware, complex programmable logic devices (CPLDs) were used.
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Kaděrka, Petr. "Systém pro zobrazování černobílých snímků v nepravých barvách (Pseudocolor)." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2008. http://www.nusl.cz/ntk/nusl-217184.

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This diploma thesis treats the possibilities of the black-white picture depiction in pseudo colors (Pseudocolor). The individual methods, software or hardware are described there and the detailed block scheme of the system Pseudocolor is suggested. The block scheme is created on the basis of gained theoretical knowledge. In the thesis, individual functional blocks of the scheme are described and their circuit designs are realized. Some of the functional blocks are simulated by the PSpice program and accompanied by corresponding signal process data. The suitable choice of the active and passive components is performed, from which the general integration of the system Pseudocolor is made. All the source materials for the realization of the device are given there – double-sided drawing of the printed circuit, layout and specification of the components.
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Cheng, Chieh-Yun, and 鄭傑允. "Complex Programmable Logic Device (CPLD) realizes Blind Guiding System." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/73785375122342532696.

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碩士
國立高雄海洋科技大學
微電子工程研究所
99
Currently the most widely used aids for the blind are the white cane. In order for visually impaired people to determine obstacles location, one needs to have directly contact with the object using cane. Without it, many accidents could happen. Another way is using the blind guide dog, but training process can be long and expensive, so it is not widely used in Taiwan at present. To mitigate the problem also with cost in mind, we proposed an electronic guide accessory combined with white cane in this work. In the thesis, we demonstrate a detection system aimed to detect obstacles in upper body space. This system consists of sensor and buzzer to locate obstacle and then produce a sound to alert the blind in time to avoid injures. This system can detect obstacles in relative long range (2 m) with reasonable accuracy. Results show that it is better than most of guide accessory on the market. System logic of this work consist of divider, counter, comparator, multiplexer and digital filters putting together by the Verilog Hardware Description Language and Complex Programmable Logic Device. The final size and weight of hardware (a MAX II CPLD, an ultrasonic sensor and a pair of headphones), is relatively small and light compared to most of products on the market.
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Lin, Yi-Ming, and 林宜民. "High-Performance Maximum Power Point Tracking of Photovoltaic Power Converter System Based on Complex Programmable Logic Device Control." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/52330170129065283062.

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碩士
國立雲林科技大學
電機工程系碩士班
92
The fully digital control of the shading of the maximum power point tracking (MPPT) for series connected photovoltaic (PV) modules have been proposed in this thesis. A PV inverter is designed to control the MPPT for PV system and synchronize a sinusoidal ac output voltage. The proposed system is composed of a full-bridge inverter, series connected PV modules, and a complex programmable logic device (CPLD) based controller. If part of PV module is prevented from receiving light, the shaded PV module cannot generate any electric power and even become a load, resulting in the power loss. The proposed control enables the individual PV module to operate effectively at the maximum power point (MPP). The MPPT control was achieved with a method combining the incremental conductance method and the perturbation and observation method. The CPLD was used to implement the feedback control, MPPT control and sinusoidal pulse-width modulation (SPWM) control for the system. Experimental results are given to confirm the proposed control scheme.
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Van, der Merwe Jacobus Stefanus. "The design of an electro-optic control interface for photonic packet switching applications with contention resolution capabilities." Diss., 2007. http://hdl.handle.net/2263/29241.

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The objective of the research is to design an electro-optic control for the Active Vertical Coupler-based Optical Cross-point Switch (OXS). The electronic control should be implemented on Printed Circuit Board (PCB) and therefore the design will include the PCB design as well. The aim of the electronic control board is to process the headers of the packets prior to entering the OXS to be switched and from the information in the headers, determine the state that the OXS should be configured in. It should then configure the optical cross-point accordingly. The electronic control board should show flexibility in the sense that it can handle different types of traffic and resolve possible contention that may occur. The research seeks to understand the problems associated with Photonic Packet Switching (PPS) networks. Two of the main problems identified in a PPS network are contention resolution and the lack of variable delays for storing optical packets. The OXS was analyzed and found to meet the requirements for future ultra-high speed PPS network technology with its high extinction ratio, wide optical bandwidth, ultra-fast switching speed and low crosstalk levels. Photonic packets were generated with 4-bit, 8-bit or 16-bit headers at a bit rate of 155 Mbit/s followed by a PRBS (Pseudo Random Bit Sequence) payload at 10 Gbit/s. Different scenarios were created with these types of packets and the electro-optic control and OXS were subjected to these scenarios with the aim of testing the flexibility of the electro-optic control to control the OXS. These scenarios include:
  • Fixed length packets arriving synchronously at one input of the OXS. Some packets are destined for output 1, some are destined for output 2 and some are destined for output 3, therefore realizing a 1-to-3 optical switch.
  • Eight variable length packets arriving synchronously at the OXS at one input, all of them destined for one output. The electro-optic control should open the switch cell for the correct amount of time.
  • Three variable length packets arriving synchronously and asynchronously at one input of the OXS. Some packets are destined for output 1 while other packets are destined for output 2. The electro-optic control should open the correct switch cell for the correct amount of time.
  • Two fixed length packets arriving at the OXS synchronously on different input ports at the same time, both destined for the same output port. The electro-optic control should detect the contention and switch the packets in such a way as to resolve the contention.
    • The electro-optic control and OXS managed to switch all these types of data traffic (scenarios) successfully and resolve the contention with an optical delay buffer. The success of the results was measured in two ways. Firstly it was deemed successful if the expected output sequence was measured at the corresponding output ports. Secondly it was successful if the degradation in quality of the packet was not drastic, meaning the output packets should have an BER (Bit Error Rate) of less than 10-9. The quality of the packets was measured in the form of eye diagrams before and after the switching and then compared. The research resulted in the design and implementation of a flexible electro-optic control for the OXS. The problem of contention was resolved for fixed length synchronous packets and a proposal is discussed to store packets for variable lengths of time by using the OXS. This electro-optic control has the potential to control the OXS for traffic with higher complexities and make the OXS compatible with future developments.
    Dissertation (MEng (Electronic Engineering))--University of Pretoria, 2008.
    Electrical, Electronic and Computer Engineering
    MEng
    unrestricted
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Books on the topic "Complex Programmable Logic Device (CPLD)"

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Parker, Philip M. The 2007-2012 World Outlook for Complex Programmable Logic Devices (CPLDs) and Field Programmable Gate Arrays (FPGAs). ICON Group International, Inc., 2006.

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Book chapters on the topic "Complex Programmable Logic Device (CPLD)"

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", "Complex Programmable Logic Devices (CPLDs)"." In Designing with FPGAs and CPLDs, 190. CRC Press, 2002. http://dx.doi.org/10.1201/9780080494456-16.

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"Complex Programmable Logic Devices (CPLDs}." In Designing with FPGAs and CPLDs, 33–48. CRC Press, 2002. http://dx.doi.org/10.1201/9780080494456-8.

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Mahmoud, Imbaby I. "Implementation of Reactor Control Rod Position Sensing/Display Using a VLSI Chip." In Field-Programmable Gate Array (FPGA) Technologies for High Performance Instrumentation, 1–16. IGI Global, 2016. http://dx.doi.org/10.4018/978-1-5225-0299-9.ch001.

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The chapter describes the use of CPLDs and FPGAs devices in Nuclear Power Plant (NPP) Instruments. The design, simulation, implementation and test of a reactor control rod position sensing electronic unit intended as a replacement of the outdated Russian type in old power reactors is presented. The signals are generated from12 ring-shaped pair of inductively coupled coils surrounding the reactor moving rod. The implementation involves both analog and digital design. The designed digital circuit has 12 TTL outputs working in a 1-out-of-12 mode, excluding both double [2-out-of-12] and no-output state. To avoid a flickering display during transition between two neighboring positions, some sort of hysteresis is implemented. One time this hysteresis is implemented through a state machine deriving up/down counter. The state machine is synthesized targeting a Xilinx Spartan XL device. To reduce the possibility of power failure effects, another circuit consists of combinatorial logic and implemented in CPLD is presented. However, energy harvesting methods in NPPs can support counter based design.
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Véstias, Mário Pereira. "Field-Programmable Gate Array." In Encyclopedia of Information Science and Technology, Fifth Edition, 257–70. IGI Global, 2021. http://dx.doi.org/10.4018/978-1-7998-3479-3.ch020.

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Field-programmable gate arrays (FPGAs) are integrated circuits whose logic and their interconnections are configurable. These devices are field-programmable, that is, they can be configured by the hardware designer without any intervention of the manufacturer. Most FPGAs can be reprogrammed as many times as we want with a vast variety of digital circuits. Some recent FPGA families are system-on-chips (SoC) with one or more microprocessor cores, memory, cache, and reconfigurable logic allowing the implementation of complex hardware/software systems in a single programmable device. This article focuses on the architecture of FPGAs, including the so called SoC FPGA. It explains the main blocks of the FPGA, how they have evolved along the last decades and the perspectives of next generation FPGAs. It also describes some applicability areas and how its architecture have evolved to adapt to some of these target markets.
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Conference papers on the topic "Complex Programmable Logic Device (CPLD)"

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Yuguo, Sun, and Chen Jin. "Embedded Fault Tree Logic Implementation Based on Complex Programmable Logic Device." In ASME 2005 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. ASMEDC, 2005. http://dx.doi.org/10.1115/detc2005-84886.

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To meet the requirements of an embedded mechanical fault diagnosis system development, a fault tree implementation and dynamic modification method based on CPLD (Complex Programmable Logic Device) is investigated experimentally. The mechanism of fault tree logic calculation in the CPLD chip is presented. The fault logic tree is modeled by VHDL (VHSIC Hardware Description Language) and logic graphic, respectively. The effects of the bottom events on the logic result are simulated in Max + plus II platform. The fault tree logic is downloaded into the EPM7064SLC44-10 chip by ISP (In System Programmable) technology. And evaluated in terms of power consumption, system’s volume and design flexibility. The study results show that CPLD is suit to the fault tree’s construction, contributed by the chip’s outstanding ISP function and programmable logic function. And the fault tree logic synthesis and the chip resource optimization need to be further investigated.
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Zhao, Fan, Delu Chen, Zhe Pu, and Jielu Wang. "A New Research Method for Corrosion Defect in Metal Pipeline by Using Pulsed Eddy Current." In ASME 2020 Pressure Vessels & Piping Conference. American Society of Mechanical Engineers, 2020. http://dx.doi.org/10.1115/pvp2020-21322.

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Abstract Pulsed eddy current (PEC) is a new technique to distinguish corrosion defeats inside and outside the metal pipeline. In comparison with other eddy current techniques, the PEC technique has the advantage of being simple and high velocity. In this article, a brand-new PEC probe based on differential conductivity is established through the combination of modules like square wave generator, eddy current coil bridge, differential current, voltage sample circuits and so on. The 50% duty cycle square wave is used as the driving signal. To measure differential conductance, a coil bridge configuration with two legs is adopted. One leg is composed of measurement eddy current coil and the in-series resistor, and the other is reference eddy current coil and the in-series resistor. Because the two legs go through defects in pipeline non-synchronously, there is a differential conductance between the two coils. A trans-impedance amplify circuit is used to detect coil eddy current. At the same time, two amplifiers are used to measure the differential voltage between the two coils. A 14 bit ADC is used to sample differential voltage, measurement and reference eddy currents which transferred to differential current by main processor Complex Programmable Logic Device (CPLD). CPLD is used to get differential conductance by differential current divide differential voltage. At last the eddy current signal sampling sequence is developed. A dynamic testing fixture with artificial defects carved on the pipeline is used to validate PEC probe’s accuracy. The differential conductance signals were displayed on the oscilloscope. Results showed that the inside defect had two peaks, positive peak and negative peak, but the outside defect only had one positive peak. We can conclude that the brand-new PEC probe has high accuracy in distinguishing the inside and outside defects.
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Lohrke, Heiko, Philipp Scholz, Christian Boit, Shahin Tajik, and Jean-Pierre Seifert. "Automated Detection of Fault Sensitive Locations for Reconfiguration Attacks on Programmable Logic." In ISTFA 2016. ASM International, 2016. http://dx.doi.org/10.31399/asm.cp.istfa2016p0336.

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Abstract Programmable logics, such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs), are widely used in security applications. In these applications cryptographic ciphers, physically unclonable functions (PUFs) and other security primitives are implemented on such platforms. These security primitives can be the target of fault injection attacks. One of the most powerful examples of fault injection techniques is laser fault injection (LFI), which can induce permanent or transient faults into the configuration memories of programmable logic. However, localization of fault sensitive locations on the chip requires reverse-engineering of the utilized building blocks, and therefore, is a tedious task. In this work, we propose an automated technique using readily available IC debug tools to map and profile the fault sensitive locations of programmable logic devices in a short period.
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Vuza, Dan Tudor, and Marian Vladescu. "Solving an EMC/EMI problem occurred inside a complex programmable logic device." In 2014 37th ISSE International Spring Seminar in Electronics Technology (ISSE). IEEE, 2014. http://dx.doi.org/10.1109/isse.2014.6887631.

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Bui, Van Thu, Thi Hieu Nguyen, and Minh Duc Le. "ON A NEW DIGITAL ELECTROTHERAPY EQUIPMENT WITH MICROCONTROLLERS AND COMPLEX PROGRAMMABLE LOGIC DEVICE." In 40th International Academic Conference, Stockholm. International Institute of Social and Economic Sciences, 2018. http://dx.doi.org/10.20472/iac.2018.040.008.

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Wang, Xiao, and Baiyang Cao. "Design of 8-Bit Serial Real-Time Decoder Based on Complex Programmable Logic Device." In 2009 2nd International Congress on Image and Signal Processing (CISP). IEEE, 2009. http://dx.doi.org/10.1109/cisp.2009.5305212.

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Gu, Zhenpu, and Yingjun Guo. "Fluorescence detection system for hydrocarbon based on charge-coupled devices and complex programmable logic device." In 5th International Symposium on Advanced Optical Manufacturing and Testing Technologies, edited by Yudong Zhang, José Sasián, Libin Xiang, and Sandy To. SPIE, 2010. http://dx.doi.org/10.1117/12.866318.

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Benkhalil, A. K., S. S. Sipson, and W. Booth. "Real-time detection and tracking of a moving object using a complex programmable logic device." In IEE Colloquium on Target Tracking and Data Fusion. IEE, 1998. http://dx.doi.org/10.1049/ic:19980428.

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Bai, Haonan, Lan Yin Lee, Yang Jing, Peter Floyd Salinas, and Kok Keng Chua. "Zynq SOC Low-Voltage and Temperature-Dependent L2 Cache Failure Diagnosis and Defect Localization Case Study." In ISTFA 2017. ASM International, 2017. http://dx.doi.org/10.31399/asm.cp.istfa2017p0322.

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Abstract:
Abstract Failure analysis and defect localization on 28nm All Programmable Zynq System-on-Chip (SoC) device is extremely challenging. While conventional FPGA, which only consists of the Programmable Logic, has greater ease and flexibility in pattern generation during fault isolation, the all programmable SoC device integrates a dual ARM Cortex-A9 cores with Programmable Logic (PL) in a single chip. The cache data access in-between processor and PL is more complex and test methodology has lesser degree of control on cache data flow and stack sequence. This paper introduced an advanced fault isolation test methodology combining Software Development Kit (SDK) with scan based diagnostic test for cache failures. It successfully pinpoint to failure locations with physical defects found. As conventional physical failure analysis approaches using SEM based passive voltage contrast could not observe any abnormalities, current imaging and nano-probing measurement using AFP played critical roles in detecting nano-ampere leakages prior subsequent TEM analysis. The findings were then feedback to the foundry for process improvement. Furthermore, a new screening methodology is innovated where an extreme low-voltage test at high temperature in Automatic Test to detect and eliminate the process marginal leakage failure.
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Jingyao, Huang, Yang Jing, and Peter Floyd Salinas. "Successfully Look Up Table Distribution RAM Control Circuitry Fault Isolation with Different Test Methodologies and Conflict Results Analysis by Using Virtual IO and Integrated Logic Analyzer Debug Tools." In ISTFA 2018. ASM International, 2018. http://dx.doi.org/10.31399/asm.cp.istfa2018p0467.

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Abstract This electrical fault isolation based on Xilinx 28nm all programmable device in a Distribution RAM (LUTRAM) functional block. The Look-Up-Table (LUT) was the major component to achieve the programmable chip versus the ASIC chip. In the device architecture, one 6-inputs-LUT (LUT6) memory can be configured as a 64bits distribution RAM (LUTRAM64) or two 32bits distribution RAMs (LUTRAM32). The Vivado design and debug tool brought up two powerful Intellectual Property (IP) Cores: Virtual Input/Output (VIO) and Integrated Logic Analyzer (ILA). This debug tool used Block RAM (BRAM) and fabric routing resources to store the full test results and achieved package level probe-less. [1] It can probe LUTRAM block input, output and Build-In Self-Test (BIST) interconnects. However the limitation was that the inner primitive functional block LUTRAM like memory cells, decoders, mode switchers, write/read controllers and so on were not able to probe. In this case study, the defect was not conventional failure inside the LUTRAM memory cell or stuck on Address/Data_in inputs. Moreover the test behavior with LUTRAM64 mode had conflicting results, which made the fault isolation even more challenge to narrow down from complex LUTRAM control circuitry to transistor level. Therefore different pattern test methodologies, pattern commonality analysis and hypothesis verification were wisely compiled together. In the end, the defect was successfully localized at the fault Isolation circuitry. It was fully matching with the failing mode and proving the fault isolation was correct. The physical defect analysis shown multiple layers metal fusing. The defect shorted the internal control output with the GND signal, which forced LUTRAM to setup as an invalid mode.
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You might also be interested in the extended bibliographies on the topic 'Complex Programmable Logic Device (CPLD)' for particular source types:
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