Journal articles: 'Complex Programmable Logic Device (CPLD)'

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Liu, Cheng, Zhe Li, and Jia Jia Hou. "Simulation and Application of PLD in Electric Power System Circuit." Applied Mechanics and Materials 241-244 (December 2012): 1931–35. http://dx.doi.org/10.4028/www.scientific.net/amm.241-244.1931.

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Programmable Logic Device(PLD) has been widely used in hardware circuit, and it has evolved into two types: Complex Programmable Logic Device(CPLD) and Field Programmable Gate Array(FPGA). This paper takes small current grounding in electric power system as background, uses xc95144, a representative CPLD of Xilinx Company in the signal collecting circuit to collect voltage and current signals, and do some other operations to spare circuit board area. This paper also tries to translate the schematic into VHDL-described text and do simulation to the text.

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Zhang, Shi Jun, and Zi Yang Xu. "Research of Automobile Driving Simulator Control System." Applied Mechanics and Materials 575 (June 2014): 771–74. http://dx.doi.org/10.4028/www.scientific.net/amm.575.771.

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This paper introduce a control system of automobile driving simulator, Using the CPLD (Complex Programmable Logic Device) technology can easily achieve detect the states of ignition equipment, steering equipment, clutch equipment, foot-brake equipment, hand-brake equipment, accelerator equipment, shift equipment etc and drive the instrumentation.

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Gołofit, Krzysztof, and Piotr Wieczorek. "Chaos-Based Physical Unclonable Functions." Applied Sciences 9, no. 5 (March 9, 2019): 991. http://dx.doi.org/10.3390/app9050991.

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The concept presented in this paper fits into the current trend of highly secured hardware authentication designs utilizing Physically Unclonable Functions (PUFs) or Physical Obfuscated Keys (POKs). We propose an idea that the PUF cryptographic keys can be derived from a chaotic circuit. We point out that the chaos theory should be explored for the sake of PUFs as a natural mechanism of amplifying random process variations of digital circuits. We prove the idea based on a novel design of a chaotic circuit, which utilizes time in a feedback loop as an analog continuous variable in a purely digital system. Our design is small and simple, and therefore feasible to implement in inexpensive reprogrammable devices (not equipped with digital clock manager, programmable delay line, phase locked loop, RAM/ROM memory, etc.). Preliminary tests proved that the chaotic circuit PUFs work in both advanced Field-Programmable Gate Arrays (FPGAs) as well as simple Complex Programmable Logic Devices (CPLDs). We showed that different PUF challenges (slightly different implementations based on variations in elements placement and/or routing) have provided significantly different keys generated within one CPLD/FPGA device. On the other hand, the same PUF challenges used in a different CPLD/FPGA instance (programmed with precisely the same bit-stream resulting in exactly the same placement and routing) have enhanced differences between devices resulting in different cryptographic keys.

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Cheng, Le Feng, Lin Fei Yin, Bin Zhou, Jing Jiang, and Tao Yu. "Development of New Multi-Function Power Quality On-Line Monitoring Device." Advanced Materials Research 971-973 (June 2014): 928–33. http://dx.doi.org/10.4028/www.scientific.net/amr.971-973.928.

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A power quality on-line monitoring device based on two CPUS is designed and implemented in this paper, which separated the data analysis from the peripheral control completely, used CPLD (Complex Programmable Logic Device) to generate control timing of peripheral devices, made full use of the DSP, so as to meet the requirements of power quality: monitoring precision and real time. The paper firstly introduces the monitor's sampling circuit, communication module circuit, storage module circuit and the flow chart of software. Then, the functions, features and designations of each module are described in detail.

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Kania, Dariusz. "Logic Decomposition for PAL-Based CPLDs." Journal of Circuits, Systems and Computers 24, no. 03 (February 10, 2015): 1550042. http://dx.doi.org/10.1142/s0218126615500425.

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The Programmable Array Logic (PAL)-based logic block is the core of the great majority of Complex Programmable Logic Devices (CPLDs). The purpose of this paper is to compare two models of decomposition dedicated to PAL-based devices. Non-standard usage of decomposition, which leads to the reduction of used PAL-based logic blocks in a programmable structure, is the aim of the presented methods. Each decomposition step is optimized for implementation in a PAL-based structure that is characterized by a PAL-based logic block. The essence of decomposition models is oriented towards minimizing the number of PAL-based logic blocks used and adjusting the designed circuit to fit the structures of PAL-based blocks best. In the experimental section, a comparison of two decomposition models with the classical implementation approach is presented. Results of the experiments prove that the proposed methods lead to a significant reduction of chip area in relation to the classical approach, especially if CPLD structures consist of PAL-based blocks containing a relatively small number of product terms.

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Liu, Li, and Qing Hong Wu. "Image Acquisition Method Based on TMS320DM642." Applied Mechanics and Materials 397-400 (September 2013): 2196–99. http://dx.doi.org/10.4028/www.scientific.net/amm.397-400.2196.

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A method of the image acquisition based on digital signal processor (DSP) is introduced. DSP, complex programmable logic device (CPLD) and contact image sensor (CIS) are combined in the hardware design, and the time-sequence analysis of the image acquisition process is also presented. Practical application indicates that this method has high accuracy and is rapid enough to satisfy the requirement of real-time acquisition.

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He, Yun Chao, Ming Deng, Qi Sheng Zhang, and Xin Jin. "The LED Dot Matrix Control Technology Based on 51 MCU and CPLD." Applied Mechanics and Materials 738-739 (March 2015): 1275–79. http://dx.doi.org/10.4028/www.scientific.net/amm.738-739.1275.

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This paper describes a kind of LED dot matrix control technology based on STC89C51 MCU and complex programmable logic device CPLD, highlighting LED dot matrix display principle and the hardware and software implementation. This design has a flexible and programmable features, to ensure the stability of the system under the premise to achieve a variety of control programs on the LED dot matrix. According to this program,the breadboard adds external data memory, which can be used to extend the external bus, and this design has been successfully used MCU experiment.

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Kubica, Marcin, and Dariusz Kania. "Graph of Outputs in the Process of Synthesis Directed at CPLDs." Mathematics 7, no. 12 (December 3, 2019): 1171. http://dx.doi.org/10.3390/math7121171.

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The paper focuses on the methodology of designing a cyber physical systems (CPS) physical layer using programmable devices. The CPS physical layer can be implemented in programmable devices, which leads to a reduction in their costs and increases their versatility. One of the groups of programmable devices are complex programmable logic devices (CPLDs), which are great for energy-saving, low-cost implementations but requiring flexibility. It becomes necessary to develop mathematical CPS design methods focused on CPLD. This paper presents an original technology mapping method for digital circuits in programmable array logic (PAL)-based CPLDs. The idea is associated with the process of multilevel optimization of circuits dedicated to minimization of the area of a final solution. In the technology mapping process, the method of a multioutput function was used in the graph of outputs form. This method is well known from previous papers and proposes optimization of a basic form of the graph of outputs to enable better use of the resources of a programmable structure. The possibilities for the graph of outputs were expanded in the form of sequential circuits. This work presents a new form of a graph that describes the process of mapping and is known as the graph of excitations and outputs. This graph enables effective technology mapping of sequential circuits. The paper presents a series of experiments that prove the efficiency of the proposed methods for technology mapping. Experiments were conducted for various sizes of PAL-based logic blocks and commercially available CPLDs. The presented results indicate the possibility of more effective implementation of the CPS physical layer.

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Han, Xiao Wei, Yi Zhen Sun, Xiao Xia Liu, and Chang Tong Li. "Design of Condenser Rubber Ball Cleaning Counting System Based on CPLD." Applied Mechanics and Materials 341-342 (July 2013): 684–89. http://dx.doi.org/10.4028/www.scientific.net/amm.341-342.684.

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The working condition of the condenser in power plant is an important factor that affects the economic operation of the power plant. Rubber ball cleaning is a main method to deal with the condenser fouling. The thesis, dealing with the problem of counting errors of rubber ball in the process of condenser cleaning, based on CPLD(Complex Programmable Logic Device) technology, designs a programme have rubber balls checking and counting automatically. The program takes use of the controlled laser sensors to count the number of rubber balls in every single pipe and the parallel processing capacity of CPLD,and have the number of different pipes counted and shown. Experiments have proved its constancy and accuracy.

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Son, Ki-Hwan, Jin-Ho Choi, Ki-Ryong Kwon, and Eung-Soo Kim. "Fabrication of Security System for Preventing an intruder Using a Complex Programmable Logic Device(CPLD)." Journal of Sensor Science and Technology 12, no. 1 (January 30, 2003): 44–50. http://dx.doi.org/10.5369/jsst.2003.12.1.044.

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He, Xing Zheng, Jing Lan Ma, and Wei Wang. "A Grating Generator for 3D Scanner Using CPLD." Applied Mechanics and Materials 462-463 (November 2013): 89–92. http://dx.doi.org/10.4028/www.scientific.net/amm.462-463.89.

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In the three-dimensional scanners (3D scanners), the grating generator is a key hardware. The commercial video projector is always used to act as the electronic grating generator normally. But there are some defects existed. Such as, the size is too large to setup in the case, it is not easy to be controlled by a single chip microcomputer, etc. To solve these problems, in this paper, a new type of grating generator was designed. A complex programmable logic device (CPLD) chip is used to control a liquid crystal on silicon (LCOS) video chip directly, and it works well.

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Zang, Chuan Qiang, Ming Yu Gao, Yun Fei Liu, and Zhi Wei He. "Study of Subdivision Stepping Motor Driver Based on the Controllable Dead-Time Compensation." Applied Mechanics and Materials 556-562 (May 2014): 1294–97. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.1294.

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In order to improve the step accuracy of two-phase hybrid stepping motors, this paper presents a high-performance stepping motor driver based on controllable dead-time compensation. After CPLD(Complex Programmable Logic Device) logical processing, the subdivision drive signal created by microcontroller STM32 becomes a complementary dead-time compensation drive signal which can realize precise control of stepper motor. The experiment shows that this program not only has effectively reduced the power consumption of the stepping motor, but also made whole system cost less.

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Liang, Jie, Rong Jiang Tang, Yin Han Gao, Tong Hang Zhao, Wen Jun Jiang, and Bing Wu Lu. "Identification Method of Vehicle Interior Airborne Noise Based on Pseudo-Random." Advanced Materials Research 338 (September 2011): 460–66. http://dx.doi.org/10.4028/www.scientific.net/amr.338.460.

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According to the source-path-receiver model of vehicle interior airborne noise, the correlative identification method of transfer function was proposed. Simulation results demonstrate that the method has excellent noise immunity performance. A m sequence generator whose shift clock frequency is adjustable and register series is optional was designed by complex programmable logic device CPLD and external circuit. The m sequence pseudo-random signal which was amplified by audio power amplifier drives the loudspeaker as sound source signal. The field tests indicate that compare with broadband white noise sweep method, the identification method based on m sequence technique has advantages in noise suppression.

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Guo, Zhi Jun, and Huan Mei Yan. "Design and Implementation of Digital Signal Generator Based on LPC2132." Applied Mechanics and Materials 303-306 (February 2013): 1869–72. http://dx.doi.org/10.4028/www.scientific.net/amm.303-306.1869.

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A design method of the digital signal generator, based on LPC2132 as the master control chip, is introduced in this paper. The system has used of a chip of the direct digital frequency synthesizer (DDS) and a complex programmable logic device(CPLD) to produce the sine wave, square wave and triangle wave, and has designed circuits of analog signal amplification and gain control. Realized the switch of different signal through the keyboard, it is a new kind of the digital signal source, which has performances including stabilizing waveform, higher precision, adjustable amplitude and frequency on the permitted scope.

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Li, Jianghao, Zhenbo Li, and Jiapin Chen. "A microstep control approach for a millimeter-sized omni-directional mobile microrobot actuated by 3-mm-electromagnetic micromotors." Robotica 27, no. 6 (October 30, 2008): 813–24. http://dx.doi.org/10.1017/s0263574708005158.

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SUMMARYThis paper presents a novel microstep control approach for improving the positioning precision of a millimeter-sized omni-directional mobile microrobot. The microrobot that is designed for microassembly in a microfactory is driven by three electromagnetic micromotors. The structures of both the microrobot and the micromotor are described in the paper. The torque vectors synthesis method (TVSM) is developed and the torque self-balance principle (TSBP) is employed to realize the microstep control. The control circuit that needs a complex digital logic is devised with a complex programmable logic device (CPLD). The experiments using a hard disk and the real microrobot demonstrated the validity and performance of TVSM and TSBP. And the angular step precision of the microrobot is increased by three times compared to the normal control.

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Abu, Mohd Azlan, Harlisya Harun, Mohammad Yazdi Harmin, Noor Izzri Abdul Wahab, and Muhd Khairulzaman Abdul Kadir. "The design of Viterbi decoder for low power consumption space time trellis code without adder architecture using RTL model." World Journal of Engineering 13, no. 6 (December 5, 2016): 540–46. http://dx.doi.org/10.1108/wje-09-2016-0088.

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Purpose This paper aims to describe the real-time design and implementation of a Space Time Trellis Code decoder using Altera Complex Programmable Logic Devices (CPLD). Design/methodology/approach The code uses a generator matrix designed for four-state space time trellis code (STTC) that uses quadrature phase shift keying (QPSK) modulation scheme. The decoding process has been carried out using maximum likelihood sequences estimation through the Viterbi algorithm. Findings The results showed that the STTC decoder can successfully decipher the encoded symbols from the STTC encoder and can fully recover the original data. The data rate of the decoder is 50 Mbps. Originality/value It has been shown that 96 per cent improvement of the total logic elements in Max V CPLD is used compared to the previous literature review.

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Wu, Liang, Yong Yang, and Zhong Kui Zhu. "A New Technology of Pulse by Pulse for NPC Three-Level Inverters." Advanced Materials Research 765-767 (September 2013): 2489–93. http://dx.doi.org/10.4028/www.scientific.net/amr.765-767.2489.

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When Neutral Point Clamped (NPC) three-level photovoltaic grid-connected inverter is overloaded or in short state, the control by software could not judge immediately, but the power switch components of the inverter would be broken. The technology of Pulse by Pulse is an important method to protect the power switch components. This paper studies the principle of traditional technology of Pulse by Pulse, then analyzes a new technology of Pulse by Pulse based on Complex Programmable Logic Device (CPLD), finally a 3KW NPC three-level grid-connected inverter is set up with the new technology of Pulse by Pulse and the feasibility is demonstrated through the experiments.

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Zhou, Jing Hua, Peng Zeng, and Xiao Wei Zhang. "Full Power Experiment Method of Single-Phase PWM Back-to-Back Converter." Applied Mechanics and Materials 577 (July 2014): 488–93. http://dx.doi.org/10.4028/www.scientific.net/amm.577.488.

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Based on the single-phase H-H power unit topology in the novel co-phase power supply system, with the back-to-back grid-connected operation method, this paper aimed at solving the problem that in experiment, system capacity constraints caused the failure to achieve unit full power output and proposed the strategy of rectifier voltage, current double closed loop and full disturbance feed-forward control. Finally, based on the digital signal processor (DSP) and complex programmable logic device (CPLD), this study constructed a hardware platform of the power unit control system. Experimental results show that the system is stable, achieving two-way flow of energy.

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BARKALOV, ALEXANDER, LARYSA TITARENKO, and SŁAWOMIR CHMIELEWSKI. "HARDWARE REDUCTION IN CPLD-BASED MOORE FSM." Journal of Circuits, Systems and Computers 23, no. 06 (May 14, 2014): 1450086. http://dx.doi.org/10.1142/s0218126614500868.

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A new two-stage method of finite state machines (FSMs) synthesis for PAL-based complex programmable logic devices (CPLD) is proposed. It is based on both the wide fan-in of PAL cells and existence of the classes of pseudoequivalent states of Moore FSM. The first step targets decreasing for the number of PAL cells used for implementing the block of input memory functions. The second step targets decreasing for the number of PAL cells in the block of microoperations. An example of application of the proposed method is given, as well as results of experiments carried out for standard benchmarks.

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Merchan-Villalba, Luis Ramon, Jose Merced Lozano-Garcia, Diego Armando de Jesus Gutierrez-Torres, Juan Gabriel Avina-Cervantes, and Alejandro Pizano-Martinez. "Four-Step Current Commutation Strategy for a Matrix Converter Based on Enhanced-PWM MCU Peripherals." Electronics 8, no. 5 (May 15, 2019): 547. http://dx.doi.org/10.3390/electronics8050547.

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In this paper, an efficient implementation of the four-step current commutation technique for controlling bidirectional power switches in a Matrix Converter (MC) is proposed. This strategy is based on the enhanced pulse width modulation peripheral included in the C 2000 Delfino 32-bit microcontroller of Texas Instruments. By tuning the algorithmic parameters contained in this module, the four-step commutation process is carried out on the Microcontroller Unit (MCU) without overloading the full complex processor and avoiding the use of additional special hardware such as Field-Programmable Gate Arrays (FPGA) or Complex Programmable Logic Devices (CPLD) when controlling the MC. The algorithm is implemented on the TMS320F28379D MCU and operationally validated on an MC prototype, where the functionality of the proposal is demonstrated.

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Moctezuma Gutiérrez, Sebastián Gael, Arturo Cruz Pazarán, Rubén Galicia Mejía, and Luz Noé Oliva Moreno. "Desarrollo de plataforma para implementación de robots colaborativos." Visión electrónica 12, no. 1 (May 30, 2018): 22–31. http://dx.doi.org/10.14483/22484728.13308.

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Los robots colaborativos son de interés en variadas áreas de control, especialmente en la manipulación, desarrollo y precisión de tareas programadas; parte de su funcionalidad radica, entonces, en la plataforma de comunicación entre ellos. En este artículo de investigación se presenta el desarrollo de una plataforma para la comunicación entre robots colaborativos empleando dispositivos lógicos programables CPLD (Complex Programmable Logic Device), sensores ultrasónicos y sensores infrarrojos con la finalidad de que realicen múltiples tareas. Según la forma en que sean programadas, estas plataformas robóticas pueden apoyarlas empresas a enfrentar dificultades tales como los altos costos derivados de otras plataformas robóticas convencionales; asimismo, pueden orientarse a facilitar tareas cotidianas —como la transportación de objetos o el apoyo en labores domésticas—que se pueden automatizar de manera eficaz.

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PERKOWSKI, MAREK A., MALGORZATA CHRZANOWSKA-JESKE, EDMUND PIERZCHALA, and ALAN COPPOLA. "AN EXACT SOLUTION TO THE FITTING PROBLEM IN THE APPLICATION SPECIFIC STATE MACHINE DEVICE." Journal of Circuits, Systems and Computers 04, no. 02 (June 1994): 173–90. http://dx.doi.org/10.1142/s0218126694000119.

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In this paper the fitting problem for a new Application Specific State Machine Device, CY7C361, from Cypress Semiconductor is formulated and the solution is proposed. This fitting problem consists of mapping a netlist obtained from high-level synthesis into the chip’s physical resources. In general, a mapping (fitting) problem can be formulated as one of the labeled graph isomorphism between the netlist graph and the subgraph of the resources graph. However, the specific architecture-related constraints of the CY7C361 device cause the fitting problem to be generalized as a graph isomorphism problem with some additional mapping constraints and node multiplication (placing some nodes of the netlist graph in more than one node of the physical graph). Such formulation is quite general for a class of Complex Programmable Logic Device (CPLD) fitting problems, and has not been found in the literature. We implemented an exact, constraint-based, tree searching algorithm with several kinds of backtracking.

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Zhang, Hui, Dan Ren, and Li Ming Du. "A New Improved Data Acquisition System for Electrical Capacitance Tomography." Advanced Materials Research 756-759 (September 2013): 1527–31. http://dx.doi.org/10.4028/www.scientific.net/amr.756-759.1527.

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To improve the precision and speed of the system, a new 16-electrode electrical capacitance tomography (ECT) system based on DSP was designed. The measure system adopts 16 electrodes combined and floating capacitance sensor array, and with the phase located loop circuit to eliminate ECT systems additional phase error. The digital signal processor (DSP) is the core of data acquisition system, the computing and control unit includes a DSP (TMS320C5416) and a complex programmable logic device (CPLD). The communication module of the designed system is developed based on HPI parallel transmission technology, which can implement high-speed communication between ECT system and PC. Simulation results show that the sensitivity distribution was more uniform and the reconstructed images for objects were improved obviously by using 16-combined and floating electrodes sensor.

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Park, Yun-Hwi, Kwangje Oh, Ikseop Kim, Hosung Chu, Jehong Sung, Seokchul Yun, and Jinwaun Kim. "Suppression of SSN by Embedded Decoupling Capacitor in LTCC Package." Journal of Microelectronics and Electronic Packaging 4, no. 2 (April 1, 2007): 57–63. http://dx.doi.org/10.4071/1551-4897-4.2.57.

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In this paper, the authors present the noise suppression performance using a decoupling capacitor which is embedded in an LTCC substrate. To embed high value capacitors (>20nF), a high K (over 500) material which can be co-fired with low K LTCC was developed successfully. Thin high K sheets under 10μm were co-laminated between low K sheets, which form the power and ground planes. Due to the short distance from the IC power pin to the decoupling capacitor, the ESL (Equivalent Series Inductance) is much lower than with surface mounted type capacitors, and so, SSN (Simultaneous Switching Noise) can be reduced significantly. To verify the noise suppression performance, we designed and fabricated a digital module using 100MHz CPLD (Complex Programmable Logic Device) on top of the LTCC substrate in which a 25nF decoupling capacitor was embedded. By measurement, we can see that SSN of CPLD on LTCC was reduced by 80% compared with designs that use surface mounted type 100nF capacitors. This embedded decoupling capacitor in LTCC (LEDC) can be useful for digital SiP (System In Package) to enhance noise performance and to reduce its footprint.

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Li, Jian Hua, Pin Rong Lin, Fu Sheng Shi, and Cai Jun Zheng. "Study on Magnetic Induced Polarization Technology and Instruments." Applied Mechanics and Materials 336-338 (July 2013): 100–105. http://dx.doi.org/10.4028/www.scientific.net/amm.336-338.100.

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In order to solve the difficult-ground areas of electromagnetic prospecting, we study magnetic induced polarization technology and instruments. Adopting the techniques such as GPS synchronization, CPLD(Complex Programmable Logic Device), digital PWM(Pulse-Width Modulation) constant current, VHDL(Very high speed integrated circuit Hardware Description Language) programming, a magnetic induced polarization instruments have been developed, which include transmitter, receiver, and three components magnetic field compensator. Instruments have functions such as high-power constant-current supplying, frequency-selective anti-interference receiving, GPS high-precision synchronizing, and amplitude-frequency response of magnetic sensor is flat. Using gradient configuration to obser the original data include magnetic field strength, magnetic polarization rate, phase, and get the magnetometric resistivity, the percent frequency efficiency by the further processing. For magnetic induced polarization instruments, we develop performance testing and the field experiments.

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Gao, Ji, Xiao Fang Ma, and Qing Yang Liu. "Software Design of Pulse Generator Based on Single-Chip Computer and CPLD." Applied Mechanics and Materials 201-202 (October 2012): 218–21. http://dx.doi.org/10.4028/www.scientific.net/amm.201-202.218.

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The purpose of this article is to study and devise pulse signal source of electrical discharge machining(EDM). The technology of EDM is the necessary key technology in various processing methods. Electrical discharge machining pulse power aims to convert the industrial frequency alternating current into certain frequencies pulse current to supply energy for electrode discharging to removal metal. Pulse power generator, controlled by an embedded MCU, can produce high voltage or low voltage discharge pulse waveform. After the research on characteristics and principles of many pulse powers, a novel, intelligent, high frequency pulse power supply with adjustable amplitude, frequency and duty is developed which has a favorable foreground in engineering application and a great theoretical significance. This paper is to realize the design of EDM pulse signal source based on the method of combining single-chip computer and complex programmable logic devices (CPLD), to satisfy the technical requirement of periodic variable and machining efficiency improving.

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Li, Huan Liang, Xiao Qiang Yang, Jin Hua Han, and Dan Wang. "Fault Test Equipment of Launcher Control System Based on Embedded System." Applied Mechanics and Materials 415 (September 2013): 216–19. http://dx.doi.org/10.4028/www.scientific.net/amm.415.216.

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The fault test equipment of mine launcher system is developed. This equipment is divided into two functional parts: master controller, an industrial processing computer and corresponding application software, which mainly engages in human-machine interactions, controlling the testing process, diagnosing the fault as well as display the output, and slave controller that performs data acquisition, signal conditioning, connection and transformation. Its hardware is composed of main control circuit with two complex programmable logic device (CPLD) chips, signal conditioning circuit, serial interface module and dedicated interface adapter unit. In addition, the application software of master controller is modular and object-oriented and developed by LabWIEW. The slave controller software is developed in VHDL that performs sampling and configuration of firing control and configuration signals. And the software consists of the five key modules: baud rate generator, enable module, pulse signal count module, data acquisition module of high level signals and communication module. Thus the equipment actually provides effective technical method in improving the repair and support skills for the mine launcher control system.

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Selokar, Pradip Ram, and P. T. Karule. "Security Enhancement in Networked Embedded System." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 4 (August 1, 2017): 1867. http://dx.doi.org/10.11591/ijece.v7i4.pp1867-1873.

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<span>In the developed system ARM9 is a master and Two ARM7s are slaves. The peripherals are being controlled by two ARM7 boards. The Peripherals are connected to the ARM7 through Complex Programmable Logic Device (CPLD). The CPLD is in turn connected to the ARM7 using Serial Peripheral Interface (SPI). The ARM7 boards collect the information from the peripherals and send it to the ARM9 board. The communication between ARM7 and ARM9 is via UART (Universal Asynchronous Receiver Transmitter) over CAN (Controller Area Network). The ARM9 board has got the software intelligence. The ARM9 behaves as a master and two ARM7 boards behave as slaves. Being master ARM9 passes tokens to ARM7 which in turn returns (Acknowledges) the token. The ARM9 is further connected to Proxy via Ethernet. The proxy is further connected to the service platform (server) via Ethernet. So subsequently any decisions at any stage can be changed at server level. Further these commands can be passed on to ARM9 which in turn controls the peripherals through ARM7. (a) The system which we have developed consists of ARM9 as a master, Two ARM7 as Slaves. The communication between ARM9-ARM7 is via UART over a CAN, <br /> (b) Each ARM7 further communicates serially (RS232) with the two 8051 Microcontroller nodes, (c)Thus a networked Embedded System is developed wherein the serial data is brought over Ethernet. The ARM7 board, which is directly linked with the peripherals, can be modified of its functionality as and when required. The functionality of ARM7 can be modified by upgrading its firmware. To upgrade the firmware same communication link has been used. ARM7 receives the new firmware via same ARM9-ARM7 communication link. The Flash Write operation is performed using the source code to write the new firmware. Bootloader application for the ARM7 has been developed. The signature has been incorporated to assure authenticity of the new Firmware. Intel Hex File Format is used to parse the hex file.</span>

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Tumenjargal, Turtogtokh, Sangkyun Kim, Hirokazu Masui, and Mengu Cho. "CubeSat bus interface with Complex Programmable Logic Device." Acta Astronautica 160 (July 2019): 331–42. http://dx.doi.org/10.1016/j.actaastro.2019.04.047.

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Zhang, Wei. "Based on SoC Technology Frequency Measurement Meter." Applied Mechanics and Materials 556-562 (May 2014): 2974–77. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.2974.

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SoC is the ASICS (ApplieationSpeenIetgratdeCierulst) design methodology of the new technology, refers to the embedded system as the core technology used in PI-based, set of software and hardware in one, and the pursuit of products inclusive of the largest integrated system chip. The article in-depth exploration into the complexity of using VHDL language and system programmable logic device (CPLD) to develop "system-on-chip (SoC)" - such as adaptive frequency measurement accuracy of the basic methods to overcome the system of the previous frequency measurement accuracy is not high , measuring the accuracy of the process of change, approaching the speed of slow-type shift shortcomings.

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Zhang, Chao Zhu, Yue Zhu, and Ji Nan Han. "The Dual Sine Signal Generator Design Based on the Principle of Difference Frequency Filtering." Advanced Materials Research 981 (July 2014): 74–77. http://dx.doi.org/10.4028/www.scientific.net/amr.981.74.

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The paper attempts to realize the processing scheme of low cost dual sine wave generator. It used single-chip microcomputer and CPLD(Complex Programable Logic Device) as the control core. It maked use of CPLD and discrete component simulations to implement DDS principle. It utilized the filter circuit, integrated op-amp circuit and multiplier circuit instead of DAC chip. The range of frequency, amplitude and phase difference are 1Hz~1000Hz, 1V~3V and 0o~359o, respectively. The results show that a 2-channel sine signal generator can be designed with adjustable frequency, amplitude and phase difference.

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Zhou, Haili, Lijun Xu, Zhang Cao, XiaoLei Liu, and Shi Liu. "A complex programmable logic device-based high-precision electrical capacitance tomography system." Measurement Science and Technology 24, no. 7 (June 12, 2013): 074006. http://dx.doi.org/10.1088/0957-0233/24/7/074006.

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Irmansyah, Muhammad. "PENGIMPLEMENTASIAN TEKNOLOGI PROGRAMMABLE LOGIC DEVICE (PLD) SEBAGAI BINER CODE DECIMAL (BCD) UNTUK SCANNING KEYPAD." Elektron : Jurnal Ilmiah 5, no. 1 (August 22, 2018): 9–18. http://dx.doi.org/10.30630/eji.5.1.38.

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Industrial of electronics developed in many fields in the middle of 1990s. Base on this situation, the manufacturer produce the product by increased the function, display, low cost, low power consumption and small size. This kind of product must be supported by complex system, small number of integrated circuit and tiny printed circuit board (PCB). Many integrated technologies such as submicron semiconductor, PCB technology, and the using of PCB surface maximal. The market situation push the producer used modern technology in design and testing for example Programmable Logic Device (PLD). It is the integrated circuit using digital logic which can be changed this function by programming and can be used to industrial application. Programmable Logic Device (PLD) technology can be used to many logical programming by using only one IC. The application of this technology can be found in IC 22V10 with 24 pins. This IC can be applied to replace the function of IC 74299 as encoder decimal to biner to scanning keypad.

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Guerrero-Rivera, Ruben, Abigail Morrison, Markus Diesmann, and Tim C. Pearce. "Programmable Logic Construction Kits for Hyper-Real-Time Neuronal Modeling." Neural Computation 18, no. 11 (November 2006): 2651–79. http://dx.doi.org/10.1162/neco.2006.18.11.2651.

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Programmable logic designs are presented that achieve exact integration of leaky integrate-and-fire soma and dynamical synapse neuronal models and incorporate spike-time dependent plasticity and axonal delays. Highly accurate numerical performance has been achieved by modifying simpler forward-Euler-based circuitry requiring minimal circuit allocation, which, as we show, behaves equivalently to exact integration. These designs have been implemented and simulated at the behavioral and physical device levels, demonstrating close agreement with both numerical and analytical results. By exploiting finely grained parallelism and single clock cycle numerical iteration, these designs achieve simulation speeds at least five orders of magnitude faster than the nervous system, termed here hyper-real-time operation, when deployed on commercially available field-programmable gate array (FPGA) devices. Taken together, our designs form a programmable logic construction kit of commonly used neuronal model elements that supports the building of large and complex architectures of spiking neuron networks for real-time neuromorphic implementation, neurophysiological interfacing, or efficient parameter space investigations.

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Ruiz-Rosero, Juan, Gustavo Ramirez-Gonzalez, and Rahul Khanna. "Field Programmable Gate Array Applications—A Scientometric Review." Computation 7, no. 4 (November 11, 2019): 63. http://dx.doi.org/10.3390/computation7040063.

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Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers’ navigation systems. This paper reviews the top FPGAs’ applications by a scientometric analysis in ScientoPy, covering publications related to FPGAs from 1992 to 2018. Here we found the top 150 applications that we divided into the following categories: digital control, communication interfaces, networking, computer security, cryptography techniques, machine learning, digital signal processing, image and video processing, big data, computer algorithms and other applications. Also, we present an evolution and trend analysis of the related applications.

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Zhou, Zhimei, Yong Wan, Yin Liu, Xiaoyan Guo, Qilin Yin, and Chen Feng. "The advancement of cluster based FPGA place & route technic." MATEC Web of Conferences 309 (2020): 01014. http://dx.doi.org/10.1051/matecconf/202030901014.

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As one of the core components of electronic hardware systems, Field Programmable Logic Array (FPGA) device design technology continues to advance under the guidance of electronic information technology policies, and has made information technology applications. huge contribution. However, with the advancement of chip technology and the continuous upgrading of information technology, the functions that FPGAs need to perform are more and more complicated. How to efficiently perform layout design and make full use of chip resources has become an important technology to be solved and optimized in FPGA design. The FPGA itself is not limited to a specific function. It contains internal functions such as memory, protocol module, clock module, high-speed interface module and digital signal processing. It can be programmed through logic modules such as programmable logic unit modules and interconnects. Blank FPGA devices are designed to be high performance system applications with complex functions. The layout and routing technology based on cluster logic unit blocks can combine the above resources to give full play to its performance advantages, and its importance is self-evident. Based on the traditional FPGA implementation, this paper analyzes several advantages based on cluster logic block layout and routing technology, and generalizes the design method and flow based on cluster logic block layout and routing technology.

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Shi, Xiao Juan. "The Design and Implementation of Motion Control Card Based on DSP." Advanced Materials Research 102-104 (March 2010): 427–31. http://dx.doi.org/10.4028/www.scientific.net/amr.102-104.427.

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A hardware implement scheme is proposed based on digital signal processor, and the complex programmable logic device and industry standard architecture bus is proposed. The dual-port random access memory communication circuit, I/O port address decoding circuit, two axis control output circuit and position detecting circuit are developed, the main program and interrupt-serving program of digital signal processor are designed by the idea of modularization. The static accuray of the motion control card is tested via special experimental device. The present analysis show that the designed circuit is effective and the static control precision of motion control card is satisfied.

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Sun, Dong Ru, Xiao Jie Ye, Liang Cheng, Yi Hua Yao, and Yun Yue Ye. "Control System Design of Improved Vertical Lifting Stereo Garage with Linear Motor as Transverse Device." Applied Mechanics and Materials 416-417 (September 2013): 940–45. http://dx.doi.org/10.4028/www.scientific.net/amm.416-417.940.

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Rotating induction motor serving as transverse device in traditional stereo garage makes system complex and inefficient. Installing linear motor in lifting platform as direct drive unit can remove intermediate links and drag vehicle loading board of parking slot directly. In this paper, control system of vertical lifting stereo garage with linear induction motor is put forward, including overall organization, operating principle and software program.Linear motor is controlled by Programmable Logic Controller (PLC) in slip frequency control method and PI algorithm. Experiment results indicate that linear motor can track reference velocitycurveand the whole stereo garage can store and take out vehicles automatically and efficiently.

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Chen, Lei, Jie Han, Ling Jun Li, and Wei Hao. "Development of an Instrument for Machine Equipment State Inspection and Safety Evaluation Based on Embedded Technology." Applied Mechanics and Materials 235 (November 2012): 413–18. http://dx.doi.org/10.4028/www.scientific.net/amm.235.413.

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In modern industry, plant equipment must be maintained effectively to guarantee safety operation. An intelligent instrument for plant equipment state inspection and safety evaluation was developed based on embedded technology. Firstly, the overall structure of the instrument system was introduced. Then the mainboard circuits were designed based on ARM core microprocessor. The control logics of the dynamic machine signals acquisition subsystem were designed by using of a complex programmable logic device. After that, the embedded operating system was transplanted and device drivers were programmed. Finally, the functions of the applications were stated. The designed instrument can meet the needs of the vibration acquisition of the rotating machines satisfactorily and provide effective means for equipment maintenance.

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Chang, Y. H. "Complex programmable logic device-based closed-loop implementation of switched-capacitor step-down DC–DC converter for multiple output choices." IET Electric Power Applications 1, no. 6 (2007): 926. http://dx.doi.org/10.1049/iet-epa:20070089.

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Wang, Rui, Yong Guan, Min Zhou, Jie Zhang, and Xiaoyu Song. "A Component-Based Modeling and Validation Method for PLC Systems." Advances in Mechanical Engineering 6 (January 1, 2014): 127618. http://dx.doi.org/10.1155/2014/127618.

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Programmable logic controllers (PLCs) are complex embedded systems that are widely used in industry. This paper presents a component-based modeling and validation method for PLC systems using the behavior-interaction-priority (BIP) framework. We designed a general system architecture and a component library for a type of device control system. The control software and hardware of the environment were all modeled as BIP components. System requirements were formalized as monitors. Simulation was carried out to validate the system model. A realistic example from industry of the gates control system was employed to illustrate our strategies. We found a couple of design errors during the simulation, which helped us to improve the dependability of the original systems. The results of experiment demonstrated the effectiveness of our approach.

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Y. David Solomon Raju, Kesari Ananda Samhitha,. "Design and Implementation of the Turbo Encoder by using Magnitude Comparator in IVS Chip." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 6 (April 5, 2021): 1537–45. http://dx.doi.org/10.17762/turcomat.v12i6.2692.

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This research studies the concept and application of the Turbo_encoder to be an integrated module in the In-Vehicle Device (IVS) embedded module by using the magnitude comparator. To create the Turbo_encoder Module, the complex PLDS are used. The variants of series and parallel Turbo_encoders are discussed. It is shown that proportional to chip size processing time also increased in the Turbo_encoder parallel computing variant system. The magnitude comparator with parallel computing variant system is implemented in this project. The usage of proposed logic resulted in efficient area and power usage. The architecture construction using Verilog HDL and implementation and simulation are executed in the Xilinx-ise tool. To incorporate the built module, Xilinx Vertex Low Power is used. The Turbo_encoder module on a single programmable computer is planned to be part of the IVS chip.

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DOKOUZYANNIS, STAVROS P., and ARGIRIS P. MOKIOS. "EVALUATION STUDY OF SYSTOLIC ARRAY PROCESSORS OPTIMIZATION AND MAPPING ON k-LUT FPGA DEVICES." Journal of Circuits, Systems and Computers 22, no. 04 (April 2013): 1350025. http://dx.doi.org/10.1142/s0218126613500254.

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This paper analyzes the design automation of embedded Systolic Array Processors (SAPs), into large scale Field Programmable Gate Array (FPGA) devices. SAPs are hardware implementations of a class of iterative, high-level language algorithms, for applications where the high-speed of processing has the principal meaning of a design. Embedding SAPs onto FPGAs is a complex process. The optimization phase in this process reduces the SAP significantly, thus less FPGA area is occupied by the embedded design, without any loss in the final performance. The present paper examines the effect of Projection Vectors (PVs) and Task Scheduling Vectors (TSVs) on the optimization process. Two optimization approaches are examined, namely technology mapping using FlowMap and Flowpack algorithms and optimization via logic synthesis using Xilinx Synthesis Tool. The multiplication of matrices, with entries being up to 32-bit integer vectors, has been taken as a sample space for the experiments conducted. The results, confirm that the selection of PV and TSV greatly affects the number of input/output signal connections of the FPGA, while the selection of an optimization approach affects the final number of logic resources occupied on the targeted device.

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Xue, Yan Lin, and Bin Wei Chen. "A Research about Acquisition and Transmission of the Water Meter's Image Based on STM32." Advanced Materials Research 1037 (October 2014): 187–90. http://dx.doi.org/10.4028/www.scientific.net/amr.1037.187.

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This paper introduces the hardware and programming involved in collecting the image of the digital code wheel by microprocessor STM32 directly driving camera chip OV7670 and the transmission of collected image. This design simplifies the hardware structure to the greatest extent and minimizes cost. Our design has three advantages. Fist, direct driving saves the intermediary register chip, simplifies the circuit and also reduces the amount of elements used. Second, by using the CMOS digital image sensor with windowing function—OV7670 to capture the image of code wheel we simplify the hardware structure and reduces the cost because of the D/A conversion circuit and complex programmable logic device contained in OV7670. Third, we successively solve the problem of the small capacity (20k) of STM32F103C8T6 chip’s SRAM by cutting out 24080 images from 640480. So time spent on data transmission and processing can be shortened.

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Шишацький, А. В., Ю. В. Журавський, В. М. Остапчук, М. В. Сова, О. Д. Гаращук, and О. І. Пікуль. "Complex methodology of parameters management of military radio networks in the conditions of uncertainty of the radioelectronic situation." Системи обробки інформації, no. 3(162), (September 30, 2020): 73–85. http://dx.doi.org/10.30748/soi.2020.162.08.

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The experience of the Joint Forces operation (Anti-terrorist operation in Donetsk and Luhansk oblasts) shows that the current order of management of military radio communication systems does not always meet the modern requirements for them. The classic centralized approach to the management of channel and network resources of military radio systems does not quite meet modern requirements, so the authors of this article proposed to take mobile self-organizing networks as a basic principle of construction. The authors propose a comprehensive method of managing the parameters of military radio networks in conditions of uncertainty of the electronic environment, the essence of which is to ensure the maintenance of the specified values of the performance of military radio communication systems at the appropriate level. The article is based on the control principle, which is described in the reference network model of open systems interaction, but with some additions and changes. This approach generally allows for end-to-end management of channel and network resources of military radio systems in a complex electronic environment. In the article, the device of fuzzy logic, the theory of electronic suppression, neural networks, the theory of noise protection, the theory of antennas, noise-resistant coding are used. The proposed complex methodology should be used in the development of software for modules (units) for the assessment of advanced radio communications, based on open architecture interfaces version SCA 2.2, which will: use effective signal-code structures to ensure noise immunity of channels; to ensure efficient use of the radio frequency resource of programmable radio communication means; increase the speed of evaluation of communication channels; reduce the use of computing resources of radio communications with programmable architecture.

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Ma, Kefan, Liquan Xiao, and Jianmin Zhang. "An Effective FPGA Solver on Probability Distribution and Preprocessing." Electronics 8, no. 3 (March 18, 2019): 333. http://dx.doi.org/10.3390/electronics8030333.

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The Boolean satisfiability (SAT) problem is the key problem in computer theory and application. A novel algorithm is introduced to implement a SLS hardware solver called probSAT+. The algorithm has no complex heuristic, and it only depends on the concepts of preprocessing technology, probability distribution and centralized search. Through constraining the initial assignments of the variables, the number of flipped variables was reduced while the solver finding a solution. Moreover, the algorithm no longer adopts some non-continuous if-then-else decisions, but depends on a single continuous function f(x,v). The flipping probability is not obtained by complex calculations, instead being selected by looking up tables, which effectively improves the performance of the solver. As far as we know, the probability distribution selection strategy descripted by hardware description language is firstly adopted by hardware SAT solver, which can be easily transplanted to any programmable logic device. The experimental results show that the probSAT+ solver is generally lower than the advanced software solver in the number of flips (up to 9.8 × 10 6 ), and the speedup is approximately 2.6 times with single thread, which shows that the probSAT+ has better results with fewer variables flipping times when a solution can be found. In addition, the success ratio of the solver in finding a solution of the problem in a suitable time is 100%.

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Noorsal, Emilia, Saharul Arof, Saiful Zaimy Yahaya, Zakaria Hussain, Daniel Kho, and Yusnita Mohd Ali. "Design of an FPGA-Based Fuzzy Feedback Controller for Closed-Loop FES in Knee Joint Model." Micromachines 12, no. 8 (August 16, 2021): 968. http://dx.doi.org/10.3390/mi12080968.

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Functional electrical stimulation (FES) device has been widely used by spinal cord injury (SCI) patients in their rehab exercises to restore motor function to their paralysed muscles. The major challenge of muscle contraction induced by FES is early muscle fatigue due to the open-loop stimulation strategy. To reduce the early muscle fatigue phenomenon, a closed-loop FES system is proposed to track the angle of the limb’s movement and provide an accurate amount of charge according to the desired reference angle. Among the existing feedback controllers, fuzzy logic controller (FLC) has been found to exhibit good control performance in handling complex non-linear systems without developing any complex mathematical model. Recently, there has been considerable interest in the implementation of FLC in hardware embedded systems. Therefore, in this paper, a digital fuzzy feedback controller (FFC) embedded in a field-programmable gate array (FPGA) board was proposed. The digital FFC mainly consists of an analog-to-digital converter (ADC) Data Acquisition and FLC sub-modules. The FFC was designed to monitor and control the progress of knee extension movement by regulating the stimulus pulse width duration to meet the target angle. The knee is expected to extend to a maximum reference angle setting (70°, 40° or 30°) from its normal position of 0° once the stimulus charge is applied to the muscle by the FES device. Initially, the FLC was modelled using MATLAB Simulink. Then, the FLC was hardcoded into digital logic using hardware description language (HDL) Verilog codes. Thereafter, the performance of the digital FLC was tested with a knee extension model using the HDL co-simulation technique in MATLAB Simulink. Finally, for real-time verification, the designed digital FFC was downloaded to the Intel FPGA (DE2-115) board. The digital FFC utilized only 4% of the total FPGA (Cyclone IV E) logic elements (LEs) and required 238 µs to regulate stimulus pulse width data, including 3 µs for the FLC computation. The high processing speed of the digital FFC enables the stimulus pulse width duration to be updated every stimulation cycle. Furthermore, the implemented digital FFC has demonstrated good control performance in accurately controlling the stimulus pulse width duration to reach the desired reference angle with very small overshoot (1.4°) and steady-state error (0.4°). These promising results are very useful for a real-world closed-loop FES application.

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Della Giustina, Davide, Amelia Alvarez de Sotomayor, Alessio Dedè, and Francisco Ramos. "A Model-Based Design of Distributed Automation Systems for the Smart Grid: Implementation and Validation." Energies 13, no. 14 (July 10, 2020): 3560. http://dx.doi.org/10.3390/en13143560.

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The paper aims at describing a model-based approach to design automation logics for fault location and supply restoration in medium voltage distribution networks. The application of automation functions along medium voltage feeders and, in particular, the installation of protection devices in secondary substations mandates the design and the implementation of complex logics to coordinate the operations of this hardware in case of fault occurrences. This synchronization is realized with the exchange of IEC 61850 GOOSE messages, but the correct usage of this information must be implemented in each protection device through dedicated logics, which are not in the common out-of-the-box system configurations. To support the introduction and the design of these logics, an automata-based approach has been proposed and successfully demonstrated in a real environment in the European research project IDE4L. This formal methodology has been introduced to simplify the design phase and to standardize the logics implemented in the protection prototypes realized in the project. The same models have also been used in the implementation phase with a semi-automatic code generation procedure, considering as a target system the software programmable logic controllers (soft-PLCs), available on the protection devices. Based on the test results and the short time to set up the test bench, this approach proved to be a reliable and effective way to implement complex medium voltage (MV) automation logics such those needed in modern smart grids.

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Zeleneva, І. Ya, Т. V. Golub, T. S. Diachuk, and А. Ye Didenko. "CONVEYOR MODEL AND IMPLEMENTATION OF THE REAL NUMBERS ADDER ON FPGA." ELECTRICAL AND COMPUTER SYSTEMS 33, no. 109 (December 22, 2020): 21–31. http://dx.doi.org/10.15276/eltecs.33.109.2020.3.

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The purpose of these studies is to develop an effective structure and internal functional blocks of a digital computing device – an adder, that performs addition and subtraction operations on floating- point numbers presented in IEEE Std 754TM-2008 format. To improve the characteristics of the adder, the circuit uses conveying, that is, division into levels, each of which performs a specific action on numbers. This allows you to perform addition / subtraction operations on several numbers at the same time, which increas- es the performance of calculations, and also makes the adder suitable for use in modern synchronous cir- cuits. Each block of the conveyor structure of the adder on FPGA is synthesized as a separate project of a digital functional unit, and thus, the overall task is divided into separate subtasks, which facilitates experi- mental testing and phased debugging of the entire device. Experimental studies were performed using EDA Quartus II. The developed circuit was modeled on FPGAs of the Stratix III and Cyclone III family. An ana- logue of the developed circuit was a functionally similar device from Altera. A comparative analysis is made and reasoned conclusions are drawn that the performance improvement is achieved due to the conveyor structure of the adder. Implementation of arithmetic over the floating-point numbers on programmable logic integrated cir- cuits, in particular on FPGA, has such advantages as flexibility of use and low production costs, and also provides the opportunity to solve problems for which there are no ready-made solutions in the form of stand- ard devices presented on the market. The developed adder has a wide scope, since most modern computing devices need to process floating-point numbers. The proposed conveyor model of the adder is quite simple to implement on the FPGA and can be an alternative to using built-in multipliers and processor cores in cases where the complex functionality of these devices is redundant for a specific task.

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Pakhomov, Yu, N. Shulga, and L. Piddubna. "ON THE QUESTION OF THE EFFECTIVENESS OF NETWORK TECHNOLOGIES IN AUTOMATED GAS SUPPLY SYSTEMS." Municipal economy of cities 1, no. 161 (March 26, 2021): 267–73. http://dx.doi.org/10.33042/2522-1809-2021-1-161-267-273.

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The topical issues of development of automated control systems of gas control stations (GCS) and ways of reliable and economical functioning of the gas supply system in modern conditions have been considered in the article. The implementation of European innovative technologies, which are associated with using the modern equipment, telemetry tools to transmit the equipment operation parameters to the dispatcher control panel are the one of the ways to increase the safety and efficiency of GCS performance. The characteristic of the modern complex of telemetry, the raising of efficiency, reliability and safe operation of the gas supply systems due to the possibility of monitoring, technological control and management from the central dispatcher control room are given. The complex of telemetry helps to prevent emergency situations at facilities and to ensure control over unauthorized entry into the GCS premises by unauthorized persons. The article discusses the use of the automated system of operative-dispatching management (ASODM). It is a multi-level automated system that ensures the reliable functioning of the gas supply system at all levels of the hierarchy. It has been shown that the result of the creation of the ASODM are equipping of the control object with microprocessor control and management devices, the integration of various automation tools into a single information management system. It has been proven that the development of ASODM of GCS on the basis of local control and management modules using traditional approaches to creation of automation systems and using the cellular telephone communication as data transmission channels based on GSM-technologies are most rational. The digital control device, which is made on the technological platform of the programmable logic integrated circuit (PLIC), is the main element of the local control and management module. Digital control device (PLIC controller) is a relatively inexpensive and reliable equipment in an automated local GCS control system. The method of data transmission via GSM / GPRS wireless communication channel is considered. The use of GSM-modems and GPRS technology allows to remove restrictions on the distance of data transmission, as well as allows to fully automate the process of transmission and processing of information. The use of GSM / GPRS-technologies in the vehicles of the emergency dispatch service is also shown. The dispatcher can fully monitor the movement of the car with registration on the map of the city where the car is located.

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Journal articles on the topic 'Complex Programmable Logic Device (CPLD)'

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