Relevant bibliographies by topics / Computational logic unit

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Computational logic unit'

Author: Grafiati
Published: 7 June 2025
Last updated: 25 June 2025

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Journal articles on the topic "Computational logic unit"

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Guller, Dušan. "A Proof Calculus for Automated Deduction in Propositional Product Logic." Mathematics 12, no. 23 (2024): 3805. https://doi.org/10.3390/math12233805.

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Propositional product logic belongs to the basic fuzzy logics with continuous t-norms using the product t-norm (defined as the ordinary product of real numbers) on the unit interval [0,1]. This paper introduces a proof calculus for the product logic which is suitable for automated deduction. The calculus provides one of possible generalisations of the family of modifications of the procedure (algorithm) of Davis, Putnam, Logemann, and Loveland (DPLL) in the context of fuzzy logics. We show that the calculus is refutation sound and finitely complete as well. The deduction, satisfiability, and validity problems are solved in the finite case. The achieved results contribute to the theoretical (logic and computational) description of multi-step fuzzy inference.
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Pinto, Felipe, and Ioannis Vourkas. "Robust Circuit and System Design for General-Purpose Computational Resistive Memories." Electronics 10, no. 9 (2021): 1074. http://dx.doi.org/10.3390/electronics10091074.

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Resistive switching devices (memristors) constitute a promising device technology that has emerged for the development of future energy-efficient general-purpose computational memories. Research has been done both at device and circuit level for the realization of primitive logic operations with memristors. Likewise, important efforts are placed on the development of logic synthesis algorithms for resistive RAM (ReRAM)-based computing. However, system-level design of computational memories has not been given significant consideration, and developing arithmetic logic unit (ALU) functionality entirely using ReRAM-based word-wise arithmetic operations remains a challenging task. In this context, we present our results in circuit- and system-level design, towards implementing a ReRAM-based general-purpose computational memory with ALU functionality. We built upon the 1T1R crossbar topology and adopted a logic design style in which all computations are equivalent to modified memory read operations for higher reliability, performed either in a word-wise or bit-wise manner, owing to an enhanced peripheral circuitry. Moreover, we present the concept of a segmented ReRAM architecture with functional and topological features that benefit flexibility of data movement and improve latency of multi-level (sequential) in-memory computations. Robust system functionality is validated via LTspice circuit simulations for an n-bit word-wise binary adder, showing promising performance features compared to other state-of-the-art implementations.
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Kim, Taehoon, and Yeonbae Chung. "Logic-Compatible Embedded DRAM Architecture for Multifunctional Digital Storage and Compute-in-Memory." Applied Sciences 14, no. 21 (2024): 9749. http://dx.doi.org/10.3390/app14219749.

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The compute-in-memory (CIM) which embeds computation inside memory is an attractive scheme to circumvent von Neumann bottlenecks. This study proposes a logic-compatible embedded DRAM architecture that supports data storage as well as versatile digital computations. The proposed configurable memory unit operates in three modes: (1) memory mode in which it works as a normal dynamic memory, (2) logic–arithmetic mode where it performs bit-wise Boolean logic and full adder operations on two words stored within the memory array, and (3) convolution mode in which it executes digitally XNOR-and-accumulate (XAC) operation for binarized neural networks. A 1.0-V 4096-word × 8-bit computational DRAM implemented in a 45-nanometer CMOS technology performs memory, logic and arithmetic operations at 241, 229, and 224 MHz while consuming the energy of 7.92, 8.09, and 8.19 pJ/cycle. Compared with conventional digital computing, it saves energy and latency of the arithmetic operation by at least 47% and 46%, respectively. For VDD = 1.0 V, the proposed CIM unit performs two 128-input XAC operations at 292 MHz with an energy consumption of 20.8 pJ/cycle, achieving 24.6 TOPS/W. This marks at least 11.9× better energy efficiency and 38.8× better delay, thereby achieving at least 461× better energy-delay product than traditional 8-bit wide computing hardware.
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Jin, Chen. "A review on multiple-valued logic circuits." Applied and Computational Engineering 43, no. 1 (2024): 322–26. http://dx.doi.org/10.54254/2755-2721/43/20230857.

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Since the traditional binary logic has several disadvantages including inaccuracy, high complexity, and limited applications. Multiple-Valued Logic (MVL), which can store more information in one digit than binary logics, require less number of logic gates and take the third value in practical logic problems, is developed and introduced. More information stored per digit leads to higher computational efficiency. Less logic gates results in more spaces on the circuit board. Considering the third value means higher accuracy. In this research, some examples of different MVL circuit are designed to give a rough picture of current research in this domain. These designs are based on ternary and quaternary logics rather than binary logics. Besides, reliability evaluation through mathematical approach is presented in order to prove that the new design is more preferable. This can be carried out with mathematical analysis such as calculating a matrix that reflects its reliability, and simulating different designs to obtain certain values and comparing them with each other. Despite facing various challenges, including complicated physical implementation and difficulty to modulate the signals. This means that there is still potential of further research in this domain of logic circuits. This result in the conclusion that the MVL logic circuits will replace the conventional binary logic circuits in the future, and probably that decimal logic would be developed and no binary-to-decimal conversion unit will be required.
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Kim, Hyojin, Daniel Bojar, and Martin Fussenegger. "A CRISPR/Cas9-based central processing unit to program complex logic computation in human cells." Proceedings of the National Academy of Sciences 116, no. 15 (2019): 7214–19. http://dx.doi.org/10.1073/pnas.1821740116.

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Controlling gene expression with sophisticated logic gates has been and remains one of the central aims of synthetic biology. However, conventional implementations of biocomputers use central processing units (CPUs) assembled from multiple protein-based gene switches, limiting the programming flexibility and complexity that can be achieved within single cells. Here, we introduce a CRISPR/Cas9-based core processor that enables different sets of user-defined guide RNA inputs to program a single transcriptional regulator (dCas9-KRAB) to perform a wide range of bitwise computations, from simple Boolean logic gates to arithmetic operations such as the half adder. Furthermore, we built a dual-core CPU combining two orthogonal core processors in a single cell. In principle, human cells integrating multiple orthogonal CRISPR/Cas9-based core processors could offer enormous computational capacity.
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Member, Takahiko Murayama, Associate, Hidekazu Yamada, Tadao Nakamura, Yoshiharu Shigei, and Yoshio Yoshioka. "Characteristics of a programmable logic unit." Systems and Computers in Japan 18, no. 9 (1987): 31–43. http://dx.doi.org/10.1002/scj.4690180904.

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Bragagnini, Walter, Paolo Guazzoni, Maurizio Pitalieri, and Luisa Zetta. "Computational logic unit for a microprogrammed data acquisition system: an evaluation prototype." Microprocessing and Microprogramming 30, no. 1-5 (1990): 67–74. http://dx.doi.org/10.1016/0165-6074(90)90219-y.

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Vinyas, K. S., and K.B.Ramesh. "Design and Implementation of Arithmetic Unit using Vedic Multiplier." Journal of Optoelectronics and Communication 6, no. 2 (2024): 39–46. https://doi.org/10.5281/zenodo.11632356.

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<em>The Arithmetic Logic Unit (ALU) is an essential part of digital computing that performs arithmetic and logical operations. The goal of this study is to improve computational efficiency, especially in multiplication operations, by investigating the integration of dedicated multiplier circuits inside the ALU architecture. The design and implementation of a logic unit utilizing Vedic multiplier principles offer a promising avenue for advancing the efficiency and performance of digital circuits. By harnessing ancient mathematical wisdom in modern computing applications, this research contributes to the ongoing pursuit of innovative and sustainable solutions in the field of digital design and engineering. The design and implementation of a logic unit utilizing Vedic multiplier principles offer a promising avenue for advancing the efficiency and performance of digital circuits. By harnessing ancient mathematical wisdom in modern computing applications, this research contributes to the ongoing pursuit of innovative and sustainable solutions in the field of digital design and engineering.</em>
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Romli, Nurul Atiqah, Nur Fariha Syaqina Zulkepli, Mohd Shareduwan Mohd Kasihmuddin, et al. "Unsupervised logic mining with a binary clonal selection algorithm in multi-unit discrete Hopfield neural networks via weighted systematic 2 satisfiability." AIMS Mathematics 9, no. 8 (2024): 22321–65. http://dx.doi.org/10.3934/math.20241087.

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&lt;p&gt;Evaluating behavioral patterns through logic mining within a given dataset has become a primary focus in current research. Unfortunately, there are several weaknesses in the research regarding the logic mining models, including an uncertainty of the attribute selected in the model, random distribution of negative literals in a logical structure, non-optimal computation of the best logic, and the generation of overfitting solutions. Motivated by these limitations, a novel logic mining model incorporating the mechanism to control the negative literal in the systematic Satisfiability, namely Weighted Systematic 2 Satisfiability in Discrete Hopfield Neural Network, is proposed as a logical structure to represent the behavior of the dataset. For the proposed logic mining models, we used ratio of &lt;italic&gt;r&lt;/italic&gt; to control the distribution of the negative literals in the logical structures to prevent overfitting solutions and optimize synaptic weight values. A new computational approach of the best logic by considering both true and false classification values of the learning system was applied in this work to preserve the significant behavior of the dataset. Additionally, unsupervised learning techniques such as Topological Data Analysis were proposed to ensure the reliability of the selected attributes in the model. The comparative experiments of the logic mining models by utilizing 20 repository real-life datasets were conducted from repositories to assess their efficiency. Following the results, the proposed logic mining model dominated in all the metrics for the average rank. The average ranks for each metric were Accuracy (7.95), Sensitivity (7.55), Specificity (7.93), Negative Predictive Value (7.50), and Mathews Correlation Coefficient (7.85). Numerical results and in-depth analysis demonstrated that the proposed logic mining model consistently produced optimal induced logic that best represented the real-life dataset for all the performance metrics used in this study.&lt;/p&gt;
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Bhoi, Bandan Kumar. "Optimized Logic Gate Design using QCA." International Journal for Research in Applied Science and Engineering Technology 12, no. 6 (2024): 1111–13. http://dx.doi.org/10.22214/ijraset.2024.63273.

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Abstract: Quantum-dot cellular automaton (QCA) represents a burgeoning and auspicious nanoelectronic computational framework for the forthcoming generation, where binary data is encoded through the electronic charge arrangement within a cell. This architec- ture, rooted in digital logic, leverages individual electrons within arrays of quantum dots to execute binary operations. At the core of QCA circuits lies the QCA cell, serving as a fundamental unit for constructing basic gates and logic devices within QCA architectures. An assessment of diverse QCA-based XOR gate implementations is conducted in this study, alongside the proposition of novel layouts exhibiting enhanced performance metrics. The paper delves into various methodologies for designing QCA circuits, specifically focus- ing on the XOR gate. These layouts demonstrate a reduced number of crossovers and a diminished cell count in comparison to the conventional structures documented in existing literature. Notably, these design configurations hold significance for communication- centric circuit applications, particularly in activities such as phase detection within digital circuits, arithmetic computations, and error identification and rectification processes. A comparative analysis of different circuit designs is also provided, illustrating the potential of the proposed layouts in realizing more intricate circuits. The simulations in this study are executed utilizing the QCADesigner tool.
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Dissertations / Theses on the topic "Computational logic unit"

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Nordliden, Petter, and Sjöbladh Linda Didrik. "Måste det alltid bråkas med bråk? : En systematisk litteraturstudie om stambråkets betydelse i matematikundervisningen." Thesis, Linnéuniversitetet, Institutionen för matematik (MA), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:lnu:diva-91687.

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Denna systematiska litteraturstudie syftar till att med hjälp av forskning identifiera avgörande faktorer för framgångsrika undervisningsstrategier av stambråk i grundskolans matematikundervisning. Studien baseras på elva vetenskapliga artiklar som bearbetats systematiskt med hjälp av innehållsanalys för att besvara forsknings-frågorna om vilka avgörande faktorer som forskningen visar för undervisningen av stambråk samt vilka framgångsrika undervisningsstrategier som finns. Forskningen visar att areamodellen som representationsform dominerar undervisningen av bråk vilket innebär att stambråk får lite plats i undervisningen. Stambråket är en viktig del för att kunna tillägna sig avgörande faktorer av bråk. Resultatet visar att en undervisning med linear measurement (linjära representationsformer) betonar stambråkets roll som tolkningsverktyg för att kunna jämföra andra bråk samt det omvända förhållandet där en större nämnare utgör en mindre andel. Resultatet visar också att undervisningen av stambråk etablerar grundläggande principer för rationella tal och mer avancerade matematiska områden som proportionalitet och algebra. Därmed är lärares val av undervisningsstrategier och representationsformer samt deras kunskaper inom dessa områden vitala för vad eleverna kan tillägna sig i samband med bråkundervisningen.
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Pinkiewicz, T. "Design of a 32-bit Arithmetic Unit based on Composite Arithmetic and its Implementation on a Field Programmable Gate Array." Thesis, Honours thesis, University of Tasmania, 1999. https://eprints.utas.edu.au/584/1/Honours_Thesis.pdf.

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As we advance into the new century, computers of the future will require new techniques for arithmetic operations, which take advantage of the modern technology and yield accurate results. Floating-point arithmetic has been in use for nearly forty years, but is plagued with inaccuracies and limitations which necessitate introduction of a new concept in computer arithmetic, called Composite Arithmetic. Composite Arithmetic combines fixed-point and floating-point arithmetic into one integrated concept where numbers are automatically assigned the right form. This negates the need for differentiating between integer and real numbers in programming languages and allows for better accuracy in calculations. The concept has two main forms: exact and inexact. The exact form deals with integers and rational numbers, while inexact form deals with numbers that cannot be represented exactly. To develop and implement such concept in hardware, tools are needed that will allow for easy design and re-design process, at a low cost. A device that meets these requirements is a Field Programmable Gate Array. This electronic device provides quick and easy way of designing the system and then implementing it by downloading data to the device. It can then be tested and reprogrammed as desired, without the need for a new device. This thesis is an attempt to design and implement Simple Composite Arithmetic Machine (SCAM), which will be capable of performing operations on exact numbers (rational and integer numbers). The core of the research is Composite Arithmetic Unit, which contains operations like Multiply, Divide, Add and Subtract. It also can find Greatest Common Divisor and cast out common factors of two numbers. The CAU is controlled using Control Unit and Feedback Unit, and results are stored in the Register Unit. The SCAM is therefore a basic microarchitecture that will form a basis for further research in this field.
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Books on the topic "Computational logic unit"

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Della Vedova, Gianluca, Besik Dundua, Steffen Lempp, and Florin Manea, eds. Unity of Logic and Computation. Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-36978-0.

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Dundua, Besik. Unity of Logic and Computation: 19th Conference on Computability in Europe, CiE 2023, Batumi, Georgia, July 24-28, 2023, Proceedings. Springer, 2023.

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Book chapters on the topic "Computational logic unit"

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Goutagny, Pierre, Aymeric Fromherz, and Raphaël Monat. "CUTECat: Concolic Execution for Computational Law." In Lecture Notes in Computer Science. Springer Nature Switzerland, 2025. https://doi.org/10.1007/978-3-031-91121-7_2.

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Abstract Many legal computations, including the amount of tax owed by a citizen, whether they are eligible to social benefits, or the wages due to civil state servants, are specified by computational laws. Their application, however, is performed by expert computer programs intended to faithfully transcribe the law into computer code. Bugs in these programs can lead to dramatic societal impact, e.g., paying employees incorrect amounts, or not awarding benefits to families in need. To address this issue, we consider concolic unit testing, a combination of concrete execution with SMT-based symbolic execution, and propose CUTECat, a concolic execution tool targeting implementations of computational laws. Such laws typically follow a pattern where a base case is later refined by many exceptions in following law articles, a pattern that can be formally modeled using default logic. We show how to handle default logic inside a concolic execution tool, and implement our approach in the context of Catala, a recent domain-specific language tailored to implement computational laws. We evaluate CUTECat on several programs, including the Catala implementation of the French housing benefits and Section 132 of the US tax code. We show that CUTECat can successfully generate hundreds of thousands of testcases covering all branches of these bodies of law. Through several heuristics, we improve CUTECat’s scalability and usability, making the testcases understandable by lawyers and programmers alike. We believe CUTECat paves the way for the use of formal methods during legislative processes.
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Naibo, Alberto, Mattia Petrolo, and Thomas Seiller. "On the Computational Meaning of Axioms." In Logic, Epistemology, and the Unity of Science. Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-26506-3_5.

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Vourkas, Ioannis, and Georgios Ch Sirakoulis. "High-Radix Arithmetic-Logic Unit (ALU) Based on Memristors." In Emergence, Complexity and Computation. Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-22647-7_6.

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Lau, Kung-Kiu, and Mario Ornaghi. "Specifying Compositional Units for Correct Program Development in Computational Logic." In Program Development in Computational Logic. Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-25951-0_1.

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Kanovich, Max, Stepan Kuznetsov, and Andre Scedrov. "L-Models and R-Models for Lambek Calculus Enriched with Additives and the Multiplicative Unit." In Logic, Language, Information, and Computation. Springer Berlin Heidelberg, 2019. http://dx.doi.org/10.1007/978-3-662-59533-6_23.

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Marrouchi, Sahbi, and Souad Chebbi. "Unit Commitment Optimization Using Gradient-Genetic Algorithm and Fuzzy Logic Approaches." In Complex System Modelling and Control Through Intelligent Soft Computations. Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-12883-2_24.

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Osama, Muhammad, and Anton Wijs. "Hitching a Ride to a Lasso: Massively Parallel On-The-Fly LTL Model Checking." In Tools and Algorithms for the Construction and Analysis of Systems. Springer Nature Switzerland, 2024. http://dx.doi.org/10.1007/978-3-031-57249-4_2.

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AbstractThe need for massively parallel algorithms, suitable to exploit the computational power of hardware such as graphics processing units, is ever increasing. In this paper, we propose a new algorithm for the on-the-fly verification of Linear-Time Temporal Logic (LTL) formulae [45] that is aimed at running on such devices. We prove its correctness and termination guarantee, and experimentally compare a GPU implementation with state-of-the-art LTL model checkers. Our new GPU LTL-checking algorithm is up to 150$$\times $$ × faster on proving the correctness of a system than LTSmin running on a 32-core high-end CPU, and is more economic in using the available memory.
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Zhang, Hao, Yuetao Wang, Yuhan Tan, and Jilong Zhao. "Parametric Skin Design Method Based on Plane Crystallographic Group Operation Principle." In Computational Design and Robotic Fabrication. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-19-8637-6_3.

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AbstractUnder the dual constraints of industrialization and digitalization, the building skin and structure are further integrated to form standardized units to meet the requirements of architectural performance, industrial prefabrication and “complexity” aesthetic characteristics. The complex and diverse forms of today's building skin hide profound mathematical logic relations and operation rules of form generation. Crystallographic group with regular symmetry and the operation principles reflected by it is one of the most important rules and methods of form and pattern processing in skin design. The study of the mural symbols in ancient Egypt, the murals in the Alhambra, the manuscripts of Escher and the window lattice in ancient Chinese architecture profoundly reflects the basic operation principle of crystal group in shaping the skin form of architecture. Abundant and diverse architectural skin forms can be formed through the operation of symmetry group on basic graphic units. On the basis of clarifying the basic principle of crystal group action, the operation matrix of crystallographic symmetry group can be transformed into parameterized operation steps through programming language for visual operation, and then the skin form with high complexity and leap dimension can be generated by geometric algorithm, and the design method of building skin generation based on crystallographic group is constructed. In the selection of operation form, combined with the calculation of building performance and structure, the construction skin can be used in practical engineering is generated. Based on crystallographic group operation, the unifications of building skin and the classification simplification of components can meet the requirements of modular and unifications design in the process of building industrialization, and meet the requirements of current building industrialization and digitization. It has great research significance and value in the aspects of design and construction efficiency and material economic cost.
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He, Xiaoxu, and Mingyu Sun. "Biomimetic Form-Finding Study of Bone Needle Microstructure Based on Sponge Regeneration Behavior." In Computational Design and Robotic Fabrication. Springer Nature Singapore, 2024. http://dx.doi.org/10.1007/978-981-99-8405-3_8.

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AbstractThe concept of “nature-algorithm-structure” refers to a digital design method in architecture that draws inspiration from nature, extracting its mathematical and physical conceptual models to construct structural systems with parameters. This study aims to address the challenge of parametric form-finding in reticular tension structures. By observing the phenomenon of “sponge regeneration”, we further illustrate the generation and optimization of reticular tension structures through the hierarchical structures of “monomer”-“path”-“mesh”. Tensile structural systems are rebound forms, and their analytical models must account for their nonlinear characteristics and the existence of equilibrium self-course. Starting from the growth dynamics of “sponge regeneration behavior”, this paper extracts the logic behind it: sponge monomers combine randomly into partial units under the condition of shredding and discrete, forming a single organism through aggregation. The multi-dimensional bone needle serves as a structural component, enabling multi-axis reorganization, while the multi-directional mesh surface as a morphological component realizes multi-branch reproduction, forming a natural “network tension structure”. This study focuses on the biomimetic form-finding of bone needle microstructure, drawing inspiration from sponge regeneration behavior. By analyzing the growth dynamics of sponge regeneration, we aim to develop a better understanding of the principles behind the formation of bone needle microstructure. This finding provides significant reference for the development of modern structures and promotes the bioshape and optimization of tensile structures.
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Hu, Changbin, Lisong Bi, ZhengGuo Piao, ChunXue Wen, and Lijun Hou. "Coordinative Optimization Control of Microgrid Based on Model Predictive Control." In Research Anthology on Smart Grid and Microgrid Development. IGI Global, 2022. http://dx.doi.org/10.4018/978-1-6684-3666-0.ch012.

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This article describes how basing on the future behavior of microgrid system, forecasting renewable energy power generation, load and real-time electricity price, a model predictive control (MPC) strategy is proposed in this article to optimize microgrid operations, while meeting the time-varying requirements and operation constraints. Considering the problems of unit commitment, energy storage, economic dispatching, sale-purchase of electricity and load reduction schedule, the authors first model a microgrid system with a large number of constraints and variables to model the power generation technology and physical characteristics. Meanwhile the authors use a mixed logic dynamical framework to guarantee a reasonable behavior for grid interaction and storage and consider the influences of battery life and recession. Then for forecasting uncertainties in the microgrid, a feedback mechanism is introduced in MPC to solve the problem by using a receding horizon control. The objective of minimizing the operation costs is achieved by an MPC strategy for scheduling the behaviors of components in the microgrid. Finally, a comparative analysis has been carried out between the MPC and some traditional control methods. The MPC leads to a significant improvement in operating costs and on the computational burden. The economy and efficiency of the MPC are shown by the simulations.
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Conference papers on the topic "Computational logic unit"

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Gupta, Nidhi. "Thermal analysis of energy efficient clock gated arithmetic logic unit on FPGA." In 2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT). IEEE, 2014. http://dx.doi.org/10.1109/iccicct.2014.6993103.

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Jianxin, Liu, and Tan Ping. "Fuzzy Logic Control of Integrated Hydraulic Actuator Unit Using High Speed Switch Valves." In 2009 International Conference on Computational Intelligence and Natural Computing (CINC). IEEE, 2009. http://dx.doi.org/10.1109/cinc.2009.65.

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Gupta, Nidhi. "Clock Power Analysis of Low Power Clock Gated Arithmetic Logic Unit on Different FPGA." In 2014 International Conference on Computational Intelligence and Communication Networks (CICN). IEEE, 2014. http://dx.doi.org/10.1109/cicn.2014.192.

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Kadam, D. P., S. S. Wagh, and P. M. Patil. "Thermal Unit Commitment Problem by Using Genetic Algorithm, Fuzzy Logic and Priority List Method." In International Conference on Computational Intelligence and Multimedia Applications (ICCIMA 2007). IEEE, 2007. http://dx.doi.org/10.1109/iccima.2007.338.

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Ersen, Ali, Volkan Ozguz, Chi Fan, Sadik Esener, and Sing H. Lee. "Smart Spatial Light Modulators (SLMs) on Si/PLZT." In Spatial Light Modulators and Applications. Optica Publishing Group, 1990. http://dx.doi.org/10.1364/slma.1990.tuc1.

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In the last few years extensive efforts have gone into the development of spatial light modulators (SLMs) for the realization of massively parallel optical processors [1-3]. The silicon-PLZT SLM approach is a promising approach and has the potential of combining the computational power of silicon with the communication capacity of optical interconnects [4]. Optical interconnects utilize the third dimension normal to the processing plane to provide the advantages of high speed parallel and global interconnections among simple silicon electronic circuits performing local computational operations. Fig. 1 shows the schematics of Si/PLZT SLM. In order to take more advantage of the computational power of silicon we want to increase the number of transistors we can put in each unit cell. Several logic gates combined with some storage capability and photodetectors will find many useful applications in opto-electronic systems. In this paper we discuss the improved fabrication techniques to achieve better yield and higher unit cell complexity. We will also report on the results of fabricated unit cell arrays with various complexities.
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Miller, Dale R. "Finding Unity in Computational Logic." In ACM-BCS Visions of Computer Science 2010. BCS Learning & Development, 2010. http://dx.doi.org/10.14236/ewic/vocs2010.3.

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Shen, Dah-Shi, Yi-Der Wu, V. K. Bykovski, J. Rosetti, and M. A. Fiddy. "Algorithm development for a digital optical processor." In OSA Annual Meeting. Optica Publishing Group, 1993. http://dx.doi.org/10.1364/oam.1993.mzz.7.

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The digital optical logic unit described here consists of two Semetex 48 by 48 element Sight-Mods, the pixel pattern from one being imaged on the second. Since the allowed pixel states are binary, the output from these modulators can have three possible states. We describe the practical difficulties associated with digital computing using hardware of this kind, including camera readout and thresholding procedures. Once the three level output has been captured, it can be interpreted directly to yield simple logical relationships between adjacent pixels. The execution of more complicated operations such as addition and multiply have been studied and algorithms developed, which can exploit the paralellism of the spatial light modulators. We describe these algorithms, identify the computational bottlenecks and discuss the potential such a system might attain. The latter obviously depends on eventual hardware capabilities, but novel exploitation of parallel addressing schemes and better use of the available three level output states offer new and different opportunities for improved computational performance.
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Falk, R. Aaron, C. David Capps, and Theodore L. Houk. "An Optical, Cross-Bar Arithmetic/Logic Unit." In Optical Computing. Optica Publishing Group, 1987. http://dx.doi.org/10.1364/optcomp.1987.tud6.

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As indicated in an earlier paper presented at this conference,(1) use of parallel Fourier optical pattern recognition techniques in conjunction with a final non-linear threshold allows rapid computation of sums and products in residue arithmetic. The coherence properties of the architecture reduce the number of non-linear elements to 2n-1 where n is the size of the radix. Incoherent point sources could also be used with the grating filters performing a holographic interconnect function, but, at the expense of requiring n2 non-linear elements. This expense is offset by allowing performance of any multi-level logic function, residue arithmetic being only one example of a multi-level logic function. This paper will describe an alternative technique to performing the desired n2 interconnect pattern which requires no lenses or filters, thereby significantly reducing the fabrication and alignment difficulties.
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9

Harvey, Nicholas, Robert Luke, James M. Keller, and Derek Anderson. "Speedup of fuzzy logic through stream processing on Graphics Processing Units." In 2008 IEEE Congress on Evolutionary Computation (CEC). IEEE, 2008. http://dx.doi.org/10.1109/cec.2008.4631314.

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Keyes, Robert W. "Overview of Electronic Switching Technologies for Digital Logic." In Photonic Switching. Optica Publishing Group, 1987. http://dx.doi.org/10.1364/phs.1987.wa2.

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Modern computation depends on the representation of information in digital form. “Digital” means that there are a discrete set of signal values. All contemporary electronic logic uses just two digits, binary representation of information. There are two recognizable signal values. A binary unit of information is known as a bit. It can be represented by the position of a switch of the familiar ON-OFF type. The state of the switch or the signal is also conveniently represented by a 0 or a 1.
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Reports on the topic "Computational logic unit"

1

Lutz, Carsten, Dirk Walther, and Frank Wolter. Quantitative Temporal Logics: PSpace and below. Technische Universität Dresden, 2005. http://dx.doi.org/10.25368/2022.146.

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Often the addition of metric operators to qualitative temporal logics leads to an increase of the complexity of satisfiability by at least one exponential. In this paper, we exhibit a number of metric extensions of qualitative temporal logics of the real line that do not lead to an increase in computational complexity. The main result states that the language obtained by extending since/until logic of the real line with the operators 'sometime within n time units', n coded in binary, is PSpace-complete even without the finite variability assumption. Without qualitative temporal operators the complexity of this language turns out to depend on whether binary or unary coding of parameters is assumed: it is still PSpace-hard under binary coding but in NP under unary coding.
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Choquette, Gary, Richard Rans, and Warren Peterson. PR000-22605-R06 Accurate Compressibility Estimates for Natural Gas. Pipeline Research Council International, Inc. (PRCI), 2024. http://dx.doi.org/10.55274/r0000068.

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This document describes methods to calculate estimated gas compressibility without having the full gas composition. The purpose of these methods is for use cases where reasonable accuracy is required but not critical and the methods must be computationally efficient such that they can be used in programmable logic controllers, remote terminal units, and supervisory control and data acquisition systems; akin to the functionality of the NX-19 or AGA-8 Gross methods but with higher accuracy. Multiple simplified calculation methods were evaluated with one method performing significantly better than the other methods. The best performing method was then tuned to better fit the reference data. The equations and associated source code for that method are contained as appendices in this report. The methods discussed here were analyzed only with respect to the application to gas phase (including some supercritical conditions) natural gas with minimal helium, hydrogen, or hydrogen sulfide. This version includes source code on the calculation method.
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