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1
Guller, Dušan. "A Proof Calculus for Automated Deduction in Propositional Product Logic." Mathematics 12, no. 23 (2024): 3805. https://doi.org/10.3390/math12233805.
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Propositional product logic belongs to the basic fuzzy logics with continuous t-norms using the product t-norm (defined as the ordinary product of real numbers) on the unit interval [0,1]. This paper introduces a proof calculus for the product logic which is suitable for automated deduction. The calculus provides one of possible generalisations of the family of modifications of the procedure (algorithm) of Davis, Putnam, Logemann, and Loveland (DPLL) in the context of fuzzy logics. We show that the calculus is refutation sound and finitely complete as well. The deduction, satisfiability, and validity problems are solved in the finite case. The achieved results contribute to the theoretical (logic and computational) description of multi-step fuzzy inference.
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Pinto, Felipe, and Ioannis Vourkas. "Robust Circuit and System Design for General-Purpose Computational Resistive Memories." Electronics 10, no. 9 (2021): 1074. http://dx.doi.org/10.3390/electronics10091074.
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Resistive switching devices (memristors) constitute a promising device technology that has emerged for the development of future energy-efficient general-purpose computational memories. Research has been done both at device and circuit level for the realization of primitive logic operations with memristors. Likewise, important efforts are placed on the development of logic synthesis algorithms for resistive RAM (ReRAM)-based computing. However, system-level design of computational memories has not been given significant consideration, and developing arithmetic logic unit (ALU) functionality entirely using ReRAM-based word-wise arithmetic operations remains a challenging task. In this context, we present our results in circuit- and system-level design, towards implementing a ReRAM-based general-purpose computational memory with ALU functionality. We built upon the 1T1R crossbar topology and adopted a logic design style in which all computations are equivalent to modified memory read operations for higher reliability, performed either in a word-wise or bit-wise manner, owing to an enhanced peripheral circuitry. Moreover, we present the concept of a segmented ReRAM architecture with functional and topological features that benefit flexibility of data movement and improve latency of multi-level (sequential) in-memory computations. Robust system functionality is validated via LTspice circuit simulations for an n-bit word-wise binary adder, showing promising performance features compared to other state-of-the-art implementations.
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Kim, Taehoon, and Yeonbae Chung. "Logic-Compatible Embedded DRAM Architecture for Multifunctional Digital Storage and Compute-in-Memory." Applied Sciences 14, no. 21 (2024): 9749. http://dx.doi.org/10.3390/app14219749.
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The compute-in-memory (CIM) which embeds computation inside memory is an attractive scheme to circumvent von Neumann bottlenecks. This study proposes a logic-compatible embedded DRAM architecture that supports data storage as well as versatile digital computations. The proposed configurable memory unit operates in three modes: (1) memory mode in which it works as a normal dynamic memory, (2) logic–arithmetic mode where it performs bit-wise Boolean logic and full adder operations on two words stored within the memory array, and (3) convolution mode in which it executes digitally XNOR-and-accumulate (XAC) operation for binarized neural networks. A 1.0-V 4096-word × 8-bit computational DRAM implemented in a 45-nanometer CMOS technology performs memory, logic and arithmetic operations at 241, 229, and 224 MHz while consuming the energy of 7.92, 8.09, and 8.19 pJ/cycle. Compared with conventional digital computing, it saves energy and latency of the arithmetic operation by at least 47% and 46%, respectively. For VDD = 1.0 V, the proposed CIM unit performs two 128-input XAC operations at 292 MHz with an energy consumption of 20.8 pJ/cycle, achieving 24.6 TOPS/W. This marks at least 11.9× better energy efficiency and 38.8× better delay, thereby achieving at least 461× better energy-delay product than traditional 8-bit wide computing hardware.
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Jin, Chen. "A review on multiple-valued logic circuits." Applied and Computational Engineering 43, no. 1 (2024): 322–26. http://dx.doi.org/10.54254/2755-2721/43/20230857.
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Since the traditional binary logic has several disadvantages including inaccuracy, high complexity, and limited applications. Multiple-Valued Logic (MVL), which can store more information in one digit than binary logics, require less number of logic gates and take the third value in practical logic problems, is developed and introduced. More information stored per digit leads to higher computational efficiency. Less logic gates results in more spaces on the circuit board. Considering the third value means higher accuracy. In this research, some examples of different MVL circuit are designed to give a rough picture of current research in this domain. These designs are based on ternary and quaternary logics rather than binary logics. Besides, reliability evaluation through mathematical approach is presented in order to prove that the new design is more preferable. This can be carried out with mathematical analysis such as calculating a matrix that reflects its reliability, and simulating different designs to obtain certain values and comparing them with each other. Despite facing various challenges, including complicated physical implementation and difficulty to modulate the signals. This means that there is still potential of further research in this domain of logic circuits. This result in the conclusion that the MVL logic circuits will replace the conventional binary logic circuits in the future, and probably that decimal logic would be developed and no binary-to-decimal conversion unit will be required.
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Kim, Hyojin, Daniel Bojar, and Martin Fussenegger. "A CRISPR/Cas9-based central processing unit to program complex logic computation in human cells." Proceedings of the National Academy of Sciences 116, no. 15 (2019): 7214–19. http://dx.doi.org/10.1073/pnas.1821740116.
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Controlling gene expression with sophisticated logic gates has been and remains one of the central aims of synthetic biology. However, conventional implementations of biocomputers use central processing units (CPUs) assembled from multiple protein-based gene switches, limiting the programming flexibility and complexity that can be achieved within single cells. Here, we introduce a CRISPR/Cas9-based core processor that enables different sets of user-defined guide RNA inputs to program a single transcriptional regulator (dCas9-KRAB) to perform a wide range of bitwise computations, from simple Boolean logic gates to arithmetic operations such as the half adder. Furthermore, we built a dual-core CPU combining two orthogonal core processors in a single cell. In principle, human cells integrating multiple orthogonal CRISPR/Cas9-based core processors could offer enormous computational capacity.
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Member, Takahiko Murayama, Associate, Hidekazu Yamada, Tadao Nakamura, Yoshiharu Shigei, and Yoshio Yoshioka. "Characteristics of a programmable logic unit." Systems and Computers in Japan 18, no. 9 (1987): 31–43. http://dx.doi.org/10.1002/scj.4690180904.
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Bragagnini, Walter, Paolo Guazzoni, Maurizio Pitalieri, and Luisa Zetta. "Computational logic unit for a microprogrammed data acquisition system: an evaluation prototype." Microprocessing and Microprogramming 30, no. 1-5 (1990): 67–74. http://dx.doi.org/10.1016/0165-6074(90)90219-y.
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Vinyas, K. S., and K.B.Ramesh. "Design and Implementation of Arithmetic Unit using Vedic Multiplier." Journal of Optoelectronics and Communication 6, no. 2 (2024): 39–46. https://doi.org/10.5281/zenodo.11632356.
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<em>The Arithmetic Logic Unit (ALU) is an essential part of digital computing that performs arithmetic and logical operations. The goal of this study is to improve computational efficiency, especially in multiplication operations, by investigating the integration of dedicated multiplier circuits inside the ALU architecture. The design and implementation of a logic unit utilizing Vedic multiplier principles offer a promising avenue for advancing the efficiency and performance of digital circuits. By harnessing ancient mathematical wisdom in modern computing applications, this research contributes to the ongoing pursuit of innovative and sustainable solutions in the field of digital design and engineering. The design and implementation of a logic unit utilizing Vedic multiplier principles offer a promising avenue for advancing the efficiency and performance of digital circuits. By harnessing ancient mathematical wisdom in modern computing applications, this research contributes to the ongoing pursuit of innovative and sustainable solutions in the field of digital design and engineering.</em>
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Romli, Nurul Atiqah, Nur Fariha Syaqina Zulkepli, Mohd Shareduwan Mohd Kasihmuddin, et al. "Unsupervised logic mining with a binary clonal selection algorithm in multi-unit discrete Hopfield neural networks via weighted systematic 2 satisfiability." AIMS Mathematics 9, no. 8 (2024): 22321–65. http://dx.doi.org/10.3934/math.20241087.
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<p>Evaluating behavioral patterns through logic mining within a given dataset has become a primary focus in current research. Unfortunately, there are several weaknesses in the research regarding the logic mining models, including an uncertainty of the attribute selected in the model, random distribution of negative literals in a logical structure, non-optimal computation of the best logic, and the generation of overfitting solutions. Motivated by these limitations, a novel logic mining model incorporating the mechanism to control the negative literal in the systematic Satisfiability, namely Weighted Systematic 2 Satisfiability in Discrete Hopfield Neural Network, is proposed as a logical structure to represent the behavior of the dataset. For the proposed logic mining models, we used ratio of <italic>r</italic> to control the distribution of the negative literals in the logical structures to prevent overfitting solutions and optimize synaptic weight values. A new computational approach of the best logic by considering both true and false classification values of the learning system was applied in this work to preserve the significant behavior of the dataset. Additionally, unsupervised learning techniques such as Topological Data Analysis were proposed to ensure the reliability of the selected attributes in the model. The comparative experiments of the logic mining models by utilizing 20 repository real-life datasets were conducted from repositories to assess their efficiency. Following the results, the proposed logic mining model dominated in all the metrics for the average rank. The average ranks for each metric were Accuracy (7.95), Sensitivity (7.55), Specificity (7.93), Negative Predictive Value (7.50), and Mathews Correlation Coefficient (7.85). Numerical results and in-depth analysis demonstrated that the proposed logic mining model consistently produced optimal induced logic that best represented the real-life dataset for all the performance metrics used in this study.</p>
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Bhoi, Bandan Kumar. "Optimized Logic Gate Design using QCA." International Journal for Research in Applied Science and Engineering Technology 12, no. 6 (2024): 1111–13. http://dx.doi.org/10.22214/ijraset.2024.63273.
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Abstract: Quantum-dot cellular automaton (QCA) represents a burgeoning and auspicious nanoelectronic computational framework for the forthcoming generation, where binary data is encoded through the electronic charge arrangement within a cell. This architec- ture, rooted in digital logic, leverages individual electrons within arrays of quantum dots to execute binary operations. At the core of QCA circuits lies the QCA cell, serving as a fundamental unit for constructing basic gates and logic devices within QCA architectures. An assessment of diverse QCA-based XOR gate implementations is conducted in this study, alongside the proposition of novel layouts exhibiting enhanced performance metrics. The paper delves into various methodologies for designing QCA circuits, specifically focus- ing on the XOR gate. These layouts demonstrate a reduced number of crossovers and a diminished cell count in comparison to the conventional structures documented in existing literature. Notably, these design configurations hold significance for communication- centric circuit applications, particularly in activities such as phase detection within digital circuits, arithmetic computations, and error identification and rectification processes. A comparative analysis of different circuit designs is also provided, illustrating the potential of the proposed layouts in realizing more intricate circuits. The simulations in this study are executed utilizing the QCADesigner tool.
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DRESCHER, CHRISTIAN, and TOBY WALSH. "A translational approach to constraint answer set solving." Theory and Practice of Logic Programming 10, no. 4-6 (2010): 465–80. http://dx.doi.org/10.1017/s1471068410000220.
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AbstractWe present a new approach to enhancing Answer Set Programming (ASP) with Constraint Processing techniques which allows for solving interesting Constraint Satisfaction Problems in ASP. We show how constraints on finite domains can be decomposed into logic programs such that unit-propagation achieves arc, bound or range consistency. Experiments with our encodings demonstrate their computational impact.
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Dominik, Ireneusz. "Interval Type-2 Fuzzy Logic Control of Maglev Test Stand." Applied Mechanics and Materials 759 (May 2015): 71–76. http://dx.doi.org/10.4028/www.scientific.net/amm.759.71.
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The paper contains a description of a research into applying classic algorithm of PID controller as well as advanced Type-2 Fuzzy logic controller to ensure stability of the levitating object in magnetic field. The implemented algorithm can handle uncertainties without increasing drastically the computational complexity, which is crucial in case of PLCs. The issues concerning the construction of the unit, where the experiments were carried out, are presented, as well as the characteristics of the object for different controllers.
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Fujiwara, Eiji, and Kohji Matsuoka. "Faultâtolerant kâoutâofân logic unit networks." Systems and Computers in Japan 19, no. 9 (1988): 21–31. http://dx.doi.org/10.1002/scj.4690190903.
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B, Premalatha. "PERFORMANCE ANALYSIS OF MEMRISTOR-BASED LOW POWER COMPUTATIONAL UNIT FOR HIGH SPEED PROCESSORS AND ITS FPGA MODELING USING FUZZY ASSISTANCE." ICTACT Journal on Microelectronics 9, no. 3 (2023): 1585–94. https://doi.org/10.21917/ijme.2023.0276.
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Random-access memory (RAM), however volatile, is used in modern computing systems for high-speed data transport. Memristors are employed as storage instead of solid-state devices due to their non-volatility and lower energy needs. Memristor-based digital design has gained popularity for low-power, space-efficient VLSI design. The most important computational units for building high-speed processors is the arithmetic logic unit (ALU). Being aware that these processors’ space and time requirements are significant due to the ALU’s constraint, memristors are employed to get around these restrictions. Memristors are used in the design and simulation of the building components that make up an ALU. In addition to having a smaller footprint than others and reduced latency, it is a strong contender for ALU design. This work compares CMOS logic with an ALU’s performance in terms of average power and integral energy for all of the memristor-based ALU’s computational units. In this work, performance analysis of a memristor-based ALU has been carried out for high-speed processors, taking fuzzy metrics into account to characterise the behaviour uncertainty of the memristor. To offer a complete picture of the ALU’s performance under various circumstances, fuzzy logic is utilised to evaluate the average power and integral energy of the ALU. The reconfigurable FPGAs’ high-likelihood characteristics can be used to model memristors.
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Singh, Naginder, and Kapil Parihar. "Comparative study of single precision floating point division using different computational algorithms." International Journal of Reconfigurable and Embedded Systems (IJRES) 12, no. 3 (2023): 336. http://dx.doi.org/10.11591/ijres.v12.i3.pp336-344.
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<span>This paper presents different computational algorithms to implement single precision floating point division on field programmable gate arrays (FPGA). Fast division computation algorithms can apply to all division cases by which an efficient result will be obtained in terms of delay time and power consumption. 24-bit Vedic multiplication (Urdhva-Triyakbhyam-sutra) technique enhances the computational speed of the mantissa module and this module is used to design a 32-bit floating point multiplier which is the crucial feature of this proposed design, which yields a higher computational speed and reduced delay time. The proposed design of floating-point divider using fast computational algorithms synthesized using Verilog hardware description language has a 32-bit floating point multiplier module unit and a 32-bit floating point subtractor module unit. Xilinx Spartan 6 SP605 evaluation platform is used to verify this proposed design on FPGA. Synthesis results provide the device utilization and propagation delay parameters for the proposed design and a comparative study is done with previous work. Input to the divider is provided in IEEE 754 32-bit formats.</span>
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MOHAN, Sri C. MURALI, and T. SWATHI. "64-Bit ALU Design Using Reversible Gates." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 09, no. 04 (2025): 1–9. https://doi.org/10.55041/ijsrem44380.
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The implementation of reversible gates to build a 64-bit Arithmetic Logic Unit (ALU) is a promising contribution to the area of quantum computing as well as low-power digital circuit design. Reversible logic gates provide the benefit of not losing information throughout the process of computation (unlike traditional irreversible gates), which leads to energy being dissipated less frequently. The purpose of designing reversible logic is to decrease the power consumption and heat dissipation challenges present in modern Very Large Scale Integration (VLSI) design. The 64-bit ALU architecture has shown to improve computational efficiency by decreases in quantum cost, garbage outputs, and constant inputs, giving further credibility to it in the field of advanced computing systems in the future. The goal of this project is to execute arithmetic and logical operations through the use of reversible logic while still decreasing power consumption and delay. The constructed ALU utilizes reversible gates, while implementing reversible gates like a Fredkin gate, Feynman gate, and CNOT gate to implement favorable operations (addition, subtraction, and multiplication) including logical functions (AND, OR, XOR). The intent is to keep the number of garbage outputs and constant inputs to a minimum - garbage outputs and constant inputs are both important parameters of irreversible gates.
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Xiao, Shuying. "Enhancing ASIC chip performance through integrated algorithm optimization." Applied and Computational Engineering 38, no. 1 (2024): 274–79. http://dx.doi.org/10.54254/2755-2721/38/20230563.
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As a crucial arithmetic logic unit, the multiplier plays a significant role in digital signal processing. However, multiplication operations often require a large number of calculations and logic gates, leading to increased circuit complexity and power consumption. To enhance the performance and efficiency of multipliers, this paper presents an optimization analysis based on the Wallace Tree and Booth algorithms. The Wallace Tree algorithm decomposes multiplication operations into multiple stages and employs both separate operations and bit-level parallelism to accelerate multiplication, achieving efficient parallel multiplication computations and reducing both latency and area complexity of multiplication. On the other hand, the Booth algorithm is an optimization method for signed binary multiplication. By introducing the concept of Booth encoding, it transforms signed multiplication into unsigned multiplication, thereby reducing the number of multiplication operations. This paper analyses the application and research progress of the Wallace Tree and Booth algorithms in the field of multiplier optimization to improve computational speed and reduce power consumption of multipliers.
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Brattka, Vasco, Stéphane Le Roux, Joseph S. Miller, and Arno Pauly. "Connected choice and the Brouwer fixed point theorem." Journal of Mathematical Logic 19, no. 01 (2019): 1950004. http://dx.doi.org/10.1142/s0219061319500041.
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We study the computational content of the Brouwer Fixed Point Theorem in the Weihrauch lattice. Connected choice is the operation that finds a point in a non-empty connected closed set given by negative information. One of our main results is that for any fixed dimension the Brouwer Fixed Point Theorem of that dimension is computably equivalent to connected choice of the Euclidean unit cube of the same dimension. Another main result is that connected choice is complete for dimension greater than or equal to two in the sense that it is computably equivalent to Weak Kőnig’s Lemma. While we can present two independent proofs for dimension three and upward that are either based on a simple geometric construction or a combinatorial argument, the proof for dimension two is based on a more involved inverse limit construction. The connected choice operation in dimension one is known to be equivalent to the Intermediate Value Theorem; we prove that this problem is not idempotent in contrast to the case of dimension two and upward. We also prove that Lipschitz continuity with Lipschitz constants strictly larger than one does not simplify finding fixed points. Finally, we prove that finding a connectedness component of a closed subset of the Euclidean unit cube of any dimension greater than or equal to one is equivalent to Weak Kőnig’s Lemma. In order to describe these results, we introduce a representation of closed subsets of the unit cube by trees of rational complexes.
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Miodragovic Vella, Irina, and Sladjana Markovic. "Topological Interlocking Assembly: Introduction to Computational Architecture." Applied Sciences 14, no. 15 (2024): 6409. http://dx.doi.org/10.3390/app14156409.
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Topological interlocking assembly (TIA) and computational architecture treat form as an emergent property of a material system, where the final shape results from the interplay of geometries and geometric interdependencies influenced by contextual constraints (material, structure, and fabrication). This paper posits that TIA is an ideal pedagogical tool for introducing students to computational architecture, and its theoretical foundations and design principles. Specifically, defining TIA as a material system provides a robust educational approach for engaging students with computation; fostering design processes through bottom-up, hands-on investigations; expressing design intents as procedural logic; understanding generative geometric rules; and exploring the flexibility of parametric variations. The methodology is detailed and illustrated through a design workshop and study unit from the Bachelor’s and Master’s programs at the Faculty for the Built Environment, University of Malta. Four case studies of TIA—of tetrahedra, cones, octahedra, and osteomorphic blocks—demonstrate how these exercises introduce students to computational thinking, parametric design, and fabrication techniques. This paper discusses the advantages and limitations of this pedagogical methodology, concluding that integrating computational architecture in education shifts students’ design processes to investigation and innovation-based approaches, enabling them to address contemporary design challenges through context-driven solutions.
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Et.al, Saiful Bahri Hisamudin. "nCODET: A Tool For Novice Developer To Detect Untestable Code." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 3 (2021): 2100–2105. http://dx.doi.org/10.17762/turcomat.v12i3.1151.
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Uncontrollability is troublesome for unit testing. It causes a non-deterministic behavior where the same input can produce different results based on different executions. The non-deterministic characteristic makes it impossible to test the internal logic of a method because it suffers from tight coupling, a single responsibility principle violation, being an untestable code, being non-reusable or hard to maintain. This paper describes a tool, namely the non-deterministic Code Detection Tool (nCODET) that aims to assist novice developers to write testable codes by avoiding the non-deterministic characteristic in their codes. Our research focuses on the unit testability of classes; particularly the effort involvedin constructing unit test cases.
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Harini, G. Iyar, and B. Ramesh K. "Design and Implementation of Quantum-Inspired ALU: A High-Performance Approach." Journal of Advancement in Electronics Design 7, no. 2 (2024): 16–27. https://doi.org/10.5281/zenodo.10996471.
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<em>This paper introduces a Quantum-Inspired Arithmetic Logic Unit (ALU) for high-performance processors, focusing on overcoming classical ALU limitations by leveraging quantum principles. The architectural design meticulously arranges quantum gates, including the Hadamard gate and CNOT gate, within the ALU framework. These gates play vital roles in quantum computation, necessitating precise placement for efficient data processing. Coherence optimization strategies, crucial for stability, ensure accurate quantum gate performance. Quantum parallelism, facilitated by coherence, enhances computational throughput. Quantum data encoding techniques like basis-state and amplitude encoding enable seamless integration of classical data for precise arithmetic and logical operations. Coherence optimization strategies within the ALU mitigate errors and decoherence, ensuring reliable quantum computations. The paper envisions the Quantum-Inspired ALU's potential applications in cryptography, optimization, and artificial intelligence, driving advancements in high-performance processors. By integrating coherence optimization strategies into the ALU design, errors and decoherence are effectively mitigated, resulting in more reliable and accurate quantum computations. These strategies are crucial for achieving the full potential of quantum-inspired computing within the ALU architecture, paving the way for advancements in high-speed computing and quantum technologies.</em>
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Macedo Azevedo da Rosa, Morgana, Rodrigo Lopes, Eduardo Da Costa, and Rafael Soares. "AxRMU-2^m: Higher m-bit Approximate Radix-2^m Multiplier Unit." Journal of Integrated Circuits and Systems 19, no. 3 (2024): 1–12. https://doi.org/10.29292/jics.v19i3.929.
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This paper presents the design and evaluation of higher m-bit Approximate Radix-2^m Multiplier Units (AxRMU) with applications in error-tolerant systems. The AxRMU proposal architectures, specifically AxRMU-8 and AxRMU-16, incorporate approximation in generating partial products, reducing the number of logic gates and improving energy efficiency while maintaining acceptable accuracy. A case study using the statistically efficient and fast calibration (StEFCal) algorithm in radio astronomy demonstrates the performance of the AxRMUs in terms of energy, area savings, and computational accuracy. Results show that AxRMU designs outperform state-of-the-art approximate multipliers like DRUM, LoBA, and RoBA, achieving energy savings of up to 98.30% and area savings of up to 91.57%, with minimal mean square error (MSE) trade-offs. These findings highlight the potential of AxRMUs in balancing performance and resource efficiency for applications that can tolerate minor computational inaccuracies.
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Jujjavarapu, Raj Mouli, and Alwin Poulose. "Verilog Design, Synthesis, and Netlisting of IoT-Based Arithmetic Logic and Compression Unit for 32 nm HVT Cells." Signals 3, no. 3 (2022): 620–41. http://dx.doi.org/10.3390/signals3030038.
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Micro-processor designs have become a revolutionary technology almost in every industry. They brought the reality of automation and also electronic gadgets. While trying to improvise these hardware modules to handle heavy computational loads, they have substantially reached a limit in size, power efficiency, and similar avenues. Due to these constraints, many manufacturers and corporate entities are trying many ways to optimize these mini beasts. One such approach is to design microprocessors based on the specified operating system. This approach came to the limelight when many companies launched their microprocessors. In this paper, we will look into one method of using an arithmetic logic unit (ALU) module for internet of things (IoT)-enabled devices. A specific set of operations is added to the classical ALU to help fast computational processes in IoT-specific programs. We integrated a compression module and a fast multiplier based on the Vedic algorithm in the 16-bit ALU module. The designed ALU module is also synthesized under a 32-nm HVT cell library from the Synopsys database to generate an overview of the areal efficiency, logic levels, and layout of the designed module; it also gives us a netlist from this database. The synthesis provides a complete overview of how the module will be manufactured if sent to a foundry.
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Ou, Qiao-Feng, Bang-Shu Xiong, Lei Yu, Jing Wen, Lei Wang, and Yi Tong. "In-Memory Logic Operations and Neuromorphic Computing in Non-Volatile Random Access Memory." Materials 13, no. 16 (2020): 3532. http://dx.doi.org/10.3390/ma13163532.
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Recent progress in the development of artificial intelligence technologies, aided by deep learning algorithms, has led to an unprecedented revolution in neuromorphic circuits, bringing us ever closer to brain-like computers. However, the vast majority of advanced algorithms still have to run on conventional computers. Thus, their capacities are limited by what is known as the von-Neumann bottleneck, where the central processing unit for data computation and the main memory for data storage are separated. Emerging forms of non-volatile random access memory, such as ferroelectric random access memory, phase-change random access memory, magnetic random access memory, and resistive random access memory, are widely considered to offer the best prospect of circumventing the von-Neumann bottleneck. This is due to their ability to merge storage and computational operations, such as Boolean logic. This paper reviews the most common kinds of non-volatile random access memory and their physical principles, together with their relative pros and cons when compared with conventional CMOS-based circuits (Complementary Metal Oxide Semiconductor). Their potential application to Boolean logic computation is then considered in terms of their working mechanism, circuit design and performance metrics. The paper concludes by envisaging the prospects offered by non-volatile devices for future brain-inspired and neuromorphic computation.
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Alaçam, Sema, Orkan Zeynel Güzelci, Ethem Gürer, and Saadet Zeynep Bacınoğlu. "Reconnoitring computational potentials of the vault-like forms: Thinking aloud on muqarnas tectonics." International Journal of Architectural Computing 15, no. 4 (2017): 285–303. http://dx.doi.org/10.1177/1478077117735019.
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This study sheds light on a holistic understanding of muqarnas with its historical, philosophical and conceptual backgrounds on one hand and formal, structural and algorithmic principles on the other hand. The vault-like Islamic architectural element, muqarnas, is generally considered to be a non-structural decorative element. Various compositional approaches have been proposed to reveal the inner logic of these complex geometric elements. Each of these approaches uses different techniques such as measuring, unit-based decoding or three-dimensional interpretation of two-dimensional patterns. However, the reflections of the inner logic onto different contexts, such as the usage of different initial geometries, materials or performative concerns, were neglected. In this study, we offer a new schema to approach the performative aspects of muqarnas tectonics. This schema contains new sets of elements, properties and relations deriving partly from previous approaches and partly from the technique of folding. Thus, this study first reviews the previous approaches to analyse the geometric and constructional principles of muqarnas. Second, it explains the proposed scheme through a series of algorithmic form-finding experiments. In these experiments, we question whether ‘fold’, as one of the performative techniques of making three-dimensional forms, contributes to the analysis of muqarnas in both a conceptual and computational sense. We argue that encoding vault-like systems via geometric and algorithmic relations based on the logic of the ‘fold’ provides informative and intuitive feedback for form-finding, specifically in the earlier phases of design. While focusing on the performative potential of a specific fold operation, we introduced the concept of bifurcation to describe the generative characteristics of folding technique and the way of subdividing the form with respect to redistribution of the forces. Thus, in this decoding process, the bifurcated fold explains not only to demystify the formal logic of muqarnas but also to generate new forms without losing contextual conditions.
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Ahn, Dong Jun, Keun Sik Kim, Hyun Do Nam, and Eun Woo Shin. "Multi-Channel Active Noise Control System Designs with Fuzzy Logic Stabilized Algorithms." Advanced Engineering Forum 2-3 (December 2011): 96–101. http://dx.doi.org/10.4028/www.scientific.net/aef.2-3.96.
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In active noise control filter, IIR filter structure which used for control filter assures the stability property. The stability characteristics of IIR filter structure is mainly determined by pole location of control filter within unit disc, so stable selection of the value of control filter coefficient is very important. In this paper, we proposed novel adaptive stabilized Filtered_U LMS algorithms with IIR filter structure which has better convergence speed and less computational burden than conventional FIR structures, for multi-channel active noise control with vehicle enclosure signal case. For better convergence speed in adaptive algorithms, fuzzy LMS algorithms where convergence coefficient computed by a fuzzy PI type controller was proposed.
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T, Raju, Pradeep Kumar A, Venkata Thriveni S, Pallavi T, and G. Mani. "Design and Implementation of Hybrid Full Adder-Based Ripple Carry Adder for Low Power Applications." International Journal for Modern Trends in Science and Technology 11, no. 03 (2025): 207–13. https://doi.org/10.5281/zenodo.15093734.
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<em>Full adders are fundamental components in various applications, including Digital Signal Processors (DSPs) and microprocessors. In modern circuit design, reducing supply voltage has become a key approach to minimizing energy consumption. Since the full adder serves as a primary arithmetic unit in many computational tasks, it plays a crucial role in the efficiency of the Arithmetic Logic Unit (ALU). This project introduces novel hybrid full adder designs aimed at achieving low Power-Delay Product (PDP). Additionally, a Ripple Carry Adder (RCA) is proposed using a chain structure to enhance driving strength. The hybrid full adder topologies are implemented to construct a 4-bit RCA based on CMOS technology, optimizing power and performance.</em>
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Skatkov, A. V., D. Y. Voronin, and LA Skatkov. "Features of degradation faults modeling of initial measurers of monitoring systems." Monitoring systems of environment, no. 1 (March 22, 2017): 48–56. http://dx.doi.org/10.33075/2220-5861-2017-1-48-56.
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The features of the modeling of degradation faults of the primary measurers of monitoring systems and networks based on their basis are considered. An integrated approach to modeling invited to perform on the basis of the use and development of analytical relations obtained for queuing systems. For this purpose it has been proposed a new functional logic component – degradator, which is the minimum structural unit of the simulation. The results of computational experiments for the purpose of estimating the degree of influence the degradation rate parameters on the system performance are given in the paper.
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Usharani, M., B. Sakthivel, K. Jayaram, and R. Renugadevi. "Design of Logically Obfuscated Memory and Arithmetic Logic Unit for Improved Hardware Security." Intelligent Automation & Soft Computing 33, no. 3 (2022): 1665–75. http://dx.doi.org/10.32604/iasc.2022.023284.
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Singh, Sarabjeet, Satvir Singh, and Vijay Kumar Banga. "An Interval Type 2 Fuzzy Logic Framework for Faster Evolutionary Design." Journal of Computational and Theoretical Nanoscience 16, no. 12 (2019): 5140–48. http://dx.doi.org/10.1166/jctn.2019.8576.
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In this paper, a fast processing and efficient framework has been proposed to get an optimum output from a noisy data set of a system by using interval type-2 fuzzy logic system. Further, the concept of GPGPU (General Purpose Computing on Graphics Processing Unit) is used for fast execution of the fuzzy rule base on Graphics Processing Unit (GPU). Application of Whale Optimization Algorithm (WOA) is used to ascertain optimum output from noisy data set. Which is further integrated with Interval Type-2 (IT2) fuzzy logic system and executed on Graphics Processing Unit for faster execution. The proposed framework is also designed for parallel execution using GPU and the results are compared with the serial program execution. Further, it is clearly observed that the parallel execution rule base evolved provide better accuracy in less time. The proposed framework (IT2FLS) has been validated with classical bench mark problem of Mackey Glass Time Series. For non-stationary time-series data with additive gaussian noise has been implemented with proposed framework and with T1 FLS. Further, it is observed that IT2 FLS provides better rule base for noisy data set.
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Chukkaluru, Ravi Shankar Reddy, Venkata Gopi Kumar Padavala, Manikandan Radhakrishnan, and Bhavana Kuruva. "A high speed and power efficient multiplier based on counterbased stacking." A high speed and power efficient multiplier based on counterbased stacking 32, no. 1 (2023): 98–106. https://doi.org/10.11591/ijeecs.v32.i1.pp98-106.
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High speed and competent addition of various operands is an essential operation in the design any computational unit. The swiftness and power competence of multiplier circuits plays vital role in enlightening the overall performance of microprocessors. Multipliers play crucial role in the design of arithmetic logic unit (ALU) or any digital signal processor (DSP) that are effectively employed for filtering and convolution operations. The process of multiplication either binary numbers or fixed-point numbers yields in enormous partial products that are to be added to get final product. These partial products in number and the process of summing up partial products dictate the latency and power consumption of the multiplier design. Here, we present a novel binary counter design that hires stacking circuits, that groups all logic “1” bits as one, followed by a novel symmetric method to merge pairs of 3-bit stacks into 6-bit stacks and then changes them to binary counts. This results in drastic improvements in power and area utilization of the multiplier. Additionally, this paper also focuses on implementation of novel approximate compressor and exploits the same for the design of approximate multipliers that can be effectively employed in any electronic systems that are characterized by power and speed constraints.
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Chaves, Luciano Eustáquio, and Luiz Fernando C. Nascimento. "Estimating outcomes in newborn infants using fuzzy logic." Revista Paulista de Pediatria 32, no. 2 (2014): 164–70. http://dx.doi.org/10.1590/0103-058220143228413.
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OBJECTIVE: To build a linguistic model using the properties of fuzzy logic to estimate the risk of death of neonates admitted to a Neonatal Intensive Care Unit.METHODS: Computational model using fuzzy logic. The input variables of the model were birth weight, gestational age, 5th-minute Apgar score and inspired fraction of oxygen in newborn infants admitted to a Neonatal Intensive Care Unit of Taubaté, Southeast Brazil. The output variable was the risk of death, estimated as a percentage. Three membership functions related to birth weight, gestational age and 5th-minute Apgar score were built, as well as two functions related to the inspired fraction of oxygen; the risk presented five membership functions. The model was developed using the Mandani inference by means of Matlab(r) software. The model values were compared with those provided by experts and their performance was estimated by ROC curve.RESULTS: 100 newborns were included, and eight of them died. The model estimated an average possibility of death of 49.7±29.3%, and the possibility of hospital discharge was 24±17.5%. These values are different when compared by Student's t-test (p<0.001). The correlation test revealed r=0.80 and the performance of the model was 81.9%.CONCLUSIONS: This predictive, non-invasive and low cost model showed a good accuracy and can be applied in neonatal care, given the easiness of its use.
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Sajid, Asher, Omar S. Sonbul, Muhammad Rashid, Muhammad Arif, and Amar Y. Jaffar. "An Optimized Hardware Implementation of a Non-Adjacent Form Algorithm Using Radix-4 Multiplier for Binary Edwards Curves." Applied Sciences 14, no. 1 (2023): 54. http://dx.doi.org/10.3390/app14010054.
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Binary Edwards Curves (BEC) play a pivotal role in modern cryptographic processes and applications, offering a combination of robust security as well as computational efficiency. For robust security, this article harnesses the inherent strengths of BEC for the cryptographic point multiplication process by utilizing the Non-Adjacent Form (NAF) algorithm. For computational efficiency, a hardware architecture for the NAF algorithm is proposed. Central to this architecture is an Arithmetic Logic Unit (ALU) designed for streamlined execution of essential operations, including addition, squaring, and multiplication. One notable innovation in our ALU design is the integration of multiplexers, which maximize ALU efficiency with minimal additional hardware requirements. Complementing the optimized ALU, the proposed architecture incorporates a radix-4 multiplier, renowned for its efficiency in both multiplication and reduction. It eliminates resource-intensive divisions, resulting in a substantial boost to overall computational speed. The architecture is implemented on Xilinx Virtex series Field-Programmable Gate Arrays (FPGAs). It achieves throughput-to-area ratios of 14.819 (Virtex-4), 25.5 (Virtex-5), 34.58 (Virtex-6), and 37.07 (Virtex-7). These outcomes underscore the efficacy of our optimizations, emphasizing an equilibrium between computational performance and area utilization.
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Mykhailo, Solomko, Tadeyev Petro, Zubyk Yaroslav, and Hladka Olena. "REDUCTION AND OPTIMAL PERFORMANCE OF ACYCLIC ADDERS OF BINARY CODES." Eastern-European Journal of Enterprise Technologies 1, no. 4 (97) (2019): 40–53. https://doi.org/10.15587/1729-4061.2019.157150.
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The conducted studies have established the prospect of increasing productivity of computing components, in particular, combinational adders, based on applying principles of computation of digital signals of the acyclic model. Application of the acyclic model is designed for: ‒ the process of series (for low-order digits of the adder circuit) and parallel (for the rest of the digits) computation of sum and carry signals. Due to this approach, it is possible, in the end, to reduce complexity of the hardware part of the device and not increase the circuit depth; ‒ setting the optimal number of computational steps. The assumption that the number of computational steps of the directed acyclic graph with two logical operations (AND and XOR) determines optimal number of carry operations in the circuit of the n-bit parallel adder of binary codes was experimentally proved. In particular, this is confirmed by presence of the 8-bit parallel acyclic adder with the circuit depth of 8 standard 2-input logic elements. Connection between the number of computational steps of the acyclic graph and the number of operations of a unit carry to the high-order digit causes the process of comparison of the adder structure with the corresponding acyclic graph. The purpose of this comparison is to set the minimum sufficient number of carry operations for adding binary codes in the circuit of a parallel adder using the parallel carry method. Use of the acyclic model is more advantageous in comparison with counterparts due to the following factors: ‒ less development costs since the acyclic model requires a simpler adder structure; ‒ presence of an optimization criterion, i.e. the number of computational steps of the acyclic graph indicates the minimum sufficient number of operations of a unit carry to the high-order digit. This provides the possibility of obtaining optimum indicators of the adder structure complexity and circuit depth. Compared to counterparts of known 8-bit prefix adder structures, this provides a 14–31% increase in the 8-bit acyclic adder operation quality, e.g. power consumption or chip area depending on the chosen structure, There are grounds to assert possibility of increasing productivity of computing components, in particular, binary code adders applying the principles of computation of digital signals of the acyclic model
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Cheang, Sin Man, Kwong Sak Leung, and Kin Hong Lee. "Genetic Parallel Programming: Design and Implementation." Evolutionary Computation 14, no. 2 (2006): 129–56. http://dx.doi.org/10.1162/evco.2006.14.2.129.
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This paper presents a novel Genetic Parallel Programming (GPP) paradigm for evolving parallel programs running on a Multi-Arithmetic-Logic-Unit (Multi-ALU) Processor (MAP). The MAP is a Multiple Instruction-streams, Multiple Data-streams (MIMD), general-purpose register machine that can be implemented on modern Very Large-Scale Integrated Circuits (VLSIs) in order to evaluate genetic programs at high speed. For human programmers, writing parallel programs is more difficult than writing sequential programs. However, experimental results show that GPP evolves parallel programs with less computational effort than that of their sequential counterparts. It creates a new approach to evolving a feasible problem solution in parallel program form and then serializes it into a sequential programif required. The effectiveness and efficiency of GPP are investigated using a suite of 14 well-studied benchmark problems. Experimental results show that GPP speeds up evolution substantially.
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Shankar Reddy, Chukkaluru Ravi, Padavala Venkata Gopi Kumar, Radhakrishnan Manikandan, and Kuruva Bhavana. "A high speed and power efficient multiplier based on counter-based stacking." Indonesian Journal of Electrical Engineering and Computer Science 32, no. 1 (2023): 98. http://dx.doi.org/10.11591/ijeecs.v32.i1.pp98-106.
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<span>High speed and competent addition of various operands is an essential operation in the design any computational unit. The swiftness and power competence of multiplier circuits plays vital role in enlightening the overall performance of microprocessors. Multipliers play crucial role in the design of <a name="_Hlk140074299"></a>arithmetic logic unit (ALU) or any digital signal processor (DSP) that are effectively employed for filtering and convolution operations. The process of multiplication either binary numbers or fixed-point numbers yields in enormous partial products that are to be added to get final product. These partial products in number and the process of summing up partial products dictate the latency and power consumption of the multiplier design. Here, we present a novel binary counter design that hires stacking circuits, that groups all logic “1” bits as one, followed by a novel symmetric method to merge pairs of 3-bit stacks into 6-bit stacks and then changes them to binary counts. This results in drastic improvements in power and area utilization of the multiplier. Additionally, this paper also focuses on implementation of novel approximate compressor and exploits the same for the design of approximate multipliers that can be effectively employed in any electronic systems that are characterized by power and speed constraints.</span>
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Velasco, Rodrigo, Rubén Hernández, Nicolás Marrugo, and César Díaz. "Notes on the design process of a responsive sun-shading system: A case study of designer and user explorations supported by computational tools." Artificial Intelligence for Engineering Design, Analysis and Manufacturing 29, no. 4 (2015): 483–502. http://dx.doi.org/10.1017/s0890060415000463.
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AbstractResponding to growing concerns regarding energy-efficient facades, this paper describes the structure and process followed in the design of a responsive sun-shading system based on the use of rotating plates with two degrees of freedom. The proposal considers, among others, the definition of variable design parameters, areas of performance evaluation and control, and construction detailing development represented by a first 1:2 unit (module) model. In the process, computational simulation procedures were employed to explore configurational possibilities that would provide high-performance solutions to the light requirements of the particular covered spaces. In developing the system, it was noticed that due to the highly subjective requirements of users in terms of quantity and quality of lighting, a purely Boolean control system would not always be appropriate. Following from that, and taking advantage of the dynamic nature of the system, a further approach of control supported by fuzzy logic was also implemented at the operative state, whose logic is explained. Digital simulations were carried out to assess the performance of the system, and their results demonstrate more even light distribution levels compared to traditional systems.
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Zhu, Ming Xia. "Research on Integration Degree Curve of Asynchronous Microprocessing Based on Virtual Characteristics Computing." Applied Mechanics and Materials 543-547 (March 2014): 3458–61. http://dx.doi.org/10.4028/www.scientific.net/amm.543-547.3458.
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Based on the virtual computing principle of computers feature and compatible MCU logic unit of full asynchronous microprocessor, this paper designs computer simulation platform of ideological and political education. The platform has data mining and analysis module. In order to verify the reliability of the platform, we design the data analysis simulation experiment of ideological and political education. Through the calculation, we can get the MCU integration curve. According to the impact of ideological and political education on users, we use computational analysis module to draw thinking fluctuation curve of political ideological education. We also can get thinking step characteristics of Political and ideological education which has high reference value for the research of the ideological and political education.
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ALVIANO, MARIO, CARMINE DODARO, JOHANNES K. FICHTE, MARKUS HECHER, TOBIAS PHILIPP, and JAKOB RATH. "Inconsistency Proofs for ASP: The ASP - DRUPE Format." Theory and Practice of Logic Programming 19, no. 5-6 (2019): 891–907. http://dx.doi.org/10.1017/s1471068419000255.
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AbstractAnswer Set Programming (ASP) solvers are highly-tuned and complex procedures that implicitly solve the consistency problem, i.e., deciding whether a logic program admits an answer set. Verifying whether a claimed answer set is formally a correct answer set of the program can be decided in polynomial time for (normal) programs. However, it is far from immediate to verify whether a program that is claimed to be inconsistent, indeed does not admit any answer sets. In this paper, we address this problem and develop the new proof format ASP-DRUPE for propositional, disjunctive logic programs, including weight and choice rules. ASP-DRUPE is based on the Reverse Unit Propagation (RUP) format designed for Boolean satisfiability. We establish correctness of ASP-DRUPE and discuss how to integrate it into modern ASP solvers. Later, we provide an implementation of ASP-DRUPE into the wasp solver for normal logic programs.
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Devnath, Bappy Chandra, and Satyendra N. Biswas. "Low Power Full Adder Design Using PTM Transistor Model." Carpathian Journal of Electronic and Computer Engineering 12, no. 2 (2019): 15–20. http://dx.doi.org/10.2478/cjece-2019-0011.
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Abstract At present the processing power of the digital electronic chip is enormous and that has been possible because of the continuous improvement of the design methodology and fabrication technology. So, the data processing capability of the chip is increased significantly. Data processing in the electronic chip means the arithmetic operation on that data. For that reason, ALU is present in any processor. Full adder is one of the critical components of arithmetic unit. Improvement of the full adder is necessary for improving the computational performance of a chip. In order to design an efficient full adder, designer should choose an appropriate logic style. In this research, two new model of full-adder circuits are designed and analyzed using Pass Transistor logic in order to reduce power consumption and increase operational speed. The first proposed adder consists of 8 transistors and the second one consists of 10 transistors. LTSPICE is employed for simulating the proposed circuits using16nm low power high-k strained silicon transistor model. The overall performance of the proposed adder circuits and comparative results demonstrate the superiority of the proposed model.
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Mundici, Daniele. "Ulam Games, Łukasiewicz Logic, and AF C*-Algebras." Fundamenta Informaticae 18, no. 2-4 (1993): 151–61. http://dx.doi.org/10.3233/fi-1993-182-405.
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Ulam asked what is the minimum number of yes-no questions necessary to find an unknown number in the search space (1, …, 2n), if up to l of the answers may be erroneous. The solutions to this problem provide optimal adaptive l error correcting codes. Traditional, nonadaptive l error correcting codes correspond to the particular case when all questions are formulated before all answers. We show that answers in Ulam’s game obey the (l+2)-valued logic of Łukasiewicz. Since approximately finite-dimensional (AF) C*-algebras can be interpreted in the infinite-valued sentential calculus, we discuss the relationship between game-theoretic notions and their C*-algebraic counterparts. We describe the correspondence between continuous trace AF C*-algebras, and Ulam games with separable Boolean search space S. whose questions are the clopen subspaces of S. We also show that these games correspond to finite products of countable Post MV algebras, as well as to countable lattice-ordered Specker groups with strong unit.
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Старолетов, Сергей Михайлович, and Игорь Сергеевич Ануреев. "Towards unit testing of event-driven control requirements." Вычислительные технологии, no. 1 (March 22, 2022): 88–100. http://dx.doi.org/10.25743/ict.2022.27.1.007.
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Тестирование - общепринятый метод контроля качества программного обеспечения, хотя о полной надежности программ при таком подходе говорить не приходится. Тем не менее этот метод очень хорошо интегрируется в среды разработки и применим при непрерывной интеграции. В статье кратко рассмотрены шаблоны поведения, которые ранее разработаны для логического описания операций программируемых логических контроллеров (ПЛК) с использованием табличных свойств. Представлена схема ограниченного алгоритма проверки модели для контроля выполнимости этих свойств. Описано, как реализовать термы и формулы, составляющие модели поведения программ ПЛК, на объектно-ориентированном языке программирования. После того как была проведена абстракция значений входов и выходов управляющих переменных системы на основе подхода “черного ящика”, показано, насколько удобно описывать требования в форме наших экземпляров классов. Это описание позволяет интегрировать процесс проверки требований ПЛК-программ в процесс модульного тестирования. Testing is a generally accepted method to control software quality, although it is not completely reliable. Nevertheless, this method integrates extremely well into development environments and continuous integration practices. In this paper, we briefly review the behavioral patterns that we have previously developed for the logical description of the programmable logic controllers (PLC) operations using tabular properties. We also present a diagram for the checking algorithm of a bounded model to investigate the feasibility of such properties. We describe how to implement the terms and formulas that provide the behavior patterns of PLC programs in an object-oriented programming language (C++ in this case). After the black box assessment for the values of the control variables for inputs and outputs of the system has been set, we show how convenient it is to describe the requirements in the form of our instantiated classes. This description allows integrating the unit testing process for the checking requirements of the PLC programs.
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Santoro, Giulia, Giovanna Turvani, and Mariagrazia Graziano. "New Logic-In-Memory Paradigms: An Architectural and Technological Perspective." Micromachines 10, no. 6 (2019): 368. http://dx.doi.org/10.3390/mi10060368.
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Processing systems are in continuous evolution thanks to the constant technological advancement and architectural progress. Over the years, computing systems have become more and more powerful, providing support for applications, such as Machine Learning, that require high computational power. However, the growing complexity of modern computing units and applications has had a strong impact on power consumption. In addition, the memory plays a key role on the overall power consumption of the system, especially when considering data-intensive applications. These applications, in fact, require a lot of data movement between the memory and the computing unit. The consequence is twofold: Memory accesses are expensive in terms of energy and a lot of time is wasted in accessing the memory, rather than processing, because of the performance gap that exists between memories and processing units. This gap is known as the memory wall or the von Neumann bottleneck and is due to the different rate of progress between complementary metal–oxide semiconductor (CMOS) technology and memories. However, CMOS scaling is also reaching a limit where it would not be possible to make further progress. This work addresses all these problems from an architectural and technological point of view by: (1) Proposing a novel Configurable Logic-in-Memory Architecture that exploits the in-memory computing paradigm to reduce the memory wall problem while also providing high performance thanks to its flexibility and parallelism; (2) exploring a non-CMOS technology as possible candidate technology for the Logic-in-Memory paradigm.
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V.P, Visanthi. "FULL ADDER CIRCUIT DESIGN WITH LOW POWER AND HIGH SPEED AT 0.25µM CMOS TECHNOLOGY USING TANNER EDA." International Journal Of Trendy Research In Engineering And Technology 07, no. 01 (2023): 46–48. http://dx.doi.org/10.54473/ijtret.2023.7109.
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A CMOS Full Adder is designed using Tanner EDA Tool based on 0.25µm CMOS Technology. In the arithmetic logic unit (ALU), the full adder cell is one of the most frequently utilized digital circuit components and the fundamental functional unit of all computational circuits. Right now, a lot of work has been done to improve the architecture and functionality of full adder circuit designs. In this research, two innovative 1-bit full adder cell designs are developed using ten transistors and 0.25mm CMOS technology (10-T). Tanner software tools will be used in the design of the CMOS full adder to simulate the schematic and layout as well as compare the schematic and layout for the purpose of determining precise design limitations. As part of this, we are going to perform the simulation of the CMOS full adder using T-SPICE of Tanner EDA and its layout design using the Microwind tool. The parameters such as power consumption, Area, Propagation Delay, and Power Delay Product (PDP) are evaluated to analyze the proposed one-bit full adder
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Brucal, Stanley Glenn E., Aaron Don M. Africa, and Luigi Carlo M. de Jesus. "Optimizing Air Conditioning Unit Power Consumption in an Educational Building: A Rough Set Theory and Fuzzy Logic-Based Approach." Applied System Innovation 8, no. 2 (2025): 32. https://doi.org/10.3390/asi8020032.
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Split air conditioning units are crucial for ensuring the thermal comfort of buildings. Conventional scheduling or pre-timed system activities result in high consumption and wasted energy. This study proposes an intelligent control system for automatic setpoint adjustment in an educational building based on real-time indoor and outdoor environmental and room occupancy data. Principal component analysis was used to identify energy consumption components in ramp-up and steady-state power usage scenarios. K-means clustering was then used to categorize environmental scenarios and occupancy patterns to identify operational states, predict power consumption and environmental variables, and generate fuzzy inference system rules. The application of rough set theory eliminated rule redundancy by at least 99.27% and enhanced computational speed by 96.40%. After testing using real historical data from an uncontrolled environment and occupant thermal comfort satisfaction surveys reflecting a range of ACU setpoints, the enhanced inference system achieved daily average power savings of 25.56% and a steady-state power period at 63.24% of the ACU operating time, as compared to conventional and variable setpoint operations. The proposed technique provides a basis for dynamic and data-driven decision-making, enabling sustainable energy management in smart building applications.
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Da Silva, Rafael, Pedro T. L. Pereira, Mateus Grellert, and Ricardo Reis. "Energy-Efficient Interpolation Filter Design for VVC Encoders Using Cross-Layer Approximate Computing." Journal of Integrated Circuits and Systems 19, no. 3 (2024): 1–11. https://doi.org/10.29292/jics.v19i3.908.
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Recent advancements in video encoding have enabled significant compression rates but at the expense of increased power consumption and computational demands. This trade-off has driven the need for dedicated accelerators capable of leveraging the parallelism inherent in computationally intensive encoding tasks, particularly through customized hardware solutions. In this work, we introduce a hardware accelerator specifically designed for Fractional Motion Estimation (FME), a key component in video encoding. Our approach leverages cross-layer approximate computing to bridge the gap between logic (arithmetic blocks), architecture, and software layers. The proposed architecture, named 4TAxA, employs an interpolation filter that supports various configurations of approximate adders. Synthesis results using ST 65nm technology demonstrate that the 4TAxA filter core achieves power savings of 69.20% to 90.64% and area reductions of 50.13% to 72.59%, compared to a precise implementation with equivalent throughput. Considering a complete FME unit and a fair or better image quality threshold, our method delivers up to 60.8% power savings and 28% area savings. We expect that our contributions help designers by enabling energy- and quality-efficient encoding systems, offering a promising direction for future cross-layer approximate computing strategies.
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Ishtiaq, Saima, Xiangrong Wang, Shahid Hassan, Alsharef Mohammad, Ahmad Aziz Alahmadi, and Nasim Ullah. "Three-Dimensional Multi-Target Tracking Using Dual-Orthogonal Baseline Interferometric Radar." Sensors 22, no. 19 (2022): 7549. http://dx.doi.org/10.3390/s22197549.
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Multi-target tracking (MTT) generally needs either a Doppler radar network with spatially separated receivers or a single radar equipped with costly phased array antennas. However, Doppler radar networks have high computational complexity, attributed to the multiple receivers in the network. Moreover, array signal processing techniques for phased array radar also increase the computational burden on the processing unit. To resolve this issue, this paper investigates the problem of the detection and tracking of multiple targets in a three-dimensional (3D) Cartesian space based on range and 3D velocity measurements extracted from dual-orthogonal baseline interferometric radar. The contribution of this paper is twofold. First, a nonlinear 3D velocity measurement function, defining the relationship between the state of the target and 3D velocity measurements, is derived. Based on this measurement function, the design of the proposed algorithm includes the global nearest neighbor (GNN) technique for data association, an interacting multiple model estimator with a square-root cubature Kalman filter (IMM-SCKF) for state estimation, and a rule-based M/N logic for track management. Second, Monte Carlo simulation results for different multi-target scenarios are presented to demonstrate the performance of the algorithm in terms of track accuracy, computational complexity, and IMM mean model probabilities.
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Mendes, Teófilo Paiva Guimarães, Ana Mafalda Ribeiro, Leizer Schnitman, and Idelfonso B. R. Nogueira. "A PLC-Embedded Implementation of a Modified Takagi–Sugeno–Kang-Based MPC to Control a Pressure Swing Adsorption Process." Processes 12, no. 8 (2024): 1738. http://dx.doi.org/10.3390/pr12081738.
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The paper presents a case study that applies a model predictive control (MPC) approach in a Micro850 programmable logic controller (PLC) to a laboratory pressure swing adsorption (PSA) process used for separating gas mixtures of CO2 and CH4. PLC is an industrial hardware characterized by its robustness to hazardous environments and limited computational capacities, which poses computational challenges for MPC implementation. This paper’s main contribution is the application of the modified Takagi–Sugeno–Kang-based MPC (MTSK-MPC) algorithm to this PSA unit, which provides features to investigate and implement feasible MPC designs in PLCs. The investigation consists of a sensitivity analysis of how some design parameters influence the PLC memory and the MPC implementation and a comparative evaluation of the computational processing from different MPC algorithms and simulations. The comparison comprises software-in-the-loop simulations with three algorithms in the PC: an implicit MPC, an explicit MPC, and the MTSK-MPC. Additionally, it includes a hardware-in-the-loop simulation with the implemented MTSK-MPC in Micro850. The results show that the MPC algorithms achieve close performance, tracking setpoint changes and rejecting output disturbances, with the MTSK-MPC presenting the lower processing time among the MPCs in the PC. The study concludes that the implementation of MTSK-MPC in the Micro850 is feasible.
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INCLEZAN, DANIELA, and MICHAEL GELFOND. "Modular action language." Theory and Practice of Logic Programming 16, no. 2 (2015): 189–235. http://dx.doi.org/10.1017/s1471068415000095.
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AbstractThe paper introduces a new modular action language,${\mathcal ALM}$, and illustrates the methodology of its use. It is based on the approach of Gelfond and Lifschitz (1993,Journal of Logic Programming 17, 2–4, 301–321; 1998,Electronic Transactions on AI 3, 16, 193–210) in which a high-level action language is used as a front end for a logic programming system description. The resulting logic programming representation is used to perform various computational tasks. The methodology based on existing action languages works well for small and even medium size systems, but is not meant to deal with larger systems that requirestructuring of knowledge.$\mathcal{ALM}$is meant to remedy this problem. Structuring of knowledge in${\mathcal ALM}$is supported by the concepts ofmodule(a formal description of a specific piece of knowledge packaged as a unit),module hierarchy, andlibrary, and by the division of a system description of${\mathcal ALM}$into two parts:theoryandstructure. Atheoryconsists of one or more modules with a common theme, possibly organized into a module hierarchy based on adependency relation. It contains declarations of sorts, attributes, and properties of the domain together with axioms describing them.Structuresare used to describe the domain's objects. These features, together with the means for defining classes of a domain as special cases of previously defined ones, facilitate the stepwise development, testing, and readability of a knowledge base, as well as the creation of knowledge representation libraries.
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ROSENBLUETH, DAVID A. "Chain programs for writing deterministic metainterpreters." Theory and Practice of Logic Programming 2, no. 2 (2002): 203–32. http://dx.doi.org/10.1017/s147106840100134x.
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Many metainterpreters found in the logic programming literature are nondeterministic in the sense that the selection of program clauses is not determined. Examples are the familiar ‘demo’ and ‘vanilla’ metainterpreters. For some applications this nondeterminism is convenient. In some cases, however, a deterministic metainterpreter, having an explicit selection of clauses, is needed. Such cases include (1) conversion of OR parallelism into AND parallelism for ‘committed-choice’ processors, (2) logic-based, imperative-language implementation of search strategies, and (3) simulation of bounded-resource reasoning. Deterministic metainterpreters are difficult to write because the programmer must be concerned about the set of unifiers of the children of a node in the derivation tree. We argue that it is both possible and advantageous to write these metainterpreters by reasoning in terms of object programs converted into a syntactically restricted form that we call ‘chain’ form, where we can forget about unification, except for unit clauses. We give two transformations converting logic programs into chain form, one for ‘moded’ programs (implicit in two existing exhaustive-traversal methods for committed-choice execution), and one for arbitrary definite programs. As illustrations of our approach we show examples of the three applications mentioned above.