Relevant bibliographies by topics / Computer architecture; branch prediction

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Computer architecture; branch prediction'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "Computer architecture; branch prediction"

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Jin, Wenbing, Feng Shi, Qiugui Song, and Yang Zhang. "A novel architecture for ahead branch prediction." Frontiers of Computer Science 7, no. 6 (September 20, 2013): 914–23. http://dx.doi.org/10.1007/s11704-013-2260-x.

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Lorenzo, Javier, Ignacio Parra Alonso, Rubén Izquierdo, Augusto Luis Ballardini, Álvaro Hernández Saz, David Fernández Llorca, and Miguel Ángel Sotelo. "CAPformer: Pedestrian Crossing Action Prediction Using Transformer." Sensors 21, no. 17 (August 24, 2021): 5694. http://dx.doi.org/10.3390/s21175694.

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Anticipating pedestrian crossing behavior in urban scenarios is a challenging task for autonomous vehicles. Early this year, a benchmark comprising JAAD and PIE datasets have been released. In the benchmark, several state-of-the-art methods have been ranked. However, most of the ranked temporal models rely on recurrent architectures. In our case, we propose, as far as we are concerned, the first self-attention alternative, based on transformer architecture, which has had enormous success in natural language processing (NLP) and recently in computer vision. Our architecture is composed of various branches which fuse video and kinematic data. The video branch is based on two possible architectures: RubiksNet and TimeSformer. The kinematic branch is based on different configurations of transformer encoder. Several experiments have been performed mainly focusing on pre-processing input data, highlighting problems with two kinematic data sources: pose keypoints and ego-vehicle speed. Our proposed model results are comparable to PCPA, the best performing model in the benchmark reaching an F1 Score of nearly 0.78 against 0.77. Furthermore, by using only bounding box coordinates and image data, our model surpasses PCPA by a larger margin (F1=0.75 vs. F1=0.72). Our model has proven to be a valid alternative to recurrent architectures, providing advantages such as parallelization and whole sequence processing, learning relationships between samples not possible with recurrent architectures.
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Misev, Anastas, and Marjan Gusev. "Simulators for courses in advance computer architecture." Facta universitatis - series: Electronics and Energetics 18, no. 2 (2005): 237–52. http://dx.doi.org/10.2298/fuee0502237m.

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The usage of simulator in teaching computer architecture courses has proven to be the most acceptable way, especially when the simulators offer rich graphical and visual representation of the architecture. In this paper we present several simulators used to teach ILP (Instruction Level of Parallelism) courses. The simulators cover wide area of concepts such as internal logic organization, datapath, control, memory behavior, register renaming, branch prediction, and overall out of order execution. Special dedicated simulators cover details in internal organization like Tomasulo approach and scoreboard for organization of reservation stations. This innovative approach in laboratory exercises is used for advanced ILP course.
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Chang, M. C., and Y. W. Chou. "Branch prediction using both global and local branch history information." IEE Proceedings - Computers and Digital Techniques 149, no. 2 (2002): 33. http://dx.doi.org/10.1049/ip-cdt:20020273.

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Xie, Zi-Chao, Dong Tong, Ming-Kai Huang, Qin-Qing Shi, and Xu Cheng. "SWIP Prediction: Complexity-Effective Indirect-Branch Prediction Using Pointers." Journal of Computer Science and Technology 27, no. 4 (July 2012): 754–68. http://dx.doi.org/10.1007/s11390-012-1262-8.

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Kwak, Jong Wook, and Chu Shik Jhon. "Dynamic per-branch history length adjustment to improve branch prediction accuracy." Microprocessors and Microsystems 31, no. 1 (February 2007): 63–76. http://dx.doi.org/10.1016/j.micpro.2006.08.002.

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Lee, S., I. C. Park, and C. M. Kyung. "Path-based branch prediction using signature analysis." Microprocessors and Microsystems 23, no. 8-9 (December 1999): 527–36. http://dx.doi.org/10.1016/s0141-9331(99)00056-3.

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Chiu, J. C., R. M. Shiu, S. A. Chi, and C. P. Chung. "Instruction cache prefetching directed by branch prediction." IEE Proceedings - Computers and Digital Techniques 146, no. 5 (1999): 241. http://dx.doi.org/10.1049/ip-cdt:19990310.

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Parikh, D., K. Skadron, Yan Zhang, and M. Stan. "Power-aware branch prediction: characterization and design." IEEE Transactions on Computers 53, no. 2 (February 2004): 168–86. http://dx.doi.org/10.1109/tc.2004.1261827.

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Bhattacharya, Sarani, Clementine Maurice, Shivam Bhasin, and Debdeep Mukhopadhyay. "Branch Prediction Attack on Blinded Scalar Multiplication." IEEE Transactions on Computers 69, no. 5 (May 1, 2020): 633–48. http://dx.doi.org/10.1109/tc.2019.2958611.

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Dissertations / Theses on the topic "Computer architecture; branch prediction"

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GAO, HONGLIANG. "IMPROVING BRANCH PREDICTION ACCURACY VIA EFFECTIVE SOURCE INFORMATION AND PREDICTION ALGORITHMS." Doctoral diss., University of Central Florida, 2008. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3286.

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Modern superscalar processors rely on branch predictors to sustain a high instruction fetch throughput. Given the trend of deep pipelines and large instruction windows, a branch misprediction will incur a large performance penalty and result in a significant amount of energy wasted by the instructions along wrong paths. With their critical role in high performance processors, there has been extensive research on branch predictors to improve the prediction accuracy. Conceptually a dynamic branch prediction scheme includes three major components: a source, an information processor, and a predictor. Traditional works mainly focus on the algorithm for the predictor. In this dissertation, besides novel prediction algorithms, we investigate other components and develop untraditional ways to improve the prediction accuracy. First, we propose an adaptive information processing method to dynamically extract the most effective inputs to maximize the correlation to be exploited by the predictor. Second, we propose a new prediction algorithm, which improves the Prediction by Partial Matching (PPM) algorithm by selectively combining multiple partial matches. The PPM algorithm was previously considered optimal and has been used to derive the upper limit of branch prediction accuracy. Our proposed algorithm achieves higher prediction accuracy than PPM and can be implemented in realistic hardware budget. Third, we discover a new locality existing between the address of producer loads and the outcomes of their consumer branches. We study this address-branch correlation in detail and propose a branch predictor to explore this correlation for long-latency and hard-to-predict branches, which existing branch predictors fail to predict accurately.
Ph.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Computer Science PhD
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Lind, Tobias. "Evaluation of Instruction Prefetch Methods for Coresonic DSP Processor." Thesis, Linköpings universitet, Datorteknik, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-129128.

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With increasing demands on mobile communication transfer rates the circuits in mobile phones must be designed for higher performance while maintaining low power consumption for increased battery life. One possible way to improve an existing architecture is to implement instruction prefetching. By predicting which instructions will be executed ahead of time the instructions can be prefetched from memory to increase performance and some instructions which will be executed again shortly can be stored temporarily to avoid fetching them from the memory multiple times. By creating a trace driven simulator the existing hardware can be simulated while running a realistic scenario. Different methods of instruction prefetch can be implemented into this simulator to measure how they perform. It is shown that the execution time can be reduced by up to five percent and the amount of memory accesses can be reduced by up to 25 percent with a simple loop buffer and return stack. The execution time can be reduced even further with the more complex methods such as branch target prediction and branch condition prediction.
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Zlatohlávková, Lucie. "Návrh a implementace prostředků pro zvýšení výkonu procesoru." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2007. http://www.nusl.cz/ntk/nusl-412764.

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This masters thesis is focused on the issue of processor architecture. The ground of this project is a design of a simple processor, which is enriched by modern components in processor architecture such as pipelining, cache memory and branch prediction. The processor has been made in VHDL programming language and was simulated in ModelSim simulation tool.
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Egan, Colin. "Dynamic branch prediction in high performance superscalar processors." Thesis, University of Hertfordshire, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.340035.

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Alovisi, Pietro. "Static Branch Prediction through Representation Learning." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-277923.

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In the context of compilers, branch probability prediction deals with estimating the probability of a branch to be taken in a program. In the absence of profiling information, compilers rely on statically estimated branch probabilities, and state of the art branch probability predictors are based on heuristics. Recent machine learning approaches learn directly from source code using natural language processing algorithms. A representation learning word embedding algorithm is built and evaluated to predict branch probabilities on LLVM’s intermediate representation (IR) language. The predictor is trained and tested on SPEC’s CPU 2006 benchmark and compared to state-of-the art branch probability heuristics. The predictor obtains a better miss rate and accuracy in branch prediction than all the evaluated heuristics, but produces and average null performance speedup over LLVM’s branch predictor on the benchmark. This investigation shows that it is possible to predict branch probabilities using representation learning, but more effort must be put in obtaining a predictor with practical advantages over the heuristics.
Med avseende på kompilatorer, handlar branch probability prediction om att uppskatta sannolikheten att en viss förgrening kommer tas i ett program. Med avsaknad av profileringsinformation förlitar sig kompilatorer på statiskt upp- skattade branch probabilities och de främsta branch probability predictors är baserade på heuristiker. Den senaste maskininlärningsalgoritmerna lär sig direkt från källkod genom algoritmer för natural language processing. En algoritm baserad på representation learning word embedding byggs och utvärderas för branch probabilities prediction på LLVM’s intermediate language (IR). Förutsägaren är tränad och testad på SPEC’s CPU 2006 riktmärke och jämförd med de främsta branch probability heuristikerna. Förutsägaren erhåller en bättre frekvens av missar och träffsäkerhet i sin branch prediction har jämförts med alla utvärderade heuristiker, men producerar i genomsnitt ingen prestandaförbättring jämfört med LLVM’s branch predictor på riktmärket. Den här undersökningen visar att det är möjligt att förutsäga branch prediction probabilities med användande av representation learning, men att det behöver satsas mer på att få tag på en förutsägare som har praktiska övertag gentemot heuristiken.
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Jiménez, Daniel Angel. "Delay-sensitive branch predictors for future technologies." Full text (PDF) from UMI/Dissertation Abstracts International, 2002. http://wwwlib.umi.com/cr/utexas/fullcit?p3081043.

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Carver, Jason W. "Architecture of a prediction economy." Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/45807.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.
Includes bibliographical references.
A design and implementation of a Prediction Economy is presented and compared to alternative designs. A Prediction Economy is composed of prediction markets, market managers, information brokers and automated trading agents. Two important goals of a Prediction Economy are to improve liquidity and information dispersal. Market managers automatically open and close appropriate markets, quickly giving traders access to the latest claims. Information brokers deliver parsed data to the trading agents. The agents execute trades on markets that might not otherwise have much trading action. Some preliminary results from a running Prediction Economy are presented, with binary markets based on football plays during a college football game. The most accurate agent chose to enter 8 of 32 markets, and was able to predict 7 of the 8 football play attempts correctly. Source code for the newly implemented tools is available, as are references to the existing open source tools used.
by Jason W. Carver.
M.Eng.
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Tarlescu, Maria-Dana. "The Elastic History Buffer, a multi-hybrid branch prediction scheme using static classification." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape7/PQDD_0025/MQ50893.pdf.

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Thankappan, Achary Retnamma Renjith. "Broadcast Mechanism for improving Conditional Branch Prediction in Speculative Multithreaded Processors." PDXScholar, 2010. https://pdxscholar.library.pdx.edu/open_access_etds/368.

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ABSTRACT Many aspects of speculative multithreading have been under constant and crucial research in the recent times with the increased importance in exploiting parallelism in single thread applications. One of the important architectural optimizations that is very pertinent in this scenario is branch prediction. Branch Prediction assumes increased importance for multi-threading systems that execute threads speculatively, since wrong predictions can be much costlier here, in terms of threads, than a few instructions that occupy the pipeline in a uni-processor. Conventional branch prediction techniques have provided increasingly better prediction accuracies for uni-core processing. But the branch prediction itself takes on a whole new dimension when applied to multi-core architectures based on Speculative Multithreading. Dependence on global branch history has helped branch predictors to achieve high prediction accuracy in single thread applications. The discontinuity of global history created at the thread boundaries cripple the performance of branch predictors in a multi-threaded environment. Many studies in the past have tried to address the branch history problem to improve the prediction accuracy. Most of these have been found either to be architecture specific or complex in terms of the hardware needed to recreate or approximate the right history to be given to the threads when they start executing out of order. This hardware overhead increases as the number and size of threads increase thereby limiting the scalability of the algorithms proposed so far. The current thesis takes a different direction and proposes a simple and scalable solution to effectively reduce the misprediction rates in Speculative Multithreaded systems. This is accomplished by making use of a synergistic interaction between threads to boost the inherent biased nature of branches and using less complex hardware to reduce aliasing between branches in the threads. The study proposes a new scheme called the Global Broadcast Buffer scheme to effectively reduce branch mispredictions in Speculative Multithreaded architectures.
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Jothi, Komal. "Dynamic Task Prediction for an SpMT Architecture Based on Control Independence." PDXScholar, 2009. https://pdxscholar.library.pdx.edu/open_access_etds/1707.

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Exploiting better performance from computer programs translates to finding more instructions to execute in parallel. Since most general purpose programs are written in an imperatively sequential manner, closely lying instructions are always data dependent, making the designer look far ahead into the program for parallelism. This necessitates wider superscalar processors with larger instruction windows. But superscalars suffer from three key limitations, their inability to scale, sequential fetch bottleneck and high branch misprediction penalty. Recent studies indicate that current superscalars have reached the end of the road and designers will have to look for newer ideas to build computer processors. Speculative Multithreading (SpMT) is one of the most recent techniques to exploit parallelism from applications. Most SpMT architectures partition a sequential program into multiple threads (or tasks) that can be concurrently executed on multiple processing units. It is desirable that these tasks are sufficiently distant from each other so as to facilitate parallelism. It is also desirable that these tasks are control independent of each other so that execution of a future task is guaranteed in case of local control flow misspeculations. Some task prediction mechanisms rely on the compiler requiring recompilation of programs. Current dynamic mechanisms either rely on program constructs like loop iterations and function and loop boundaries, resulting in unbalanced loads, or predict tasks which are too short to be of use in an SpMT architecture. This thesis is the first proposal of a predictor that dynamically predicts control independent tasks that are consistently wide apart, and executes them on a novel SpMT architecture.
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Books on the topic "Computer architecture; branch prediction"

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Branch strategy taxonomy and performance models. Los Alamitos, CA: IEEE Computer Society Press, 1992.

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ACM Special Interest Group on Design Automation., IEEE Computer Society. Technical Committee on VLSI., and Philips Natuurkundig Laboratorium, eds. 2001 International Workshop on System-Level Interconnect Prediction: Sonoma, California, USA March 31-April 1, 2001. New York, N.Y: ACM, 2001.

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Sun, Xian-He. Performance prediction: A case study using a multi-ring KSR-1 machine. Hampton, VA: Institute for Computer Applications in Science and Engineering, NASA Langley Research Center, 1995.

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Branch strategy taxonomy and performance models. dont know, 2000.

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Performance prediction: A case study using a multi-ring KSR-1 machine. Hampton, VA: Institute for Computer Applications in Science and Engineering, NASA Langley Research Center, 1995.

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W, Stoughton John, Mielke Roland R, and Langley Research Center, eds. Strategies for concurrent processing of complex algorithms in data driven architectures. Hampton, Va: National Aeronautics and Space Administration, Langley Research Center, 1990.

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Book chapters on the topic "Computer architecture; branch prediction"

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Chung, Sung Woo, and Kevin Skadron. "Using Branch Prediction Information for Near-Optimal I-Cache Leakage." In Advances in Computer Systems Architecture, 24–37. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11859802_4.

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Desmet, Veerle, Lieven Eeckhout, and Koen De Bosschere. "Using Decision Trees to Improve Program-Based and Profile-Based Static Branch Prediction." In Advances in Computer Systems Architecture, 336–52. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11572961_27.

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Vintan, Lucian, Arpad Gellert, Adrian Florea, Marius Oancea, and Colin Egan. "Understanding Prediction Limits Through Unbiased Branches." In Advances in Computer Systems Architecture, 480–87. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11859802_47.

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Chung, Sung Woo, and Sung Bae Park. "A Low Power Branch Predictor to Selectively Access the BTB." In Advances in Computer Systems Architecture, 374–84. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30102-8_32.

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Zhang, Tan, Chaobing Zhou, Libo Huang, Nong Xiao, and Sheng Ma. "Improving Branch Prediction for Thread Migration on Multi-core Architectures." In Lecture Notes in Computer Science, 87–99. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-68210-5_8.

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He, Liqiang, and Guangyong Zhang. "Parallel Branch Prediction on GPU Platform." In Lecture Notes in Computer Science, 153–60. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-11842-5_20.

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Acıiçmez, Onur, Çetin Kaya Koç, and Jean-Pierre Seifert. "Predicting Secret Keys Via Branch Prediction." In Lecture Notes in Computer Science, 225–42. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11967668_15.

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Yang, Chia-Lin, Shun-Ying Wang, and Yi-Jung Chen. "Branch Behavior Characterization for Multimedia Applications." In Advances in Computer Systems Architecture, 523–30. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11859802_53.

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Santana, Oliverio J., Ayose Falcón, Enrique Fernández, Pedro Medina, Alex Ramírez, and Mateo Valero. "A Comprehensive Analysis of Indirect Branch Prediction." In Lecture Notes in Computer Science, 133–45. Berlin, Heidelberg: Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-47847-7_13.

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Veidenbaum, Alexander V. "Instruction cache prefetching using multilevel branch prediction." In Lecture Notes in Computer Science, 51–70. Berlin, Heidelberg: Springer Berlin Heidelberg, 1997. http://dx.doi.org/10.1007/bfb0024203.

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Conference papers on the topic "Computer architecture; branch prediction"

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Farooq, M. U., K. Khubaib, and L. K. John. "Store-Load-Branch (SLB) predictor: A compiler assisted branch prediction for data dependent branches." In 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA). IEEE, 2013. http://dx.doi.org/10.1109/hpca.2013.6522307.

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Bonanno, J., A. Collura, D. Lipetz, U. Mayer, B. Prasky, and A. Saporito. "Two level bulk preload branch prediction." In 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA). IEEE, 2013. http://dx.doi.org/10.1109/hpca.2013.6522308.

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Quinones, Eduardo, Joan-Manuel Parcerisa, and Antonio Gonzailez. "Improving Branch Prediction and Predicated Execution in Out-of-Order Processors." In 2007 IEEE 13th International Symposium on High Performance Computer Architecture. IEEE, 2007. http://dx.doi.org/10.1109/hpca.2007.346186.

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Vougioukas, Ilias, Nikos Nikoleris, Andreas Sandberg, Stephan Diestelhorst, Bashir M. Al-Hashimi, and Geoff V. Merrett. "BRB: Mitigating Branch Predictor Side-Channels." In 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 2019. http://dx.doi.org/10.1109/hpca.2019.00058.

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Vijayn, Balaji, and Dmitry V. Ponomarev. "Accurate and Low-Overhead Dynamic Detection and Prediction of Program Phases Using Branch Signatures." In 2008 20th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD). IEEE, 2008. http://dx.doi.org/10.1109/sbac-pad.2008.23.

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Seznec, Andre. "Storage free confidence estimation for the TAGE branch predictor." In 2011 IEEE 17th International Symposium on High Performance Computer Architecture (HPCA). IEEE, 2011. http://dx.doi.org/10.1109/hpca.2011.5749750.

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Ravale, Priya P., and Sulabha S. Apte. "Design of a branch prediction unit of a microprocessor based on superscalar architecture using VLSI." In 2010 2nd International Conference on Computer Engineering and Technology. IEEE, 2010. http://dx.doi.org/10.1109/iccet.2010.5485221.

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Adiga, Narasimha, James Bonanno, Adam Collura, Matthias Heizmann, Brian R. Prasky, and Anthony Saporito. "The IBM z15 High Frequency Mainframe Branch Predictor Industrial Product." In 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA). IEEE, 2020. http://dx.doi.org/10.1109/isca45697.2020.00014.

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Mirbagher Ajorpaz, Samira, Elba Garza, Sangam Jindal, and Daniel A. Jimenez. "Exploring Predictive Replacement Policies for Instruction Cache and Branch Target Buffer." In 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA). IEEE, 2018. http://dx.doi.org/10.1109/isca.2018.00050.

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Dankanikote, Pavithra, Jin Hwan Park, and Yul Chu. "Branch Prediction and Power Reduction Techniques in the Clustered Loop Buffer VLIW Architecture." In 2007 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing. IEEE, 2007. http://dx.doi.org/10.1109/pacrim.2007.4313192.

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