Log in

Relevant bibliographies by topics / Computer architecture; branch prediction / Journal articles

To see the other types of publications on this topic, follow the link: Computer architecture; branch prediction.

Journal articles on the topic 'Computer architecture; branch prediction'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'Computer architecture; branch prediction.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

Jin, Wenbing, Feng Shi, Qiugui Song, and Yang Zhang. "A novel architecture for ahead branch prediction." Frontiers of Computer Science 7, no. 6 (September 20, 2013): 914–23. http://dx.doi.org/10.1007/s11704-013-2260-x.

Full text

APA, Harvard, Vancouver, ISO, and other styles

2

Lorenzo, Javier, Ignacio Parra Alonso, Rubén Izquierdo, Augusto Luis Ballardini, Álvaro Hernández Saz, David Fernández Llorca, and Miguel Ángel Sotelo. "CAPformer: Pedestrian Crossing Action Prediction Using Transformer." Sensors 21, no. 17 (August 24, 2021): 5694. http://dx.doi.org/10.3390/s21175694.

Full text

Abstract:

Anticipating pedestrian crossing behavior in urban scenarios is a challenging task for autonomous vehicles. Early this year, a benchmark comprising JAAD and PIE datasets have been released. In the benchmark, several state-of-the-art methods have been ranked. However, most of the ranked temporal models rely on recurrent architectures. In our case, we propose, as far as we are concerned, the first self-attention alternative, based on transformer architecture, which has had enormous success in natural language processing (NLP) and recently in computer vision. Our architecture is composed of various branches which fuse video and kinematic data. The video branch is based on two possible architectures: RubiksNet and TimeSformer. The kinematic branch is based on different configurations of transformer encoder. Several experiments have been performed mainly focusing on pre-processing input data, highlighting problems with two kinematic data sources: pose keypoints and ego-vehicle speed. Our proposed model results are comparable to PCPA, the best performing model in the benchmark reaching an F1 Score of nearly 0.78 against 0.77. Furthermore, by using only bounding box coordinates and image data, our model surpasses PCPA by a larger margin (F1=0.75 vs. F1=0.72). Our model has proven to be a valid alternative to recurrent architectures, providing advantages such as parallelization and whole sequence processing, learning relationships between samples not possible with recurrent architectures.

APA, Harvard, Vancouver, ISO, and other styles

3

Misev, Anastas, and Marjan Gusev. "Simulators for courses in advance computer architecture." Facta universitatis - series: Electronics and Energetics 18, no. 2 (2005): 237–52. http://dx.doi.org/10.2298/fuee0502237m.

Full text

Abstract:

The usage of simulator in teaching computer architecture courses has proven to be the most acceptable way, especially when the simulators offer rich graphical and visual representation of the architecture. In this paper we present several simulators used to teach ILP (Instruction Level of Parallelism) courses. The simulators cover wide area of concepts such as internal logic organization, datapath, control, memory behavior, register renaming, branch prediction, and overall out of order execution. Special dedicated simulators cover details in internal organization like Tomasulo approach and scoreboard for organization of reservation stations. This innovative approach in laboratory exercises is used for advanced ILP course.

APA, Harvard, Vancouver, ISO, and other styles

4

Chang, M. C., and Y. W. Chou. "Branch prediction using both global and local branch history information." IEE Proceedings - Computers and Digital Techniques 149, no. 2 (2002): 33. http://dx.doi.org/10.1049/ip-cdt:20020273.

Full text

APA, Harvard, Vancouver, ISO, and other styles

5

Xie, Zi-Chao, Dong Tong, Ming-Kai Huang, Qin-Qing Shi, and Xu Cheng. "SWIP Prediction: Complexity-Effective Indirect-Branch Prediction Using Pointers." Journal of Computer Science and Technology 27, no. 4 (July 2012): 754–68. http://dx.doi.org/10.1007/s11390-012-1262-8.

Full text

APA, Harvard, Vancouver, ISO, and other styles

6

Kwak, Jong Wook, and Chu Shik Jhon. "Dynamic per-branch history length adjustment to improve branch prediction accuracy." Microprocessors and Microsystems 31, no. 1 (February 2007): 63–76. http://dx.doi.org/10.1016/j.micpro.2006.08.002.

Full text

APA, Harvard, Vancouver, ISO, and other styles

7

Lee, S., I. C. Park, and C. M. Kyung. "Path-based branch prediction using signature analysis." Microprocessors and Microsystems 23, no. 8-9 (December 1999): 527–36. http://dx.doi.org/10.1016/s0141-9331(99)00056-3.

Full text

APA, Harvard, Vancouver, ISO, and other styles

8

Chiu, J. C., R. M. Shiu, S. A. Chi, and C. P. Chung. "Instruction cache prefetching directed by branch prediction." IEE Proceedings - Computers and Digital Techniques 146, no. 5 (1999): 241. http://dx.doi.org/10.1049/ip-cdt:19990310.

Full text

APA, Harvard, Vancouver, ISO, and other styles

9

Parikh, D., K. Skadron, Yan Zhang, and M. Stan. "Power-aware branch prediction: characterization and design." IEEE Transactions on Computers 53, no. 2 (February 2004): 168–86. http://dx.doi.org/10.1109/tc.2004.1261827.

Full text

APA, Harvard, Vancouver, ISO, and other styles

10

Bhattacharya, Sarani, Clementine Maurice, Shivam Bhasin, and Debdeep Mukhopadhyay. "Branch Prediction Attack on Blinded Scalar Multiplication." IEEE Transactions on Computers 69, no. 5 (May 1, 2020): 633–48. http://dx.doi.org/10.1109/tc.2019.2958611.

Full text

APA, Harvard, Vancouver, ISO, and other styles

11

KWAK, J. W. "The Impact of Branch Direction History Combined with Global Branch History in Branch Prediction." IEICE Transactions on Information and Systems E88-D, no. 7 (July 1, 2005): 1754–58. http://dx.doi.org/10.1093/ietisy/e88-d.7.1754.

Full text

APA, Harvard, Vancouver, ISO, and other styles

12

Li, Tao, Lizy Kurian John, Anand Sivasubramaniam, N. Vijaykrishnan, and Juan Rubio. "OS-Aware Branch Prediction: Improving Microprocessor Control Flow Prediction for Operating Systems." IEEE Transactions on Computers 56, no. 1 (January 2007): 2–17. http://dx.doi.org/10.1109/tc.2007.250619.

Full text

APA, Harvard, Vancouver, ISO, and other styles

13

Mohammadi, Milad, Song Han, Ehsan Atoofian, Amirali Baniasadi, Tor M. Aamodt, and William J. Dally. "Energy Efficient On-Demand Dynamic Branch Prediction Models." IEEE Transactions on Computers 69, no. 3 (March 1, 2020): 453–65. http://dx.doi.org/10.1109/tc.2019.2956710.

Full text

APA, Harvard, Vancouver, ISO, and other styles

14

Choi, Min, Jong Hyuk Park, Seungho Lim, and Young-Sik Jeong. "Achieving reliable system performance by fast recovery of branch miss prediction." Journal of Network and Computer Applications 35, no. 3 (May 2012): 982–91. http://dx.doi.org/10.1016/j.jnca.2011.03.015.

Full text

APA, Harvard, Vancouver, ISO, and other styles

15

Gao, Xiao Peng, and Ping Yang Guo. "PPSim: A Cycle-Accurate Simulator for PowerPC Instruction Set." Applied Mechanics and Materials 325-326 (June 2013): 1766–69. http://dx.doi.org/10.4028/www.scientific.net/amm.325-326.1766.

Full text

Abstract:

Simulators play an important part in computer architecture research. As for specific microarchitecture study, which focuses on the accurate behavior of out-of-order scheduling, ALU contention, and function unit management, an over-simplified abstraction is not sufficient to represent modern processor organizations. Thus cycle-accurate simulators are introduced to describe the accurate behavior in target microarchitecture. In cycle-accurate simulators, the timing feature within function units is simulated. This paper presents PPSim, a cycle-accurate PowerPC instruction set simulator, which models the cache, branch prediction, and out of order pipeline in PowerPC microarchitecture.

APA, Harvard, Vancouver, ISO, and other styles

16

Yi Ma, Hongliang Gao, and Huiyang Zhou. "Using indexing functions to reduce conflict aliasing in branch prediction tables." IEEE Transactions on Computers 55, no. 8 (August 2006): 1057–61. http://dx.doi.org/10.1109/tc.2006.133.

Full text

APA, Harvard, Vancouver, ISO, and other styles

17

Haris, Malik, and Adam Glowacz. "Lane Line Detection Based on Object Feature Distillation." Electronics 10, no. 9 (May 8, 2021): 1102. http://dx.doi.org/10.3390/electronics10091102.

Full text

Abstract:

In order to meet the real-time requirements of the autonomous driving system, the existing method directly up-samples the encoder’s output feature map to pixel-wise prediction, thus neglecting the importance of the decoder for the prediction of detail features. In order to solve this problem, this paper proposes a general lane detection framework based on object feature distillation. Firstly, a decoder with strong feature prediction ability is added to the network using direct up-sampling method. Then, in the network training stage, the prediction results generated by the decoder are regarded as soft targets through knowledge distillation technology, so that the directly up-samples branch can learn more detailed lane information and have a strong feature prediction ability for the decoder. Finally, in the stage of network inference, we only need to use the direct up-sampling branch instead of the forward calculation of the decoder, so compared with the existing model, it can improve the lane detection performance without additional cost. In order to verify the effectiveness of this framework, it is applied to many mainstream lane segmentation methods such as SCNN, DeepLabv1, ResNet, etc. Experimental results show that, under the condition of no additional complexity, the proposed method can obtain higher F1Measure on CuLane dataset.

APA, Harvard, Vancouver, ISO, and other styles

18

Xu, Yingda, and Jianming Wei. "Deep Feature Fusion Based Dual Branch Network for X-ray Security Inspection Image Classification." Applied Sciences 11, no. 16 (August 14, 2021): 7485. http://dx.doi.org/10.3390/app11167485.

Full text

Abstract:

Automatic computer security inspection of X-ray scanned images has an irresistible trend in modern life. Aiming to address the inconvenience of recognizing small-sized prohibited item objects, and the potential class imbalance within multi-label object classification of X-ray scanned images, this paper proposes a deep feature fusion model-based dual branch network architecture. Firstly, deep feature fusion is a method to fuse features extracted from several model layers. Specifically, it operates these features by upsampling and dimension reduction to match identical sizes, then fuses them by element-wise sum. In addition, this paper introduces focal loss to handle class imbalance. For balancing importance on samples of minority and majority class, it assigns weights to class predictions. Additionally, for distinguishing difficult samples from easy samples, it introduces modulating factor. Dual branch network adopts the two components above and integrates them in final loss calculation through the weighted sum. Experimental results illustrate that the proposed method outperforms baseline and state-of-art by a large margin on various positive/negative ratios of datasets. These demonstrate the competitivity of the proposed method in classification performance and its potential application under actual circumstances.

APA, Harvard, Vancouver, ISO, and other styles

19

Sendag, R., J. J. Yi, and Peng-fei Chuang. "Branch Misprediction Prediction: Complementary Branch Predictors." IEEE Computer Architecture Letters 6, no. 2 (February 2007): 49–52. http://dx.doi.org/10.1109/l-ca.2007.13.

Full text

APA, Harvard, Vancouver, ISO, and other styles

20

Falcon, Ayose, Oliverio J. Santana, Alex Ramirez, and Mateo Valero. "A latency-conscious SMT branch prediction architecture." International Journal of High Performance Computing and Networking 2, no. 1 (2004): 11. http://dx.doi.org/10.1504/ijhpcn.2004.009264.

Full text

APA, Harvard, Vancouver, ISO, and other styles

21

Mohammadi, Milad, Song Han, Tor M. Aamodt, and William J. Dally. "On-Demand Dynamic Branch Prediction." IEEE Computer Architecture Letters 14, no. 1 (January 1, 2015): 50–53. http://dx.doi.org/10.1109/lca.2014.2330820.

Full text

APA, Harvard, Vancouver, ISO, and other styles

22

Stark, Jared, Marius Evers, and Yale N. Patt. "Variable length path branch prediction." ACM SIGOPS Operating Systems Review 32, no. 5 (December 1998): 170–79. http://dx.doi.org/10.1145/384265.291042.

Full text

APA, Harvard, Vancouver, ISO, and other styles

23

Jiménez, Daniel A. "Generalizing neural branch prediction." ACM Transactions on Architecture and Code Optimization 5, no. 4 (March 2009): 1–27. http://dx.doi.org/10.1145/1498690.1498692.

Full text

APA, Harvard, Vancouver, ISO, and other styles

24

Young, Cliff, and Michael D. Smith. "Improving the accuracy of static branch prediction using branch correlation." ACM SIGOPS Operating Systems Review 28, no. 5 (December 1994): 232–41. http://dx.doi.org/10.1145/381792.195549.

Full text

APA, Harvard, Vancouver, ISO, and other styles

25

Choi, Bumyong, Leo Porter, and Dean M. Tullsen. "Accurate branch prediction for short threads." ACM SIGOPS Operating Systems Review 42, no. 2 (March 25, 2008): 125–34. http://dx.doi.org/10.1145/1353535.1346298.

Full text

APA, Harvard, Vancouver, ISO, and other styles

26

Silc, Jurij, Theo Ungerer, and Borut Robic. "Dynamic branch prediction and control speculation." International Journal of High Performance Systems Architecture 1, no. 1 (2007): 2. http://dx.doi.org/10.1504/ijhpsa.2007.013287.

Full text

APA, Harvard, Vancouver, ISO, and other styles

27

Ball, Thomas, and James R. Larus. "Branch prediction for free." ACM SIGPLAN Notices 28, no. 6 (June 1993): 300–313. http://dx.doi.org/10.1145/173262.155119.

Full text

APA, Harvard, Vancouver, ISO, and other styles

28

Chen, I.-Cheng K., John T. Coffey, and Trevor N. Mudge. "Analysis of branch prediction via data compression." ACM SIGOPS Operating Systems Review 30, no. 5 (December 1996): 128–37. http://dx.doi.org/10.1145/248208.237171.

Full text

APA, Harvard, Vancouver, ISO, and other styles

29

Calder, Brad, Dirk Grunwald, Donald Lindsay, James Martin, Michael Mozer, and Benjamin Zorn. "Corpus-based static branch prediction." ACM SIGPLAN Notices 30, no. 6 (June 1995): 79–92. http://dx.doi.org/10.1145/223428.207118.

Full text

APA, Harvard, Vancouver, ISO, and other styles

30

Stark, Jared, Marius Evers, and Yale N. Patt. "Variable length path branch prediction." ACM SIGPLAN Notices 33, no. 11 (November 1998): 170–79. http://dx.doi.org/10.1145/291006.291042.

Full text

APA, Harvard, Vancouver, ISO, and other styles

31

Wong, W. F. "Source Level Static Branch Prediction." Computer Journal 42, no. 2 (February 1, 1999): 142–49. http://dx.doi.org/10.1093/comjnl/42.2.142.

Full text

APA, Harvard, Vancouver, ISO, and other styles

32

Egan, Colin, Gordon Steven, Patrick Quick, Rubén Anguera, Fleur Steven, and Lucian Vintan. "Two-level branch prediction using neural networks." Journal of Systems Architecture 49, no. 12-15 (December 2003): 557–70. http://dx.doi.org/10.1016/s1383-7621(03)00095-x.

Full text

APA, Harvard, Vancouver, ISO, and other styles

33

Pan, Shien-Tai, Kimming So, and Joseph T. Rahmeh. "Improving the accuracy of dynamic branch prediction using branch correlation." ACM SIGPLAN Notices 27, no. 9 (September 1992): 76–84. http://dx.doi.org/10.1145/143371.143490.

Full text

APA, Harvard, Vancouver, ISO, and other styles

34

Young, Cliff, and Michael D. Smith. "Improving the accuracy of static branch prediction using branch correlation." ACM SIGPLAN Notices 29, no. 11 (November 1994): 232–41. http://dx.doi.org/10.1145/195470.195549.

Full text

APA, Harvard, Vancouver, ISO, and other styles

35

Choi, Bumyong, Leo Porter, and Dean M. Tullsen. "Accurate branch prediction for short threads." ACM SIGPLAN Notices 43, no. 3 (March 25, 2008): 125–34. http://dx.doi.org/10.1145/1353536.1346298.

Full text

APA, Harvard, Vancouver, ISO, and other styles

36

SMEDA, ADEL, MOURAD OUSSALAH, and TAHAR KHAMMACI. "MY ARCHITECTURE: A KNOWLEDGE REPRESENTATION META-MODEL FOR SOFTWARE ARCHITECTURE." International Journal of Software Engineering and Knowledge Engineering 18, no. 07 (November 2008): 877–94. http://dx.doi.org/10.1142/s0218194008003921.

Full text

Abstract:

In this article we show how knowledge representation techniques can be applied to software architecture. We define a representation model for software architecture concepts. The model is based on MY model (meta modeling in Y), which is a knowledge engineering methodology. It represents software architecture concepts using three branches: component, connector, and architecture. The component branch represents concepts that are related to computations, the connector branch represents concepts that are related to interactions, and the architecture branch represents concepts that are related to the structure and the topology of the system described. We think that such a representation of architecture concepts aids in improving reusability not only at the implementation level, but also at the description level. The model assigns a hierarchical library for the four software architecture conceptual levels (meta-meta architecture level, meta architecture level, architecture level, application level).

APA, Harvard, Vancouver, ISO, and other styles

37

Abramov, E. M. "IMPLEMENTATION OF THE BRANCH PREDICTION SCHEMES FOR THE MICROPROCESSOR OF RISC-V ARCHITECTURE." Issues of radio electronics, no. 8 (August 20, 2018): 49–55. http://dx.doi.org/10.21778/2218-5453-2018-8-49-55.

Full text

Abstract:

One of the limiting factors for increasing the performance of CPU computation pipeline is the pipelining of control transfer instructions. This article provides a review of the problems of raising the instruction pipeline efficiency while executing the branch instructions, by the example of microarchitecture with the implementation of open RISC-V ISA. It gives a description of the various methods of resolving the control hazards. Implementations of the various static and dynamic branch prediction methods, as well as the scheme of calculating a jump address, has been provided. For the dynamic schemes this article gives an estimate of the dependency of prediction accuracy from the size of the branch history tables. Also, it contains the results of synthesis, which allow to estimate the hardware cost of the implementation of given schemes. It has been discovered that the presence of dynamic branch prediction module at the computation pipeline is helping to raise the efficiency of pipeline processing.

APA, Harvard, Vancouver, ISO, and other styles

38

Falcon, A., J. Stark, A. Ramirez, Konrad Lai, and M. Valero. "Better Branch Prediction Through Prophet/Critic Hybrids." IEEE Micro 25, no. 1 (January 2005): 80–89. http://dx.doi.org/10.1109/mm.2005.5.

Full text

APA, Harvard, Vancouver, ISO, and other styles

39

Chen, I.-Cheng K., John T. Coffey, and Trevor N. Mudge. "Analysis of branch prediction via data compression." ACM SIGPLAN Notices 31, no. 9 (September 1996): 128–37. http://dx.doi.org/10.1145/248209.237171.

Full text

APA, Harvard, Vancouver, ISO, and other styles

40

Lee, Yongsuk, and Gyungho Lee. "Detecting Code Reuse Attacks with Branch Prediction." Computer 51, no. 4 (April 2018): 40–47. http://dx.doi.org/10.1109/mc.2018.2141035.

Full text

APA, Harvard, Vancouver, ISO, and other styles

41

Qiu, Keni, Mengying Zhao, Chun Jason Xue, and Alex Orailoglu. "Branch Prediction-Directed Dynamic Instruction Cache Locking for Embedded Systems." ACM Transactions on Embedded Computing Systems 13, no. 5s (December 15, 2014): 1–24. http://dx.doi.org/10.1145/2660492.

Full text

APA, Harvard, Vancouver, ISO, and other styles

42

Sanchez, Ernesto, and Matteo Sonza Reorda. "On the Functional Test of Branch Prediction Units." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23, no. 9 (September 2015): 1675–88. http://dx.doi.org/10.1109/tvlsi.2014.2356612.

Full text

APA, Harvard, Vancouver, ISO, and other styles

43

Jiménez, Daniel A. "Code placement for improving dynamic branch prediction accuracy." ACM SIGPLAN Notices 40, no. 6 (June 12, 2005): 107–16. http://dx.doi.org/10.1145/1064978.1065025.

Full text

APA, Harvard, Vancouver, ISO, and other styles

44

Krall, Andreas. "Improving semi-static branch prediction by code replication." ACM SIGPLAN Notices 29, no. 6 (June 1994): 97–106. http://dx.doi.org/10.1145/773473.178252.

Full text

APA, Harvard, Vancouver, ISO, and other styles

45

Patterson, Jason R. C. "Accurate static branch prediction by value range propagation." ACM SIGPLAN Notices 30, no. 6 (June 1995): 67–78. http://dx.doi.org/10.1145/223428.207117.

Full text

APA, Harvard, Vancouver, ISO, and other styles

46

Tarjan, David, and Kevin Skadron. "Merging path and gshare indexing in perceptron branch prediction." ACM Transactions on Architecture and Code Optimization 2, no. 3 (September 2005): 280–300. http://dx.doi.org/10.1145/1089008.1089011.

Full text

APA, Harvard, Vancouver, ISO, and other styles

47

Biggar, Paul, Nicholas Nash, Kevin Williams, and David Gregg. "An experimental study of sorting and branch prediction." ACM Journal of Experimental Algorithmics 12 (June 2008): 1–39. http://dx.doi.org/10.1145/1227161.1370599.

Full text

APA, Harvard, Vancouver, ISO, and other styles

48

Fan, Hehe, Linchao Zhu, and Yi Yang. "Cubic LSTMs for Video Prediction." Proceedings of the AAAI Conference on Artificial Intelligence 33 (July 17, 2019): 8263–70. http://dx.doi.org/10.1609/aaai.v33i01.33018263.

Full text

Abstract:

Predicting future frames in videos has become a promising direction of research for both computer vision and robot learning communities. The core of this problem involves moving object capture and future motion prediction. While object capture specifies which objects are moving in videos, motion prediction describes their future dynamics. Motivated by this analysis, we propose a Cubic Long Short-Term Memory (CubicLSTM) unit for video prediction. CubicLSTM consists of three branches, i.e., a spatial branch for capturing moving objects, a temporal branch for processing motions, and an output branch for combining the first two branches to generate predicted frames. Stacking multiple CubicLSTM units along the spatial branch and output branch, and then evolving along the temporal branch can form a cubic recurrent neural network (CubicRNN). Experiment shows that CubicRNN produces more accurate video predictions than prior methods on both synthetic and real-world datasets.

APA, Harvard, Vancouver, ISO, and other styles

49

Mittal, Sparsh. "A survey of techniques for dynamic branch prediction." Concurrency and Computation: Practice and Experience 31, no. 1 (September 2, 2018): e4666. http://dx.doi.org/10.1002/cpe.4666.

Full text

APA, Harvard, Vancouver, ISO, and other styles

50

Ye, Ji Hua, Qi Xie, and Yao Hong Xiahou. "Simulation and Implementation of HLA-Based Branch Predictor of Multi-Pipeline Processor." Applied Mechanics and Materials 204-208 (October 2012): 4952–57. http://dx.doi.org/10.4028/www.scientific.net/amm.204-208.4952.

Full text

Abstract:

Researched how the multi-pipeline processor accelerates the running of thread ,found that when the branch predictor facing the random branch instruction, the hit rate will become very low, so bring out a new method that using the free pipeline to accelerate the running of branch instruction. If the right prediction from branch predictor is less than 70% and there is a free pipeline, then using two pipelines to run the two sides of a branch instruction at the same time. In order to test the new method, the HLA (High Level architecture) architecture-based simulation system is established, the results show that the new method can really reduce the time when processing the random branch instructions.

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!