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Books on the topic 'Computer architecture. Cache memory'

Author: Grafiati

Published: 4 June 2021

Last updated: 2 February 2022

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1

Balasubramonian, Rajeev. Multi-core cache hierarchies. San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA): Morgan & Claypool, 2011.

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2

Analysis of cache performance for operating systems and multiprogramming. Boston: Kluwer Academic Publishers, 1989.

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3

Machinery, Association for Computing, and IEEE Computer Society, eds. ASPLOS-VII proceedings: Seventh International Conference on Architectural Support for Programming Languages and Operating Systems, Cambridge, Massachusetts, October 1-5, 1996. New York: Association for Computing Machinery, 1996.

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4

William, Stallings. Computer organization and architecture: Designing for performance. 7th ed. Upper Saddle River, NJ: Pearson Prentice Hall, 2006.

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5

William, Stallings. Computer organization and architecture: Designing for performance. 6th ed. Upper Saddle River, NJ: Pearson Education, 2003.

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6

William, Stallings. Computer organization and architecture: Designing for performance. 4th ed. London: Prentice-Hall International (UK), 1996.

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7

William, Stallings. Computer organization and architecture: Designing for performance. 6th ed. Upper Saddle River, N.J: Prentice Hall Pearson Education International, 2003.

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8

William, Stallings. Computer organization and architecture: Designing for performance. 5th ed. Upper Saddle River, N.J: Prentice Hall, 2000.

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9

William, Stallings. Computer organization and architecture: Designing for performance. 4th ed. Upper Saddle River, N.J: Prentice Hall, 1996.

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10

William, Stallings. Computer organization and architecture: Principles of structure and function. New York: Macmillan, 1987.

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11

William, Stallings. Computer organization and architecture: Principles of structure and function. 2nd ed. New York: Macmillan, 1990.

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12

William, Stallings, and William Stallings. Computer organization and architecture: Principles of structure and function. 3rd ed. New York: Macmillan, 1993.

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13

Handy, Jim. The cache memory book. Boston: Academic Press, 1993.

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14

The cache memory book. 2nd ed. San Diego: Academic Press, 1998.

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15

Jacob, Bruce. Memory systems: Cache, DRAM, disk. Burlington, MA: Morgan Kaufmann Publishers, 2008.

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16

Sorin, Daniel J. A primer on memory consistency and cache coherence. San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA): Morgan & Claypool, 2011.

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17

Nicol, David. Massively parallel algorithms for trace-driven cache simulations. Hampton, Va: National Aeronautics and Space Administration, Langley Research Center, 1991.

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18

Przybylski, Steven A. Cache and memory hierarchy design: A performance-directed approach. San Mateo, Calif: Morgan Kaufmann Publishers, 1990.

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19

Tartalja, Igor. The cache coherence problem in shared-memory multiprocessors: Software solutions. Los Alamitos, Calif: IEEE Computer Society Press, 1996.

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20

Gössel, Michael. Memory architecture & parallel access. Amsterdam: Elsevier, 1994.

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21

ElAarag, Hala. Web Proxy Cache Replacement Strategies: Simulation, Implementation, and Performance Evaluation. London: Springer London, 2013.

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22

Tick, Evan. Memory performance of prolog architectures. Boston: Kluwer Academic Publishers, 1988.

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23

Squid: The definitive guide. Sebastopol, CA: O'Reilly & Associates, Inc., 2004.

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24

Mastering DynaCache in WebSphere commerce. [United States]: International Business Machines Corporation, 2006.

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25

Grun, Peter. Memory architecture exploration for programmable embedded systems. Boston: Kluwer Academic Publishers, 2003.

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26

Grun, Peter. Memory architecture exploration for programmable embedded systems. Boston: Kluwer Academic Publishers, 2003.

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27

Grun, Peter. Memory architecture exploration for programmable embedded systems. Boston, MA: Kluwer Academic Publishers, 2002.

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28

Corporation, International Business Machines. Program directory for remote spooling communications subsystem (RSCS) networking for z/VM: Function level 540, program number 5741-A05 for use with z/VM version 5 release 4. [Endicott, NY]: IBM, 2008.

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29

Web caching. Sebastopol, CA: O'Reilly & Associates, 2001.

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30

Memory storage patterns in parallel processing. Boston: Kluwer Academic, 1987.

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31

Programmed visions: Software and memory. Cambridge, Mass: MIT Press, 2011.

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32

Oualha, Nouha. Peer-to-peer storage: Security and protocols. New York: Nova Science Publishers, 2010.

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33

Client data caching: A foundation for high performance object database systems. Boston: Kluwer Academic Publishers, 1996.

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34

Dufrasne, Bertrand. IBM XIV Storage System: Concepts, architecture, and usage. 2nd ed. [Poughkeepse, NY]: IBM, International Technical Support Organization, 2009.

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35

Corporation, International Business Machines, ed. IBM XIV Storage System: Concepts, architecture, and usage. Poughkeepsie, NY: IBM, 2009.

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36

Sharing bandwidth. Foster City, CA: IDG Books Worldwide, 1998.

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37

Standley, Hilda M. Computer architecture evaluation for structural dynamics computations: Final technial report, project summary. Toledo, Ohio: Dept. of Computer Science, University of Toledo, 1989.

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38

International Symposium on Computer Architecture (26th 1999 Atlanta, Ga.). Proceedings of the 26th International Symposium on Computer Architecture: May 2-4, 1999, Atlanta, Georgia. Los Alamitos, Calif: IEEE Computer Society, 1999.

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39

Hennessy, John L. Computer Organization and Design: The Hardware/Software Interface. San Mateo, Calif: Morgan Kaufmann, 1994.

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40

Hennessy, John L. Computer organization and design: The hardware/software interface. San Mateo, Calif: Morgan Kaufmann, 1994.

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41

Hennessy, John L. Computer organization and design: The hardware/software interface. San Francisco: Morgan Kaufmann Publishers, 1994.

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42

Baram, Yoram. Ground-state coding in partially connected neural networks. Moffett Field, Calif: National Aeronautics and Space Administration, Ames Research Center, 1989.

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43

Baram, Yoram. Ground-state coding in partially connected neural networks. Moffett Field, Calif: National Aeronautics and Space Administration, Ames Research Center, 1989.

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44

1953-, Dubois Michel, and Thakkar S. S, eds. Cache and interconnect architectures in multiprocessors. Boston: Kluwer Academic Publishers, 1990.

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45

Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann, 2007.

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46

inc, Motorola, ed. MC88200 cache/memory management unit user's manual. 2nd ed. Englewood Cliffs, N.J: Prentice Hall, 1990.

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47

Motorola, ed. MC88200 cache/memory management unit user's manual. 2nd ed. Englewood Cliffs: Prentice Hall, 1990.

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48

Cache-based error recovery for shared memory multiprocessor systems. Urbana, Ill: University of Illinois at Urbana-Champaign, 1988.

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49

Cache-based error recovery for shared memory multiprocessor systems. Urbana, Ill: University of Illinois at Urbana-Champaign, 1988.

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50

Sorin, Daniel J., Vijay Nagarajan, and Mark D. Hill. Primer on Memory Consistency and Cache Coherence: Second Edition. Morgan & Claypool Publishers, 2020.

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