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Relevant bibliographies by topics / Computer architecture. Real-time data processing. Embedded computer systems Field programmable gate arrays

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Journal articles
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Academic literature on the topic 'Computer architecture. Real-time data processing. Embedded computer systems Field programmable gate arrays'

Author: Grafiati

Published: 4 June 2021

Last updated: 14 February 2022

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Journal articles on the topic "Computer architecture. Real-time data processing. Embedded computer systems Field programmable gate arrays"

1

Ramadurgam, Srikanth, and Darshika G. Perera. "An Efficient FPGA-Based Hardware Accelerator for Convex Optimization-Based SVM Classifier for Machine Learning on Embedded Platforms." Electronics 10, no. 11 (2021): 1323. http://dx.doi.org/10.3390/electronics10111323.

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Machine learning is becoming the cornerstones of smart and autonomous systems. Machine learning algorithms can be categorized into supervised learning (classification) and unsupervised learning (clustering). Among many classification algorithms, the Support Vector Machine (SVM) classifier is one of the most commonly used machine learning algorithms. By incorporating convex optimization techniques into the SVM classifier, we can further enhance the accuracy and classification process of the SVM by finding the optimal solution. Many machine learning algorithms, including SVM classification, are

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Tan, H., M. Walby, W. Hennig, et al. "A Digital Signal Processing Module for Time-Division Multiplexed Microcalorimeter Arrays." Applied Superconductivity, IEEE Transactions on 23, no. 3 (2013): 2500305. http://dx.doi.org/10.1109/tasc.2012.2236632.

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We have developed a digital signal processing module for real time processing of time-division multiplexed data from SQUID-coupled transition-edge sensor microcalorimeter arrays. It is a 3U PXI card consisting of a standardized core processor board and a daughter board. Through fiber-optic links on its front panel, the daughter board receives time-division multiplexed data (comprising error and feedback signals) and clocks from the digital-feedback cards developed at the National Institute of Standards and Technology. After mixing the error signal with the feedback signal in a field-programmab

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3

Frikha, Tarek, Faten Chaabane, Nadhir Aouinti, Omar Cheikhrouhou, Nader Ben Amor, and Abdelfateh Kerrouche. "Implementation of Blockchain Consensus Algorithm on Embedded Architecture." Security and Communication Networks 2021 (April 23, 2021): 1–11. http://dx.doi.org/10.1155/2021/9918697.

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The adoption of Internet of Things (IoT) technology across many applications, such as autonomous systems, communication, and healthcare, is driving the market’s growth at a positive rate. The emergence of advanced data analytics techniques such as blockchain for connected IoT devices has the potential to reduce the cost and increase in cloud platform adoption. Blockchain is a key technology for real-time IoT applications providing trust in distributed robotic systems running on embedded hardware without the need for certification authorities. There are many challenges in blockchain IoT applica

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Pérez, Ignacio, and Miguel Figueroa. "A Heterogeneous Hardware Accelerator for Image Classification in Embedded Systems." Sensors 21, no. 8 (2021): 2637. http://dx.doi.org/10.3390/s21082637.

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Convolutional neural networks (CNN) have been extensively employed for image classification due to their high accuracy. However, inference is a computationally-intensive process that often requires hardware acceleration to operate in real time. For mobile devices, the power consumption of graphics processors (GPUs) is frequently prohibitive, and field-programmable gate arrays (FPGA) become a solution to perform inference at high speed. Although previous works have implemented CNN inference on FPGAs, their high utilization of on-chip memory and arithmetic resources complicate their application

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Oh, Hyun Woo, Ji Kwang Kim, Gwan Beom Hwang, and Seung Eun Lee. "The Design of a 2D Graphics Accelerator for Embedded Systems." Electronics 10, no. 4 (2021): 469. http://dx.doi.org/10.3390/electronics10040469.

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Recently, advances in technology have enabled embedded systems to be adopted for a variety of applications. Some of these applications require real-time 2D graphics processing running on limited design specifications such as low power consumption and a small area. In order to satisfy such conditions, including a specific 2D graphics accelerator in the embedded system is an effective method. This method reduces the workload of the processor in the embedded system by exploiting the accelerator. The accelerator assists the system to perform 2D graphics processing in real-time. Therefore, a variet

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Blaiech, Ahmed Ghazi, Khaled Ben Khalifa, Mohamed Boubaker, Mohamed Akil, and Mohamed Hedi Bedoui. "Integration of Optimization Approach Based on Multiple Wordlength Operation Grouping in the AAA Methodology for Real-Time Systems." International Journal of Embedded and Real-Time Communication Systems 5, no. 1 (2014): 37–60. http://dx.doi.org/10.4018/ijertcs.2014010103.

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The Multiple-Wordlength Operation Grouping (MWOG) is a recently used approach for an optimized implementation on a Field Programmable Gate Array (FPGA). By fixing the precision constraint, this approach allows minimizing the data wordlength. In this paper, the authors present the integration of the approach based on the MWOG in the Algorithm Architecture Adequation (AAA) methodology, designed to implement real-time applications onto reconfigurable circuits. This new AAA-MWOG methodology will improve the optimization phase of the AAA methodology by taking into account the data wordlength and cr

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Vandendriessche, Jurgen, Bruno da Silva, Lancelot Lhoest, An Braeken, and Abdellah Touhafi. "M3-AC: A Multi-Mode Multithread SoC FPGA Based Acoustic Camera." Electronics 10, no. 3 (2021): 317. http://dx.doi.org/10.3390/electronics10030317.

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Acoustic cameras allow the visualization of sound sources using microphone arrays and beamforming techniques. The required computational power increases with the number of microphones in the array, the acoustic images resolution, and in particular, when targeting real-time. Such a constraint limits the use of acoustic cameras in many wireless sensor network applications (surveillance, industrial monitoring, etc.). In this paper, we propose a multi-mode System-on-Chip (SoC) Field-Programmable Gate Arrays (FPGA) architecture capable to satisfy the high computational demand while providing wirele

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Drahoš, Peter, Michal Kocúr, Oto Haffner, Erik Kučera, and Alena Kozáková. "RISC Conversions for LNS Arithmetic in Embedded Systems." Mathematics 8, no. 8 (2020): 1208. http://dx.doi.org/10.3390/math8081208.

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The paper presents an original methodology for the implementation of the Logarithmic Number System (LNS) arithmetic, which uses Reduced Instruction Set Computing (RISC). The core of the proposed method is a newly developed algorithm for conversion between LNS and the floating point (FLP) representations named “looping in sectors”, which brings about reduced memory consumption without a loss of accuracy. The resulting effective RISC conversions use only elementary computer operations without the need to employ multiplication, division, or other functions. Verification of the new concept and rel

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Hernández, Mario, Juan M. Cebrián, José M. Cecilia, and José M. García. "Offloading strategies for Stencil kernels on the KNC Xeon Phi architecture: Accuracy versus performance." International Journal of High Performance Computing Applications 34, no. 2 (2017): 199–207. http://dx.doi.org/10.1177/1094342017738352.

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The ever-increasing computational requirements of HPC and service provider applications are becoming a great challenge for hardware and software designers. These requirements are reaching levels where the isolated development on either computational field is not enough to deal with such challenge. A holistic view of the computational thinking is therefore the only way to success in real scenarios. However, this is not a trivial task as it requires, among others, of hardware–software codesign. In the hardware side, most high-throughput computers are designed aiming for heterogeneity, where acce

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Sánchez, Diego F., Daniel M. Muñoz, Carlos H. Llanos, and José M. Motta. "A Reconfigurable System Approach to the Direct Kinematics of a 5D.o.fRobotic Manipulator." International Journal of Reconfigurable Computing 2010 (2010): 1–10. http://dx.doi.org/10.1155/2010/727909.

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Hardware acceleration in high performance computer systems has a particular interest for many engineering and scientific applications in which a large number of arithmetic operations and transcendental functions must be computed. In this paper a hardware architecture for computing direct kinematics of robot manipulators with 5 degrees of freedom (5D.o.f) using floating-point arithmetic is presented for 32, 43, and 64 bit-width representations and it is implemented in Field Programmable Gate Arrays (FPGAs). The proposed architecture has been developed using several floating-point libraries for

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Dissertations / Theses on the topic "Computer architecture. Real-time data processing. Embedded computer systems Field programmable gate arrays"

1

Isaacson, Spencer William. "Hardware support for a configurable architecture for real-time embedded systems on a programmable chip /." Diss., CLICK HERE for online access, 2007. http://contentdm.lib.byu.edu/ETD/image/etd1966.pdf.

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Klingler, Randall S. "Compilation and Generation of Multi-Processor on a Chip Real-Time Embedded Systems." Diss., CLICK HERE for online access, 2007. http://contentdm.lib.byu.edu/ETD/image/etd1941.pdf.

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