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Relevant bibliographies by topics / Computer architectures; Digital signal processing

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Academic literature on the topic 'Computer architectures; Digital signal processing'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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Journal articles on the topic "Computer architectures; Digital signal processing"

1

Allen, J. "Computer architecture for digital signal processing." Proceedings of the IEEE 73, no. 5 (1985): 852–73. http://dx.doi.org/10.1109/proc.1985.13218.

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Bridges, Pries, McLeod, Yunik, Gulak, and Card. "Dual Systolic Architectures for VLSI Digital Signal Processing Systems." IEEE Transactions on Computers C-35, no. 10 (October 1986): 916–23. http://dx.doi.org/10.1109/tc.1986.1676684.

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Ramadass, N., and S. Natarajan. "Dynamically Reconfigurable Embedded Architecture-An Alternative To Application-Specific Digital Signal Processing Architectures." Journal of Computer Science 3, no. 10 (October 1, 2007): 823–28. http://dx.doi.org/10.3844/jcssp.2007.823.828.

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Anderson, John. "Digital Signal Processing." Microprocessors and Microsystems 13, no. 10 (December 1989): 673. http://dx.doi.org/10.1016/0141-9331(89)90076-8.

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M Tasbolatov, N. Mekebayev, O. Mamyrbayev, M. Turdalyuly, D. Oralbekova,. "Algorithms and architectures of speech recognition systems." Psychology and Education Journal 58, no. 2 (February 20, 2021): 6497–501. http://dx.doi.org/10.17762/pae.v58i2.3182.

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Digital processing of speech signal and the voice recognition algorithm is very important for fast and accurate automatic scoring of the recognition technology. A voice is a signal of infinite information. The direct analysis and synthesis of a complex speech signal is due to the fact that the information is contained in the signal. Speech is the most natural way of communicating people. The task of speech recognition is to convert speech into a sequence of words using a computer program. This article presents an algorithm of extracting MFCC for speech recognition. The MFCC algorithm reduces the processing power by 53% compared to the conventional algorithm. Automatic speech recognition using Matlab.

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ROSENDAHL, G. K., R. D. MCLEOD, and H. C. CARD. "A DSP–FPGA-BASED RECONFIGURABLE COMPUTER." Journal of Circuits, Systems and Computers 08, no. 04 (August 1998): 453–59. http://dx.doi.org/10.1142/s0218126698000250.

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In order to exploit architectural advantages associated with specific computations while at the same time having flexibility in those computations, we have designed a reconfigurable parallel machine architecture. A prototype reconfigurable computer has been constructed based on digital signal processing (DSP) chips and field-programmable gate arrays (FPGAs). Communications are based upon a broadcast network that employs FPGA-based message pre-processing and post-processing. Tradeoffs between computational and communication performance are made possible by software reconfiguration of the FPGAs. The system has been successfully tested on several applications in signal processing.

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Nawandar, Neha K., and Vishal R. Satpute. "Energy Efficient Quality Tunable CORDIC for DSP Applications on Battery Operated Portable Devices." Journal of Circuits, Systems and Computers 27, no. 04 (December 6, 2017): 1850051. http://dx.doi.org/10.1142/s0218126618500512.

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COrdinate Rotation DIgital Computer (CORDIC) is commonly utilized for the computation of cosine/sine i.e., the trigonometric functions, singular value decomposition, in digital signal processing (especially in image/video processing), etc. This paper introduces an energy efficient quality tunable CORDIC architecture that computes the cosine/sine values of any required angle in real-time, and is thus well suited for real time DSP applications, especially for image or video processing applications. The proposed architecture reduces the latency and overcomes data dependency by simultaneously performing all the five iterations, that may vary depending upon the desired energy efficiency. The novelty of this architecture is that, desired quality can be achieved by selecting one out of the available three modes. In order to assess the efficacy of the suggested architecture, some benchmark images are processed using the Discrete Cosine Transform (DCT) coefficients obtained via the proposed design. Energy saving is achieved at the cost of slight acceptable degradation in the output image quality. Further, the simulation results show that the proposed architecture is 92.3%, 2.8% and 49.08% more energy efficient than the existing basic, scale-free and lookahead CORDIC architectures, respectively.

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Fouts, Douglas J., Kendrick R. Macklin, Daniel P. Zulaica, and Russell W. Duren. "Electronic Warfare Digital Signal Processinig On COTS Computer Systems With Reconfigurable Architectures." Journal of Aerospace Computing, Information, and Communication 2, no. 10 (October 2005): 414–29. http://dx.doi.org/10.2514/1.17265.

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Saponara, Sergio, and Luca Fanucci. "Homogeneous and Heterogeneous MPSoC Architectures with Network-On-Chip Connectivity for Low-Power and Real-Time Multimedia Signal Processing." VLSI Design 2012 (August 14, 2012): 1–17. http://dx.doi.org/10.1155/2012/450302.

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Two multiprocessor system-on-chip (MPSoC) architectures are proposed and compared in the paper with reference to audio and video processing applications. One architecture exploits a homogeneous topology; it consists of 8 identical tiles, each made of a 32-bit RISC core enhanced by a 64-bit DSP coprocessor with local memory. The other MPSoC architecture exploits a heterogeneous-tile topology with on-chip distributed memory resources; the tiles act as application specific processors supporting a different class of algorithms. In both architectures, the multiple tiles are interconnected by a network-on-chip (NoC) infrastructure, through network interfaces and routers, which allows parallel operations of the multiple tiles. The functional performances and the implementation complexity of the NoC-based MPSoC architectures are assessed by synthesis results in submicron CMOS technology. Among the large set of supported algorithms, two case studies are considered: the real-time implementation of an H.264/MPEG AVC video codec and of a low-distortion digital audio amplifier. The heterogeneous architecture ensures a higher power efficiency and a smaller area occupation and is more suited for low-power multimedia processing, such as in mobile devices. The homogeneous scheme allows for a higher flexibility and easier system scalability and is more suited for general-purpose DSP tasks in power-supplied devices.

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Ching, PC, and SW Wu. "Realtime digital signal processing system using a parallel processing architecture." Microprocessors and Microsystems 13, no. 10 (December 1989): 653–58. http://dx.doi.org/10.1016/0141-9331(89)90073-2.

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Dissertations / Theses on the topic "Computer architectures; Digital signal processing"

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Dung, Lan-Rong. "VHDL-based conceptual prototyping of embedded DSP architectures." Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/14780.

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Pourbigharaz, Fariborz. "An investigation into efficient interfacing strategies for VLSI arithmetic processors based on residue number systems utilising diminished and augmented radix-2 moduli." Thesis, Brunel University, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.282927.

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Song, William S. "A fault-tolerant multiprocessor architecture for digital signal processing applications." Thesis, Massachusetts Institute of Technology, 1988. http://hdl.handle.net/1721.1/14427.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1989.
Includes bibliographical references.
Partly funded by US Air Force Office of Scientific Research. AFOSR-86-0164 Partly funded by Draper Laboratories.
by William S. Song.
Ph.D.

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Curtis, Bryce Allen. "A special instruction set multiple chip computer for DSP : architecture and compiler design." Diss., Georgia Institute of Technology, 1992. http://hdl.handle.net/1853/15736.

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Hodges, Christopher Joseph Munroe. "Skewed single instruction multiple data computation." Thesis, Georgia Institute of Technology, 1985. http://hdl.handle.net/1853/15693.

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Mauersberger, Gary S. "The design and hardware evaluation of an advanced 16-bit, low-power, high performance microcomputer system for digital signal processing." Thesis, Kansas State University, 1985. http://hdl.handle.net/2097/14006.

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Dworaczyk, Wiltshire Austin Aaron. "CUDA ENHANCED FILTERING IN A PIPELINED VIDEO PROCESSING FRAMEWORK." DigitalCommons@CalPoly, 2013. https://digitalcommons.calpoly.edu/theses/1072.

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The processing of digital video has long been a significant computational task for modern x86 processors. With every video frame composed of one to three planes, each consisting of a two-dimensional array of pixel data, and a video clip comprising of thousands of such frames, the sheer volume of data is significant. With the introduction of new high definition video formats such as 4K or stereoscopic 3D, the volume of uncompressed frame data is growing ever larger. Modern CPUs offer performance enhancements for processing digital video through SIMD instructions such as SSE2 or AVX. However, even with these instruction sets, CPUs are limited by their inherently sequential design, and can only operate on a handful of bytes in parallel. Even processors with a multitude of cores only execute on an elementary level of parallelism. GPUs provide an alternative, massively parallel architecture. GPUs differ from CPUs by providing thousands of throughput-oriented cores, instead of a maximum of tens of generalized “good enough at everything” x86 cores. The GPU’s throughput-oriented cores are far more adept at handling large arrays of pixel data, as many video filtering operations can be performed independently. This computational independence allows for pixel processing to scale across hun- dreds or even thousands of device cores. This thesis explores the utilization of GPUs for video processing, and evaluates the advantages and caveats of porting the modern video filtering framework, Vapoursynth, over to running entirely on the GPU. Compute heavy GPU-enabled video processing results in up to a 108% speedup over an SSE2-optimized, multithreaded CPU implementation.

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Smith, Paul Devon. "An Analog Architecture for Auditory Feature Extraction and Recognition." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4839.

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Speech recognition systems have been implemented using a wide range of signal processing techniques including neuromorphic/biological inspired and Digital Signal Processing techniques. Neuromorphic/biologically inspired techniques, such as silicon cochlea models, are based on fairly simple yet highly parallel computation and/or computational units. While the area of digital signal processing (DSP) is based on block transforms and statistical or error minimization methods. Essential to each of these techniques is the first stage of extracting meaningful information from the speech signal, which is known as feature extraction. This can be done using biologically inspired techniques such as silicon cochlea models, or techniques beginning with a model of speech production and then trying to separate the the vocal tract response from an excitation signal. Even within each of these approaches, there are multiple techniques including cepstrum filtering, which sits under the class of Homomorphic signal processing, or techniques using FFT based predictive approaches. The underlying reality is there are multiple techniques that have attacked the problem in speech recognition but the problem is still far from being solved. The techniques that have shown to have the best recognition rates involve Cepstrum Coefficients for the feature extraction and Hidden-Markov Models to perform the pattern recognition. The presented research develops an analog system based on programmable analog array technology that can perform the initial stages of auditory feature extraction and recognition before passing information to a digital signal processor. The goal being a low power system that can be fully contained on one or more integrated circuit chips. Results show that it is possible to realize advanced filtering techniques such as Cepstrum Filtering and Vector Quantization in analog circuitry. Prior to this work, previous applications of analog signal processing have focused on vision, cochlea models, anti-aliasing filters and other single component uses. Furthermore, classic designs have looked heavily at utilizing op-amps as a basic core building block for these designs. This research also shows a novel design for a Hidden Markov Model (HMM) decoder utilizing circuits that take advantage of the inherent properties of subthreshold transistors and floating-gate technology to create low-power computational blocks.

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Wells, Ian. "Digital signal processing architectures for speech recognition." Thesis, University of the West of England, Bristol, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.294705.

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Wang, Dalan. "Parallel architectures for signal processing." Thesis, University of Aberdeen, 1991. http://digitool.abdn.ac.uk/R?func=search-advanced-go&find_code1=WSN&request1=AAIU034219.

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This thesis presents the development of parallel architectures and algorithms for signal processing techniques, particularly for application to ultrasonic surface texture measurement. The background and context of this project is the real need to perform high speed signal processing on ultrasonic echoes used to extract information on texture properties of surfaces. Earlier investigation provided a solution by the nonlinear Maximum Entropy Method (MEM) which needs to be implemented at high speed and high performance. A review of parallel architectures for signal processing and digital signal processors is given. The aim is to introduce ways in which signal processing algorithms can be implemented at high speed. Both hardware and software have been developed in the project, and the signal processing system and parallel implementations of the algorithms are presented in detail. The signal processing system employs a parallel architecture using transputers. A feature of the design is that a floating-point digital signal processor is incorporated into a transputer array so that the performance of the system can be significantly enhanced. The design, testing and construction of the hardware system are discussed in detail. An investigation of some parallel DSP algorithms, including matrix multiplication, the Discrete Fourier Transform (DFT) and the Fast Fourier Transform (FFT), and their implementations based on the transputer array are discussed in order to choose an appropriate FFT implementation for our application. Several implementations of the deconvolution algorithms, including the Wiener-Hopf filter, the Maximum Entropy Method (MEM) and Projection Onto Convex Sets (POCS) are developed, which can benefit from the use of concurrency. A development of the MEM implementation based on the transputer array is to use the DSP as a subsystem for FFT calculations; this dual-system environment provides a significant resourse to be used to process ultrasonic echoes to determine surface roughness. Finally, the performance of the Projection Onto Convex Sets (POCS) algorithm in the field of ultrasonic surface determination and comparison with the Wiener-Hopf filter and the MEM are presented using simulated and real data. It is concluded that the parallel architecture provides a valuable contribution to high speed implementations of signal processing techniques.

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Books on the topic "Computer architectures; Digital signal processing"

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Architectures for digital signal processing. Chichester: Wiley, 1998.

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Residue number systems: Algorithms and architectures. Boston: Kluwer Academic Publishers, 2002.

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Luk, Franklin T. Advanced signal processing algorithms, architectures, and implementations XVIII: 10-11 August 2008, San Diego, California, USA. Edited by SPIE (Society). Bellingham, Wash: SPIE, 2008.

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Luk, Franklin T. Advanced signal processing algorithms, architectures, and implementations XVII: 26-27 August 2007, San Diego, California, USA. Edited by Society of Photo-optical Instrumentation Engineers. Bellingham, Wash: SPIE, 2007.

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Luk, Franklin T. Advanced signal processing algorithms, architectures, and implementations XVII: 26-27 August 2007, San Diego, California, USA. Edited by Society of Photo-optical Instrumentation Engineers. Bellingham, Wash: SPIE, 2007.

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Highly parallel signal processing architectures: 21 - 22 Jan. 1986, Los Angeles, Calif. Bellingham, Wash: Internat. Soc. for Optical Engineering, 1986.

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Bromley, Keith. Highly parallel signal processing architectures: 21 - 22 Jan. 1986, Los Angeles, Calif. Bellingham, Wash: Internat. Soc. for Optical Engineering, 1986.

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Inc, ebrary, ed. Special design topics in digital wideband receivers. Boston, Mass: Artech House, 2010.

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Kong), International Symposium on Computer Architecture and Digital Signal Processing (1989 Hong. CA-DSP '89: 1989 International Symposium on Computer Architecture and Digital Signal Processing, 11-14 October, 1989, Hong Kong Convention and Exhibition Centre Hong Kong. Hong Kong: Institution of Electrical Engineers, Hong Kong Centre, 1989.

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(Society), SPIE, ed. Mathematics for signal and information processing: 2-5 August 2009, San Diego, California, United States. Bellingham, Wash: SPIE, 2009.

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Book chapters on the topic "Computer architectures; Digital signal processing"

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Pirsch, P. "VLSI Architectures for Digital Video Signal Processing." In Computer Systems and Software Engineering, 65–99. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3506-5_3.

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Freimann, Achim. "Probabilistic Power Estimation for Digital Signal Processing Architectures." In Lecture Notes in Computer Science, 458–67. Berlin, Heidelberg: Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-45716-x_46.

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Benoit, Pascal, Gilles Sassatelli, Lionel Torres, Didier Demigny, Michel Robert, and Gaston Cambon. "Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability." In Lecture Notes in Computer Science, 128–37. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-27776-7_14.

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Raczinski, Jean-Michel, and Stéphane Sladek. "The Modular Architecture of SYNTHUP, FPGA Based PCI Board for Real-Time Sound Synthesis and Digital Signal Processing." In Lecture Notes in Computer Science, 834–37. Berlin, Heidelberg: Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/3-540-44614-1_97.

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Kienle, Frank. "Digital Transmission System." In Architectures for Baseband Signal Processing, 17–36. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-8030-3_2.

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Perdikaris, George A. "Digital Signal Processing." In Computer Controlled Systems, 291–321. Dordrecht: Springer Netherlands, 1991. http://dx.doi.org/10.1007/978-94-015-7929-2_5.

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Tolimieri, Richard, Myoung An, and Chao Lu. "Implementation on RISC Architectures." In Signal Processing and Digital Filtering, 141–60. New York, NY: Springer New York, 1997. http://dx.doi.org/10.1007/978-1-4612-1948-4_10.

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Tolimieri, Richard, Myoung An, and Chao Lu. "Implementation on Parallel Architectures." In Signal Processing and Digital Filtering, 161–83. New York, NY: Springer New York, 1997. http://dx.doi.org/10.1007/978-1-4612-1948-4_11.

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Tolimieri, Richard, Myoung An, and Chao Lu. "Implementation on RISC Architectures." In Signal Processing and Digital Filtering, 179–202. New York, NY: Springer US, 1993. http://dx.doi.org/10.1007/978-1-4684-0205-6_10.

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Tolimieri, Richard, Myoung An, and Chao Lu. "Implementation on Parallel Architectures." In Signal Processing and Digital Filtering, 203–29. New York, NY: Springer US, 1993. http://dx.doi.org/10.1007/978-1-4684-0205-6_11.

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Conference papers on the topic "Computer architectures; Digital signal processing"

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Farshchi, Farzad, Muhammad Saeed Abrishami, and Sied Mehdi Fakhraie. "New approximate multiplier for low power digital signal processing." In 2013 17th CSI International Symposium on Computer Architecture and Digital Systems (CADS). IEEE, 2013. http://dx.doi.org/10.1109/cads.2013.6714233.

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Som, S., and M. D. Wagh. "Throughput enhancement in multiprocessor architectures for pipelining and digital signal processing applications." In Eleventh Annual International Phoenix Conference on Computers and Communication [1992 Conference Proceedings]. IEEE, 1992. http://dx.doi.org/10.1109/pccc.1992.200540.

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Kshirsagar, Shirish P., David A. Hartley, David M. Harvey, and Clifford A. Hobson. "Parallel digital signal processing architectures for image processing." In SPIE's 1994 International Symposium on Optics, Imaging, and Instrumentation, edited by Franklin T. Luk. SPIE, 1994. http://dx.doi.org/10.1117/12.190876.

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Harvey, D. M. "Digital signal processing systems architectures for image processing." In Fifth International Conference on Image Processing and its Applications. IEE, 1995. http://dx.doi.org/10.1049/cp:19950701.

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Zou, Chengzhe, and Ryan L. Harne. "Folding Star-Shaped Acoustic Transducers for Real-Time Guidance of Radiated Acoustic Waves." In ASME 2017 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. American Society of Mechanical Engineers, 2017. http://dx.doi.org/10.1115/detc2017-67286.

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Directed acoustic energy is used throughout medical practices, scientific research, and engineering applications. Conventionally, arrays of transducer constituents are assembled and driven with inputs that are determined by digital signal processing methods, which guides the acoustic waves for signal transmission and reception purposes. Beamforming is the term for this approach, although inherent limitations of stability and computational efficiency hinder the outcomes. Recent efforts have revealed the broad merits of folding origami-inspired acoustic array architectures so that the transducer constituent and array shapes change, giving rise to direct control of acoustic energy radiation characteristics. Because the design of the origami tessellation used to create the array is pivotal to the adaptive acoustic energy steering, a new star-shaped foldable transducer is studied in this work for its unique inward and outward shape change characteristics. In order to facilitate this investigation, an analytical framework is developed to identify the connections between the folding-induced topology and radiated sound field. The high-fidelity boundary element method verifies the analytical model while experimental efforts validate the theoretical predictions. The adaptation of radiated sound pressure from the star-shaped transducer is shown to be several orders of magnitude, which illustrates its great potential in acoustic energy guidance and prospective applications.

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Teimoori, Hassan, Dimitrios Apostolopoulos, Kyriakos Vlachos, Cedric Ware, Dimitrios Petrantonakis, Kostas Yiannopoulos, Leontios Stampoulidis, Hercules Avramopoulos, and Didier Erasme. "Physical architectures for packet-switching network nodes based on nonlinear logic gates." In Digital Signal Processing (CSNDSP). IEEE, 2008. http://dx.doi.org/10.1109/csndsp.2008.4610753.

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Labhane, Mrunalini B., and Prachi Palsodkar. "Various architectures of analog to digital converter." In 2015 International Conference on Communications and Signal Processing (ICCSP). IEEE, 2015. http://dx.doi.org/10.1109/iccsp.2015.7322696.

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Brenner, K. H., and A. Lohmann. "Optical circuitry and architectures for digital optical computing." In IEEE International Conference on Acoustics, Speech, and Signal Processing. IEEE, 1986. http://dx.doi.org/10.1109/icassp.1986.1169022.

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Dabrowski, Adam, Pawel Pawlowski, and Tomasz Marciniak. "Parallel digital signal processing using multi-issue instructions." In 2007 Signal Processing Algorithms, Architectures, Arrangements, and Applications (SPA 2007). IEEE, 2007. http://dx.doi.org/10.1109/spa.2007.5903293.

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Abd-Elrady, E., and B. Mulgrew. "Direct learning architectures for digital predistortion of nonlinear Volterra systems." In Sensor Signal Processing for Defence (SSPD 2010). IET, 2010. http://dx.doi.org/10.1049/ic.2010.0226.

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Reports on the topic "Computer architectures; Digital signal processing"

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Parhi, Keshab K. Design Tools and Architectures for Dedicated Digital Signal Processing (DSP) Processors. Fort Belvoir, VA: Defense Technical Information Center, July 1996. http://dx.doi.org/10.21236/ada397589.

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