Journal articles: 'Computer architectures; Digital signal processing'

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Allen, J. "Computer architecture for digital signal processing." Proceedings of the IEEE 73, no. 5 (1985): 852–73. http://dx.doi.org/10.1109/proc.1985.13218.

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Bridges, Pries, McLeod, Yunik, Gulak, and Card. "Dual Systolic Architectures for VLSI Digital Signal Processing Systems." IEEE Transactions on Computers C-35, no. 10 (October 1986): 916–23. http://dx.doi.org/10.1109/tc.1986.1676684.

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Ramadass, N., and S. Natarajan. "Dynamically Reconfigurable Embedded Architecture-An Alternative To Application-Specific Digital Signal Processing Architectures." Journal of Computer Science 3, no. 10 (October 1, 2007): 823–28. http://dx.doi.org/10.3844/jcssp.2007.823.828.

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Anderson, John. "Digital Signal Processing." Microprocessors and Microsystems 13, no. 10 (December 1989): 673. http://dx.doi.org/10.1016/0141-9331(89)90076-8.

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M Tasbolatov, N. Mekebayev, O. Mamyrbayev, M. Turdalyuly, D. Oralbekova,. "Algorithms and architectures of speech recognition systems." Psychology and Education Journal 58, no. 2 (February 20, 2021): 6497–501. http://dx.doi.org/10.17762/pae.v58i2.3182.

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Digital processing of speech signal and the voice recognition algorithm is very important for fast and accurate automatic scoring of the recognition technology. A voice is a signal of infinite information. The direct analysis and synthesis of a complex speech signal is due to the fact that the information is contained in the signal. Speech is the most natural way of communicating people. The task of speech recognition is to convert speech into a sequence of words using a computer program. This article presents an algorithm of extracting MFCC for speech recognition. The MFCC algorithm reduces the processing power by 53% compared to the conventional algorithm. Automatic speech recognition using Matlab.

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ROSENDAHL, G. K., R. D. MCLEOD, and H. C. CARD. "A DSP–FPGA-BASED RECONFIGURABLE COMPUTER." Journal of Circuits, Systems and Computers 08, no. 04 (August 1998): 453–59. http://dx.doi.org/10.1142/s0218126698000250.

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In order to exploit architectural advantages associated with specific computations while at the same time having flexibility in those computations, we have designed a reconfigurable parallel machine architecture. A prototype reconfigurable computer has been constructed based on digital signal processing (DSP) chips and field-programmable gate arrays (FPGAs). Communications are based upon a broadcast network that employs FPGA-based message pre-processing and post-processing. Tradeoffs between computational and communication performance are made possible by software reconfiguration of the FPGAs. The system has been successfully tested on several applications in signal processing.

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Nawandar, Neha K., and Vishal R. Satpute. "Energy Efficient Quality Tunable CORDIC for DSP Applications on Battery Operated Portable Devices." Journal of Circuits, Systems and Computers 27, no. 04 (December 6, 2017): 1850051. http://dx.doi.org/10.1142/s0218126618500512.

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COrdinate Rotation DIgital Computer (CORDIC) is commonly utilized for the computation of cosine/sine i.e., the trigonometric functions, singular value decomposition, in digital signal processing (especially in image/video processing), etc. This paper introduces an energy efficient quality tunable CORDIC architecture that computes the cosine/sine values of any required angle in real-time, and is thus well suited for real time DSP applications, especially for image or video processing applications. The proposed architecture reduces the latency and overcomes data dependency by simultaneously performing all the five iterations, that may vary depending upon the desired energy efficiency. The novelty of this architecture is that, desired quality can be achieved by selecting one out of the available three modes. In order to assess the efficacy of the suggested architecture, some benchmark images are processed using the Discrete Cosine Transform (DCT) coefficients obtained via the proposed design. Energy saving is achieved at the cost of slight acceptable degradation in the output image quality. Further, the simulation results show that the proposed architecture is 92.3%, 2.8% and 49.08% more energy efficient than the existing basic, scale-free and lookahead CORDIC architectures, respectively.

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Fouts, Douglas J., Kendrick R. Macklin, Daniel P. Zulaica, and Russell W. Duren. "Electronic Warfare Digital Signal Processinig On COTS Computer Systems With Reconfigurable Architectures." Journal of Aerospace Computing, Information, and Communication 2, no. 10 (October 2005): 414–29. http://dx.doi.org/10.2514/1.17265.

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Saponara, Sergio, and Luca Fanucci. "Homogeneous and Heterogeneous MPSoC Architectures with Network-On-Chip Connectivity for Low-Power and Real-Time Multimedia Signal Processing." VLSI Design 2012 (August 14, 2012): 1–17. http://dx.doi.org/10.1155/2012/450302.

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Two multiprocessor system-on-chip (MPSoC) architectures are proposed and compared in the paper with reference to audio and video processing applications. One architecture exploits a homogeneous topology; it consists of 8 identical tiles, each made of a 32-bit RISC core enhanced by a 64-bit DSP coprocessor with local memory. The other MPSoC architecture exploits a heterogeneous-tile topology with on-chip distributed memory resources; the tiles act as application specific processors supporting a different class of algorithms. In both architectures, the multiple tiles are interconnected by a network-on-chip (NoC) infrastructure, through network interfaces and routers, which allows parallel operations of the multiple tiles. The functional performances and the implementation complexity of the NoC-based MPSoC architectures are assessed by synthesis results in submicron CMOS technology. Among the large set of supported algorithms, two case studies are considered: the real-time implementation of an H.264/MPEG AVC video codec and of a low-distortion digital audio amplifier. The heterogeneous architecture ensures a higher power efficiency and a smaller area occupation and is more suited for low-power multimedia processing, such as in mobile devices. The homogeneous scheme allows for a higher flexibility and easier system scalability and is more suited for general-purpose DSP tasks in power-supplied devices.

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Ching, PC, and SW Wu. "Realtime digital signal processing system using a parallel processing architecture." Microprocessors and Microsystems 13, no. 10 (December 1989): 653–58. http://dx.doi.org/10.1016/0141-9331(89)90073-2.

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Vehlies, Uwe. "Stepwise Transformation of Algorithms into Array Processor Architectures by the DECOMP." VLSI Design 3, no. 1 (January 1, 1995): 67–80. http://dx.doi.org/10.1155/1995/76861.

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A formal approach for the transformation of computation intensive digital signal processing algorithms into suitable array processor architectures is presented. It covers the complete design flow from algorithmic specifications in a high-level programming language to architecture descriptions in a hardware description language. The transformation itself is divided into manageable design steps and implemented in the CAD-tool DECOMP which allows the exploration of different architectures in a short time. With the presented approach data independent algorithms can be mapped onto array processor architectures. To allow this, a known mapping methodology for array processor design is extended to handle inhomogeneous dependence graphs with nonregular data dependences. The implementation of the formal approach in the DECOMP is an important step towards design automation for massively parallel systems.

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Sapper, André, Guilherme Paim, Eduardo Antônio César Da Costa, and Sergio Bampi. "Exploring the CORDIC Algorithm and Clock-Gating for Power-Efficient Fast Fourier Transform Hardware Architectures." Journal of Integrated Circuits and Systems 16, no. 2 (August 15, 2021): 1–11. http://dx.doi.org/10.29292/jics.v16i2.226.

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This work explores hardware-oriented optimizations for the CORDIC (COordinate Rotation Digital Computer) algorithm investigating the power-efficiency improvements employing N-point Fast Fourier Transform (FFT) hardware architectures. We introduced three hardware-oriented optimizations for the CORDIC: (a) improving the signal extension, (b) removing the angle accumulation and (c) eliminating the redundancies in the iterations, both unnecessary when processing the FFT processing. Fully sequential FFT architectures of 32, 64, 128, and 256 points were synthesized employing ST 65 nm standard cell libraries. The results show up to 38% of power savings on average when using our best CORDIC optimization proposal to the FFT architecture comparing to the explicit multiply-based butterfly version. Moreover, when combining our best CORDIC optimization with the clock-gating technique, the power savings rises to 78.5% on average for N-point FFT.

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Challener, Paul. "Fast algorithms for digital signal processing." Microprocessors and Microsystems 9, no. 10 (December 1985): 514. http://dx.doi.org/10.1016/0141-9331(85)90186-3.

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Saponara, Sergio, and Pierangelo Terreni. "Mixed-Signal Architectures for High-Efficiency and Low-Distortion Digital Audio Processing and Power Amplification." EURASIP Journal on Embedded Systems 2010 (2010): 1–11. http://dx.doi.org/10.1155/2010/394070.

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McKinney, B. C., and F. El Guibaly. "A multiple-access pipeline architecture for digital signal processing." IEEE Transactions on Computers 37, no. 3 (March 1988): 283–90. http://dx.doi.org/10.1109/12.2165.

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Tan, H., M. Walby, W. Hennig, W. Warburton, P. Grudberg, C. Reintsema, D. Bennett, W. Doriese, and J. Ullom. "A Digital Signal Processing Module for Time-Division Multiplexed Microcalorimeter Arrays." Applied Superconductivity, IEEE Transactions on 23, no. 3 (January 2013): 2500305. http://dx.doi.org/10.1109/tasc.2012.2236632.

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We have developed a digital signal processing module for real time processing of time-division multiplexed data from SQUID-coupled transition-edge sensor microcalorimeter arrays. It is a 3U PXI card consisting of a standardized core processor board and a daughter board. Through fiber-optic links on its front panel, the daughter board receives time-division multiplexed data (comprising error and feedback signals) and clocks from the digital-feedback cards developed at the National Institute of Standards and Technology. After mixing the error signal with the feedback signal in a field-programmable gate array, the daughter board transmits demultiplexed data to the core processor. Real-time processing in the field-programmable gate array of the core processor board includes pulse detection, pileup inspection, pulse height computation, and histogramming into on-board spectrum memory. Data from up to 128 microcalorimeter pixels can be processed by a single module in real time. Energy spectra, waveform, and run statistics data can be read out in real time through the PCI bus by a host computer at a maximum rate of ~100 MB/s. The module's hardware architecture, mechanism for synchronizing with NIST's digital-feedback, and count rate capability are presented.

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Cho, Koon-Shik, and Jun-Dong Cho. "Low Power Digital Multimedia Telecommunication Designs." VLSI Design 12, no. 3 (January 1, 2001): 301–15. http://dx.doi.org/10.1155/2001/43078.

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The increasing prominence of wireless multimedia systems and the need to limit power capability in very-high density VLSI chips have led to rapid and innovative developments in low-power design. Power reduction has emerged as a significant design constraint in VLSI design. The need for wireless multimedia systems leads to much higher power consumption than traditional portable applications. This paper presents possible optimization technique to reduce the energy consumption for wireless multimedia communication systems. Four topics are presented in the wireless communication systems subsection which deal with architectures such as PN acquisition, parallel correlator, matched filter and channel coding. Two topics include the IDCT and motion estimation in multimedia application.These topics consider algorithms and architectures for low power design such as using hybrid architecture in PN acquisition, analyzing the algorithm and optimizing the sample storage in parallel correlator, using complex matched filter that analog operational circuits controlled by digital signals, adopting bit serial arithmetic for the ACS operation in viterbi decoder, using CRC to adaptively terminate the SOVA iteration in turbo decoder, using codesign in RS codec, disabling the processing elements as soon as the distortion values become great than the minimum distortion value in motion estimation, and exploiting the relative occurrence of zero-valued DCT coefficient in IDCT.

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Hendry, David. "High level synthesis for real-time digital signal processing." Microprocessors and Microsystems 18, no. 8 (October 1994): 491–92. http://dx.doi.org/10.1016/0141-9331(94)90100-7.

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Schneider, M., H. Blume, and T. G. Noll. "Power estimation on functional level for programmable processors." Advances in Radio Science 2 (May 27, 2005): 215–19. http://dx.doi.org/10.5194/ars-2-215-2004.

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Abstract. In diesem Beitrag werden verschiedene Ansätze zur Verlustleistungsschätzung von programmierbaren Prozessoren vorgestellt und bezüglich ihrer Übertragbarkeit auf moderne Prozessor-Architekturen wie beispielsweise Very Long Instruction Word (VLIW)-Architekturen bewertet. Besonderes Augenmerk liegt hierbei auf dem Konzept der sogenannten Functional-Level Power Analysis (FLPA). Dieser Ansatz basiert auf der Einteilung der Prozessor-Architektur in funktionale Blöcke wie beispielsweise Processing-Unit, Clock-Netzwerk, interner Speicher und andere. Die Verlustleistungsaufnahme dieser Bl¨ocke wird parameterabhängig durch arithmetische Modellfunktionen beschrieben. Durch automatisierte Analyse von Assemblercodes des zu schätzenden Systems mittels eines Parsers können die Eingangsparameter wie beispielsweise der erzielte Parallelitätsgrad oder die Art des Speicherzugriffs gewonnen werden. Dieser Ansatz wird am Beispiel zweier moderner digitaler Signalprozessoren durch eine Vielzahl von Basis-Algorithmen der digitalen Signalverarbeitung evaluiert. Die ermittelten Schätzwerte für die einzelnen Algorithmen werden dabei mit physikalisch gemessenen Werten verglichen. Es ergibt sich ein sehr kleiner maximaler Schätzfehler von 3%. In this contribution different approaches for power estimation for programmable processors are presented and evaluated concerning their capability to be applied to modern digital signal processor architectures like e.g. Very Long InstructionWord (VLIW) -architectures. Special emphasis will be laid on the concept of so-called Functional-Level Power Analysis (FLPA). This approach is based on the separation of the processor architecture into functional blocks like e.g. processing unit, clock network, internal memory and others. The power consumption of these blocks is described by parameter dependent arithmetic model functions. By application of a parser based automized analysis of assembler codes of the systems to be estimated the input parameters of the Correspondence to: H. Blume (blume@eecs.rwth-aachen.de) arithmetic functions like e.g. the achieved degree of parallelism or the kind and number of memory accesses can be computed. This approach is exemplarily demonstrated and evaluated applying two modern digital signal processors and a variety of basic algorithms of digital signal processing. The resulting estimation values for the inspected algorithms are compared to physically measured values. A resulting maximum estimation error of 3% is achieved.

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El-Sharkawy, Mohamed, Wenlong Tsang, and Maurice Aburdene. "Parallel vector processing of multidimensional orthogonal transforms for digital signal processing applications." Multidimensional Systems and Signal Processing 1, no. 2 (June 1990): 199–216. http://dx.doi.org/10.1007/bf01816549.

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Elhossini, Ahmed, Shawki Areibi, and Robert Dony. "Architecture Exploration Based on GA-PSO Optimization, ANN Modeling, and Static Scheduling." VLSI Design 2013 (September 26, 2013): 1–22. http://dx.doi.org/10.1155/2013/624369.

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Embedded systems are widely used today in different digital signal processing (DSP) applications that usually require high computation power and tight constraints. The design space to be explored depends on the application domain and the target platform. A tool that helps explore different architectures is required to design such an efficient system. This paper proposes an architecture exploration framework for DSP applications based on Particle Swarm Optimization (PSO) and genetic algorithms (GA) techniques that can handle multiobjective optimization problems with several hybrid forms. A novel approach for performance evaluation of embedded systems is also presented. Several cycle-accurate simulations are performed for commercial embedded processors. These simulation results are used to build an artificial neural network (ANN) model that can predict performance/power of newly generated architectures with an accuracy of 90% compared to cycle-accurate simulations with a very significant time saving. These models are combined with an analytical model and static scheduler to further increase the accuracy of the estimation process. The functionality of the framework is verified based on benchmarks provided by our industrial partner ON Semiconductor to illustrate the ability of the framework to investigate the design space.

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Moldakhan, Inabat, Dinara K. Matrassulova, Dina B. Shaltykova, and Ibragim E. Suleimenov. "Some advantages of non-binary Galois fields for digital signal processing." Indonesian Journal of Electrical Engineering and Computer Science 23, no. 2 (August 1, 2021): 871. http://dx.doi.org/10.11591/ijeecs.v23.i2.pp871-878.

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It is shown that the convenient processing facilities of digital signals that varying in a finite range of amplitudes are non-binary Galois fields, the numbers of which elements are equal to prime numbers. Within choosing a sampling interval which corresponding to such a Galois field, it becomes possible to construct a Galois field Fourier transform, a distinctive feature of which is the exact correspondence with the ranges of variation of the amplitudes of the original signal and its digital spectrum. This favorably distinguishes the Galois Field Fourier Transform of the proposed type from the spectra, which calculated using, for example, the Walsh basis. It is also shown, that Galois Field Fourier Transforms of the proposed type have the same properties as the Fourier transform associated with the expansion in terms of the basis of harmonic functions. In particular, an analogue of the classical correlation, which connected the signal spectrum and its derivative, was obtained. On this basis proved, that the using of the proposed type of Galois fields makes it possible to develop a complete analogue of the transfer function apparatus, but only for signals presented in digital form.

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Merakos, P. K., K. Masselos, and C. E. Goutis. "Power Efficient Hierarchical Scheduling for DSP Transformations." VLSI Design 14, no. 2 (January 1, 2002): 203–17. http://dx.doi.org/10.1080/10655140290010114.

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In this paper, the problem of scheduling the computation of partial products in transformational Digital Signal Processing (DSP) algorithms, aiming at the minimization of the switching activity in data and address buses, is addressed. The problem is stated as a hierarchical scheduling problem. Two different optimization algorithms, which are based on the Travelling Salesman Problem (TSP), are defined. The proposed optimization algorithms are independent on the target architecture and can be adapted to take into account it. Experimental results obtained from the application of the proposed algorithms in various widely used DSP transformations, like Discrete Cosine Transform (DCT) and Discrete Fourier Transform (DFT), show that significant switching activity savings in data and address buses can be achieved, resulting in corresponding power savings. In addition, the differences between the two proposed methods are underlined, providing envisage for their suitable selection for implementation, in particular transformational algorithms and architectures.

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Tan, Jingjia, Lesheng He, and Jun Wang. "Signal acquisition and processing system based on zynq dual core." MATEC Web of Conferences 246 (2018): 03001. http://dx.doi.org/10.1051/matecconf/201824603001.

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In order to speed up the acquisition and processing of signal, this paper has developed a signal acquisition and processing system based on zynq platform. Based on the ARM Cortex-A9 dual-core and editable logic unit architecture of Zynq AP SoC platform, this paper implements a fully functional signal acquisition and processing system by software and hardware collaborative design. ARM0 is the main processor that controls system and shared resources. ARM1 is the slave processor. ARM1 is responsible for receiving the data converted by the AD7606 analog-to-digital chip. The data is sent to the Hamming window function IP core created under vivado HLS through the AXI bus. After the data is processed by Hamming window function, it is sent to ARM1 again through AXI bus. OCM acts as the shared memory for ARM0 and ARM1 communication. The Linux system runs on ARM0. The processed data is sent to the upper computer through ethernet through UDP protocol. Utilizing the architecture of the Zynq platform, the system efficiency is improved, and the stability of the system is ensured, so that the FPGA can enter the field of embedded systems.

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Torres-Huitzil, Cesar. "Resource Efficient Hardware Architecture for Fast Computation of Running Max/Min Filters." Scientific World Journal 2013 (2013): 1–10. http://dx.doi.org/10.1155/2013/108103.

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Running max/min filters on rectangular kernels are widely used in many digital signal and image processing applications. Filtering with ak×kkernel requires ofk2−1comparisons per sample for a direct implementation; thus, performance scales expensively with the kernel sizek. Faster computations can be achieved by kernel decomposition and using constant time one-dimensional algorithms on custom hardware. This paper presents a hardware architecture for real-time computation of running max/min filters based on the van Herk/Gil-Werman (HGW) algorithm. The proposed architecture design uses less computation and memory resources than previously reported architectures when targeted to Field Programmable Gate Array (FPGA) devices. Implementation results show that the architecture is able to compute max/min filters, on1024×1024images with up to255×255kernels, in around 8.4 milliseconds, 120 frames per second, at a clock frequency of 250 MHz. The implementation is highly scalable for the kernel size with good performance/area tradeoff suitable for embedded applications. The applicability of the architecture is shown for local adaptive image thresholding.

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Dolz, Manuel F., Fran J. Alventosa, Pedro Alonso-Jordá, and Antonio M. Vidal. "A pipeline structure for the block QR update in digital signal processing." Journal of Supercomputing 75, no. 3 (October 30, 2018): 1470–82. http://dx.doi.org/10.1007/s11227-018-2666-1.

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Gassoumi, Ismail, Lamjed Touil, Bouraoui Ouni, and Abdellatif Mtibaa. "An Efficient Design of DCT Approximation Based on Quantum Dot Cellular Automata (QCA) Technology." Journal of Electrical and Computer Engineering 2019 (October 2, 2019): 1–11. http://dx.doi.org/10.1155/2019/9029526.

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Optimization for power is one of the most important design objectives in modern digital image processing applications. The DCT is considered to be one of the most essential techniques in image and video compression systems, and consequently a number of extensive works had been carried out by researchers on the power optimization. On the other hand, quantum-dot cellular automata (QCA) can present a novel opportunity for the design of highly parallel architectures and algorithms for improving the performance of image and video processing systems. Furthermore, it has considerable advantages in comparison with CMOS technology, such as extremely low power dissipation, high operating frequency, and a small size. Therefore, in this study, the authors propose a multiplier-less DCT architecture in QCA technology. The proposed design provides high circuit performance, very low power consumption, and very low dimension outperform to the existing conventional structures. The QCADesigner tool has been utilized for QCA circuit design and functional verification of all designs in this work. QCAPro, a very widespread power estimator tool, is applied to estimate the power dissipation of the proposed circuit. The suggested design has 53% improvement in terms of power over the conventional solution. The outcome of this work can clearly open up a new window of opportunity for low power image processing systems.

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Hong, Juhyung, Jaehyun Baek, and Myung Hoon Sunwoo. "Novel Digital Signal Processing Unit Using New Digital Baseline Wander Corrector for Fast Ethernet." Journal of Signal Processing Systems 61, no. 2 (November 17, 2009): 193–204. http://dx.doi.org/10.1007/s11265-009-0422-8.

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A. Asker, Mshari, Khalaf S. Gaeid, Nada N. Tawfeeq, Humam K. Zain, Ali I. Kauther, and Thamir Q Abdullah. "Design and Analysis of Robot PID Controller Using Digital Signal Processing Techniques." International Journal of Engineering & Technology 7, no. 4.37 (December 13, 2018): 103. http://dx.doi.org/10.14419/ijet.v7i4.37.23625.

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Recently robotic is a playing vital role in the life In our modern society, the usage of robotic arms are increasing and much of the work in the industry is now performed by robots. As robots begin to behave like humans in an intelligent manner, control system becomes a major concern. In this paper, design and analyses of the pick and place robot due to control, the forearm, wrist, desired turntable and desired bicep is introduced to construct a closed system with four degrees of freedom (4DOFs). The main performance specifications are the accuracy and stability of the input system for obtaining a good system performance. Implementation of the control system using PID parameters for stability, minimum steady state error, minimum overshoot and faster system response has been carried out. The design of two degree of freedom PID(2DoFPID) to control robotic arm along with first order low pass filter(LPF) to compensate the unwanted signal is improved. To be able to implement such a precise and effective system, feedback system has to be made to improve the overall performance specifications. The digital signal processing controller (Arduino Uno) is used as it is active, cheap , it has open source code and easy to use in the software and hardware applications.Experimental set up developed in addition to the Matlab/Simulink implementation of the complete system. The results and the communication signals test ensure smooth operation of the control system and the effectiveness of the proposed algorithm.

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Alekseev, G. G., E. A. Alekseeva, P. V. Galagan, A. P. Sorokin, and S. А. Sorokin. "METHODS FOR IMPLEMENTING NEURAL NETWORK HYDROACOUSTICS ALGORITHMS BASED ON HETEROGENEOUS HARDWARE PLATFORM GRIFON." Issues of radio electronics, no. 5 (June 8, 2019): 48–59. http://dx.doi.org/10.21778/2218-5453-2019-5-48-59.

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Recently, there has been an increase of interest in creating new neural network hydroacoustics algorithms, for example, test sites in the Arctic are being created to evaluate the effectiveness of target detection and to ensure the safety of the Canadian North. The open architecture allows you to adapt hardware to new threats or economic interests. Not only the equipment of radiation and reception of hydroacoustic systems is improved, but also their processing. The article discusses the ways of improvement and the principles of building specialized computers based on the GRIFON hardware platform, providing control and signal processing in mobile and stationary sonar systems. We consider an example of creating a complex that demonstrates the capabilities of the equipment and the prospects for creating calculators with high parameters and minimal mass‑dimensional characteristics. Described in detail the structure and principles of the mathematical software of specialized computer. Comparative characteristics of the proposed algorithms that can be used to optimize signal processing paths and the volume of digital equipment are given.

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Magueta, R., V. Mendes, D. Castanheira, A. Silva, R. Dinis, and A. Gameiro. "Iterative Multiuser Equalization for Subconnected Hybrid mmWave Massive MIMO Architecture." Wireless Communications and Mobile Computing 2017 (2017): 1–13. http://dx.doi.org/10.1155/2017/9171068.

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Millimeter waves and massive MIMO are a promising combination to achieve the multi-Gb/s required by future 5G wireless systems. However, fully digital architectures are not feasible due to hardware limitations, which means that there is a need to design signal processing techniques for hybrid analog-digital architectures. In this manuscript, we propose a hybrid iterative block multiuser equalizer for subconnected millimeter wave massive MIMO systems. The low complexity user-terminals employ pure-analog random precoders, each with a single RF chain. For the base station, a subconnected hybrid analog-digital equalizer is designed to remove multiuser interference. The hybrid equalizer is optimized using the average bit-error-rate as a metric. Due to the coupling between the RF chains in the optimization problem, the computation of the optimal solutions is too complex. To address this problem, we compute the analog part of the equalizer sequentially over the RF chains using a dictionary built from the array response vectors. The proposed subconnected hybrid iterative multiuser equalizer is compared with a recently proposed fully connected approach. The results show that the performance of the proposed scheme is close to the fully connected hybrid approach counterpart after just a few iterations.

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Redinbo, G. Robert. "Fault-tolerant digital filtering architectures using fast finite field transforms." Signal Processing 9, no. 1 (July 1985): 37–50. http://dx.doi.org/10.1016/0165-1684(85)90063-5.

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Mu`ñoz, Daniel M., Diego F. Sanchez, Carlos H. Llanos, and Mauricio Ayala-Rincón. "Tradeoff of FPGA Design of a Floating-point Library for Arithmetic Operators." Journal of Integrated Circuits and Systems 5, no. 1 (November 21, 2010): 42–52. http://dx.doi.org/10.29292/jics.v5i1.309.

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Many scientific and engineering applications require to perform a large number of arithmetic operations that must be computed in an efficient manner using a high precision and a large dynamic range. Commonly, these applications are implemented on personal computers taking advantage of the floating-point arithmetic to perform the computations and high operational frequencies. However, most common software architectures execute the instructions in a sequential way due to the von Neumann model and, consequently, several delays are introduced in the data transfer between the program memory and the Arithmetic Logic Unit (ALU). There are several mobile applications which require to operate with a high performance in terms of accuracy of the computations and execution time as well as with low power consumption. Modern Field Programmable Gate Arrays (FPGAs) are a suitable solution for high performance embedded applications given the flexibility of their architectures and their parallel capabilities, which allows the implementation of complex algorithms and performance improvements. This paper describes a parameterizable floating-point library for arithmetic operators based on FPGAs. A general architecture was implemented for addition/subtraction and multiplication and two different architectures based on the Goldschmidt’s and the Newton-Raphson algorithms were implemented for division and square root. Additionally, a tradeoff analysis of the hardware implementation was performed, which enables the designer to choose, for general purpose applications, the suitable bit-width representation and error associated, as well as the area cost, elapsed time and power consumption for each arithmetic operator. Synthesis results have demonstrated the effectiveness of the implemented cores on commercial FPGAs and showed that the most critical parameter is the dedicated Digital Signal Processing (DSP) slices consumption. Simulation results were addressed to compute the mean square error (MSE) and maximum absolute error demonstrating the correctness of the implemented floating-point library and achieving and experimental error analysis. The Newton-Raphson algorithm achieves similar MSE results as the Goldschmidt’s algorithm, operating with similar frequencies; however, the first one saves more logic area and dedicated DSP blocks.

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Kameyama, Michitaka. "Special Issue on Computer Architecture for Robotics." Journal of Robotics and Mechatronics 2, no. 6 (December 20, 1990): 417. http://dx.doi.org/10.20965/jrm.1990.p0417.

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In the realization of intelligent robots, highly intelligent manipulation and movement techniques are required such as intelligent man-machine interfaces, intelligent information processing for path planning and problem solutions, practical robot vision, and high-speed sensor signal processing. Thus, very high-speed processing to cope with vast amounts of data as well as the development of various algorithms has become important subjects. To fulfill such requirements, the development of high-performance computer architecture using advanced microelectronics technology is required. For these purposes, the development of implementing computer systems’ for robots will be classified as follows: (a) Use of general-purpose computers As the performance of workstations and personal computers is increased year by year, software development is the major task without requiring hardware development except the interfaces with peripheral equipment. Since current high-level languages and software can be applied, the approach is excellent in case of system development, but the processing performance is limited. (b) Use of commercially available (V) LSI chips This is an approach to design a computer system by the combination of commercially available LSIs. Since the development of both hardware and software is involved in this system development, the development period tends to be longer than in (a). These chips include general-purpose microprocessors, memory chips, digital signal processors (DSPs) and multiply-adder LSIs. Though the kinds of available chips are limited to some degree, the approach can cope with a considerably high-performance specifications because a number of chips can be flexibly used. (c) Design, development and system configuration of VLSI chips This is an approach to develop new special-purpose VLSI chips using ASIC (Application Specific Integrated Circuit) technology, that is, semicustom or full-custom technology. If these attain practical use and are marketed, they will be widely used as high-performance VLSI chips of the level (b). Since a very high-performance specification must be satisfied, the study of very high performance VLSI computer architecture becomes very important. But this approach involving chip development requires a very long period in the design-development from the determination of processor specifications to the system configuration using the fabricated chips. For the above three approaches, the order from the viewpoint of ease of development will be (a), (b) and (c), while that from the viewpoint of performance will be (c), (b) and (a). Each approach is not exclusive but is complementary each other. For example, the development of new chips by (c) can also give new impact as the components of (a) and (b). Further, the common point of these approaches is that performance improvement by highly parallel architecture becomes important. This special edition introduces, from the above standpoint, the latest information on the present state and' future prospects of the computer techniques in Japan. We hope that this edition will contribute to the development of this field.

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Ko, Yohan, Soohwan Kim, Hyunchoong Kim, and Kyoungwoo Lee. "Selective Code Duplication for Soft Error Protection on VLIW Architectures." Electronics 10, no. 15 (July 30, 2021): 1835. http://dx.doi.org/10.3390/electronics10151835.

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Very Long Instruction Word, or VLIW, architectures have received much attention in specific-purpose applications such as scientific computation, digital signal processing, and even safety-critical systems. Several compilation techniques for VLIW architectures have been proposed in order to improve the performance, but there is a lack of research to improve reliability against soft errors. Instruction duplication techniques have been proposed by exploiting unused instruction slots (i.e., NOPs) in VLIW architectures. All the instructions cannot be replicated without additional code lines. Additional code lines are required to increase the number of duplicated instructions in VLIW architectures. Our experimental results show that 52% performance overhead as compared to unprotected source code when we duplicate all the instructions. This considerable performance overhead can be inapplicable for resource-constrained embedded systems so that we can limit the number of additional NOP instructions for selective protection. However, the previous static scheme duplicates instructions just in sequential order. In this work, we propose packing-oriented duplication to maximize the number of duplicated instructions within the same peroformance overhead bounds. Our packing-oriented approach can duplicate up to 18% more instructions within the same performance overheads compared to the previous static duplication techniques.

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Vázquez-Castillo, Javier, Alejandro Castillo-Atoche, Roberto Carrasco-Alvarez, Omar Longoria-Gandara, and Jaime Ortegón-Aguilar. "FPGA-Based Hardware Matrix Inversion Architecture Using Hybrid Piecewise Polynomial Approximation Systolic Cells." Electronics 9, no. 1 (January 18, 2020): 182. http://dx.doi.org/10.3390/electronics9010182.

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The hardware of the matrix inversion architecture using QR decomposition with Givens Rotations (GR) and a back substitution (BS) block is required for many signal processing algorithms. However, the hardware of the GR algorithm requires the implementation of complex operations, such as the reciprocal square root (RSR), which is typically implemented using LookUp Table (LUT) and COordinate Rotation DIgital Computer (CORDICs), among others, conveying to either high-area consumption or low throughput. This paper introduces an Field-Programmable Gate Array (FPGA)-based full matrix inversion architecture using hybrid piecewise polynomial approximation systolic cells. In the design, a hybrid segmentation technique was incorporated for the implementation of piecewise polynomial systolic cells. This hybrid approach is composed by an external and internal segmentation, where the first is nonuniform and the second is uniform, fitting the curve shape of the complex functions achieving a better signal-quantization-to noise-ratio; furthermore, it improves the time performance and area resources. Experimental results reveal a well-balanced improvement in the design achieving high throughput and, hence, less resource utilization in comparison to state-of-the-art FPGA-based architectures. In our study, the proposed design achieves 7.51 Mega-Matrices per second for performing 4 × 4 matrix operations with a latency of 12 clock cycles; meanwhile, the hardware design requires only 1474 slice registers, 1458 LUTs in an FPGA Virtex-5 XC5VLX220T, and 1474 slice registers and 1378 LUTs when a FPGA Virtex-6 XC6VLX240T is used.

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Liu, Yin, and Keshab K. Parhi. "Linear-Phase Lattice FIR Digital Filter Architectures Using Stochastic Logic." Journal of Signal Processing Systems 90, no. 5 (January 25, 2017): 791–803. http://dx.doi.org/10.1007/s11265-017-1224-z.

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Huang, Zhen, Chengkang Li, Qiang Lv, Rijian Su, and Kaibo Zhou. "Automatic Recognition of Communication Signal Modulation Based on the Multiple-Parallel Complex Convolutional Neural Network." Wireless Communications and Mobile Computing 2021 (June 9, 2021): 1–11. http://dx.doi.org/10.1155/2021/5006248.

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This paper implements a deep learning-based modulation pattern recognition algorithm for communication signals using a convolutional neural network architecture as a modulation recognizer. In this paper, a multiple-parallel complex convolutional neural network architecture is proposed to meet the demand of complex baseband processing of all-digital communication signals. The architecture learns the structured features of the real and imaginary parts of the baseband signal through parallel branches and fuses them at the output according to certain rules to obtain the final output, which realizes the fitting process to the complex numerical mapping. By comparing and analyzing several commonly used time-frequency analysis methods, a time-frequency analysis method that can well highlight the differences between different signal modulation patterns is selected to convert the time-frequency map into a digital image that can be processed by a deep network. In order to fully extract the spatial and temporal characteristics of the signal, the CLP algorithm of the CNN network and LSTM network in parallel is proposed. The CNN network and LSTM network are used to extract the spatial features and temporal features of the signal, respectively, and the fusion of the two features as well as the classification is performed. Finally, the optimal model and parameters are obtained through the design of the modulation recognizer based on the convolutional neural network and the performance analysis of the convolutional neural network model. The simulation experimental results show that the improved convolutional neural network can produce certain performance gains in radio signal modulation style recognition. This promotes the application of machine learning algorithms in the field of radio signal modulation pattern recognition.

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Visalli, Giuseppe. "A Novel Coordinate Rotation Digital Computer Method for Energy and Latency Saving by Trigonometric Operations Spatial Locality Principle." Journal of Low Power Electronics 15, no. 4 (December 1, 2019): 338–50. http://dx.doi.org/10.1166/jolpe.2019.1619.

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In this work, we propose an approximate and energy-efficient CORDIC method, based on a trigonometric function spatial locality principle derived from benchmarks profiling. Successive sine/cosine computation requests cover more than 50% when the absolute phase difference is at most ten degrees. Consequently, this property suggests an optimized circuit implementation, both iterative or a succession of microrotation modules, where the last CORDIC requires fewer iterations, reducing the latency and the total energy budget at the same precision of two separate and independent instances. Thus, this simple design strategy allows significant area and energy dissipation in general-purpose VLSI architectures, but it introduces also dramatically optimizations in applicationspecific embedded systems used in the area of signal processing and radio frequency communication. In this contribution, we introduce a method, the hardware overhead and the energy budget per single cycle. Simulation results show the total energy saving in considered benchmarks is 40% in pipelined and iterative general purposes CORDIC. Furthermore, our application-specific systems (fast Fourier transform and digital oscillators for radiofrequency down conversions) show remarkable cycle savings when the successive sine/cosine computation requests are more than 70%. Finally, in this work, we extend the proposed approach to whichever phase difference less than 26.56° , as a variable for the second CORDIC number of angle rotations.

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Moroz, Leonid, Shinobu Nagayama, Taras Mykytiv, Ihor Kirenko, and Taras Boretskyy. "Simple Hybrid Scaling-Free CORDIC Solution for FPGAs." International Journal of Reconfigurable Computing 2014 (2014): 1–4. http://dx.doi.org/10.1155/2014/615472.

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COordinate Rotation DIgital Computer (CORDIC) is an effective method that is used in digital signal processing applications for computing various trigonometric, hyperbolic, linear, and transcendental functions. This paper presents the theoretical basis and practical implementation of circular (sine-cosine) CORDIC-based generator. Synthesis results of this generator based on Altera Stratix III FPGA (EP3SL340F1517C2) using Quartus II version 9.0 show that the proposed hybrid FPGA architecture significantly reduces latency (42% reduction) with a small area overhead, compared to the conventional version. The proposed algorithm has been simulated for sine and cosine function evaluation, and it has been verified that the accuracy is comparable with conventional algorithm.

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Assaad, Maher, and Mohammed H. Alser. "Design of an All-Digital Synchronized Frequency Multiplier Based on a Dual-Loop (D/FLL) Architecture." VLSI Design 2012 (September 18, 2012): 1–7. http://dx.doi.org/10.1155/2012/546212.

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This paper presents a new architecture for a synchronized frequency multiplier circuit. The proposed architecture is an all-digital dual-loop delay- and frequency-locked loops circuit, which has several advantages, namely, it does not have the jitter accumulation issue that is normally encountered in PLL and can be adapted easily for different FPGA families as well as implemented as an integrated circuit. Moreover, it can be used in supplying a clock reference for distributed digital processing systems as well as intra/interchip communication in system-on-chip (SoC). The proposed architecture is designed using the Verilog language and synthesized for the Altera DE2-70 development board. The experimental results validate the expected phase tracking as well as the synthesizing properties. For the measurement and validation purpose, an input reference signal in the range of 1.94–2.62 MHz was injected; the generated clock signal has a higher frequency, and it is in the range of 124.2–167.9 MHz with a frequency step (i.e., resolution) of 0.168 MHz. The synthesized design requires 330 logic elements using the above Altera board.

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Stobińska, M., A. Buraczewski, M. Moore, W. R. Clements, J. J. Renema, S. W. Nam, T. Gerrits, et al. "Quantum interference enables constant-time quantum information processing." Science Advances 5, no. 7 (July 2019): eaau9674. http://dx.doi.org/10.1126/sciadv.aau9674.

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It is an open question how fast information processing can be performed and whether quantum effects can speed up the best existing solutions. Signal extraction, analysis, and compression in diagnostics, astronomy, chemistry, and broadcasting build on the discrete Fourier transform. It is implemented with the fast Fourier transform (FFT) algorithm that assumes a periodic input of specific lengths, which rarely holds true. A lesser-known transform, the Kravchuk-Fourier (KT), allows one to operate on finite strings of arbitrary length. It is of high demand in digital image processing and computer vision but features a prohibitive runtime. Here, we report a one-step computation of a fractional quantum KT. The quantum d-nary (qudit) architecture we use comprises only one gate and offers processing time independent of the input size. The gate may use a multiphoton Hong-Ou-Mandel effect. Existing quantum technologies may scale it up toward diverse applications.

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Fazli, Saeid, and Lindsay Kleeman. "Sensor design and signal processing for an advanced sonar ring." Robotica 24, no. 4 (December 6, 2005): 433–46. http://dx.doi.org/10.1017/s0263574705002432.

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A conventional sonar ring measures the range to objects based on the first echo and is widely used in indoor mobile robots. In contrast, advanced sonar sensing can produce accurate range and bearing (incidence angle) measurements to multiple targets using multiple receivers and multiple echoes per each receiver at the expense of intensive computation. This paper presents an advanced sonar ring that employs a low receiver sample rate to achieve processing of 48 receiver channels at near real time repetition rates of 11.5 Hz. The sonar ring sensing covers 360 degrees around the robot for specular targets for ranges up to six metres, with simultaneously firing of all its 24 transmitters. Digital Signal Processing (DSP) techniques and interference rejection ideas are applied in this sensor to produce a fast and accurate sonar ring. Seven custom designed DSP boards process the receivers sampled at 250 kHz to maximize the speed of processing and to limit memory requirements. This paper presents the new sensor design, the hardware structure, the software architecture, and signal processing of the advanced sonar ring. Repeatability and accuracy of the measurements are tested to characterize the proposed sensor. Due to the low sample rate of 250 kHz, a problem called cycle hopping can occur. The paper presents a solution to cycle hopping and a new transmit coding based on pulse duration to differentiate neighbouring transmitters in the ring. Experimental data show the effectiveness of the designed sensor in indoor environments.

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Loy, D. Gareth. "Life and Times of the Samson Box." Computer Music Journal 37, no. 3 (September 2013): 26–48. http://dx.doi.org/10.1162/comj_a_00192.

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Peter Samson designed and built a real-time signal-processing computer for music applications in the 1970s. The Systems Concepts Digital Synthesizer (“Samson Box” for short) was installed at the Center for Computer Research in Music and Acoustics (CCRMA) at Stanford University in 1977, where it served for over a decade as the principal music generation system. It was an important landmark in the transition from general-purpose computers to real-time systems for music and audio, and helped set the stage for the sea change in the music industry from analog to digital technologies that began in the 1980s and continues at a rapid pace today. This article focuses on the historical context of the Samson Box, its development, its impact on the culture of CCRMA and the Stanford Artificial Intelligence Laboratory, its use for music research and composition at Stanford, and its role in the transformation of the music and audio industries from analog to digital practices. A list of compositions realized on the Samson Box is included, which shows that from 1978 to its decommissioning in 1992 it was used to create over 100 finished works, many of which were widely performed and were awarded prizes. A companion article provides a detailed architectural review and an interview with Pete Samson.

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Grguric, Andrej, Omar Khan, Ana Ortega-Gil, Evangelos K. Markakis, Konstantin Pozdniakov, Christos Kloukinas, Alejandro M. Medrano-Gil, Eugenio Gaeta, Giuseppe Fico, and Konstantina Koloutsou. "Reference Architectures, Platforms, and Pilots for European Smart and Healthy Living—Analysis and Comparison." Electronics 10, no. 14 (July 6, 2021): 1616. http://dx.doi.org/10.3390/electronics10141616.

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Motivated by the aging trend, much effort is being invested into implementing ICT (Information and Communications Technology)-enabled systems to provide a better quality of life and support the independent living of older people. As a result, many systems, often labeled as eHealth or AAL (Ambient/Active Assisted Living), were developed over the years. In creating such systems, which very often serve various needs, different architectures have emerged. This work focuses on analyzing and comparing the work and architectures from seven (six of which are in progress) EU-funded healthcare projects, with a total budget of 126MEUR in which we participate. After establishing the theoretical foundation by defining core concepts, we give a brief background on architectures in eHealth and AAL. We elaborate on the chosen analysis method based on three established healthcare and AAL taxonomies we identified by performing a literature survey and the selected Reference Architecture Model (RAM). Since there is no standard way of describing architectures in the eHealth and AAL domain, we conducted the online survey during August and September 2020 and identified CREATE-IoT 3D RAM as the most appropriate option. We present a classification of selected projects based on established taxonomies and map projects’ architectures to CREATE-IoT 3D RAM, which we also propose as standard RAM for future digital healthcare and AAL projects. During our analysis, we identify the most common types of assistance: communication support, reminders, monitoring, and guidance to address health and communication issues. We conclude that proper ecosystems are critical for lowering entry barriers and facilitating sustainable solutions for smart and healthy living.

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Jiang, Xiaochang, Jie Wu, and Yubo Ma. "Synchronous Mixing Architecture for Digital Bandwidth Interleaving Sampling System." Electronics 10, no. 16 (August 18, 2021): 1998. http://dx.doi.org/10.3390/electronics10161998.

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By using a mixer to down-convert the high frequency components of a signal, digital bandwidth interleaving (DBI) technology can simultaneously increase the sampling rate and bandwidth of the sampling system, compared to the time-interleaved and hybrid filter bank. However, the software and hardware of the classical architecture are too complicated, which also leads to poor performance. In particular, the pilot tone used to synchronize the analog and digital local oscillators (LO) of mixers intermodulates with the high frequency components of the signal, resulting in larger spurs. This paper proposes a synchronous mixing architecture for the DBI system, where the LO of the analog mixer is synchronized with the sampling clock of the analog-to-digital converter. Its hardware and software are simplified—the pilot tone used to synchronize the LOs can also be removed. An evaluation platform with a sampling rate of 250 MSPS is implemented to illustrate the performance of the new architecture. The result shows that the spurious free dynamic range (SFDR) of the new architecture is more than 20 dB higher than the classical one in a high frequency range. The rise time of a step signal of the new architecture is 0.578 ± 0.070 ns faster than the classical one with the same bandwidth (90 MHz).

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Essayeh, Chaimaa, Mohammed Raiss El-Fenni, Hamza Dahmouni, and Mohamed Aymane Ahajjam. "Energy Management Strategies for Smart Green MicroGrid Systems: A Systematic Literature Review." Journal of Electrical and Computer Engineering 2021 (February 24, 2021): 1–21. http://dx.doi.org/10.1155/2021/6675975.

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Having neither precise definition nor a commonly accepted scope, the term “MicroGrid” tends to be used differently across researchers and practitioners alike. The management of energy usage within a microgrid is one of the topics that was handled from numerous perspectives. This study presents systematic literature review (SLR) of research on architectures and energy management techniques for microgrids, providing an aggregated up-to-date catalogue of solutions suggested by the scientific community. The SLR incorporated 45 papers selected according to inclusion/exclusion criteria and defined a priori. The selection process was based on an automated search and covered three known digital libraries. The extraction process covers three main questions. (i) The architectures of microgrids including their components, their bus configuration, and the adopted utility grid policy. (ii) The employed methods to ensure an optimal usage of energy under uncertainty. (iii) The confronted challenges and constraints of the suggested strategies. The findings of this SLR indicate a great diversity of methods and a rich background. Finally, the SLR suggests that future research should take into account the uncertainty aspect relating to energy management rather than the direct use of historical data as it is commonly done in most research papers. A sensitivity analysis should be provided in the latter case.

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Kumar, Thanikodi Manoj, Kasarla Satish Reddy, Stefano Rinaldi, Bidare Divakarachari Parameshachari, and Kavitha Arunachalam. "A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application." Electronics 10, no. 16 (August 21, 2021): 2023. http://dx.doi.org/10.3390/electronics10162023.

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Nowadays, a huge amount of digital data is frequently changed among different embedded devices over wireless communication technologies. Data security is considered an important parameter for avoiding information loss and preventing cyber-crimes. This research article details the low power high-speed hardware architectures for the efficient field programmable gate array (FPGA) implementation of the advanced encryption standard (AES) algorithm to provide data security. This work does not depend on the Look-Up Table (LUTs) for the implementation the SubBytes and InvSubBytes stages of transformations of the AES encryption and decryption; this new architecture uses combinational logical circuits for implementing SubBytes and InvSubBytes transformation. Due to the elimination of LUTs, unwanted delays are eliminated in this architecture and a subpipelining structure is introduced for improving the speed of the AES algorithm. Here, modified positive polarity reed muller (MPPRM) architecture is inserted to reduce the total hardware requirements, and comparisons are made with different implementations. With MPPRM architecture introduced in SubBytes stages, an efficient mixcolumn and invmixcolumn architecture that is suited to subpipelined round units is added. The performances of the proposed AES-MPPRM architecture is analyzed in terms of number of slice registers, flip flops, number of slice LUTs, number of logical elements, slices, bonded IOB, operating frequency and delay. There are five different AES architectures including LAES, AES-CTR, AES-CFA, AES-BSRD, and AES-EMCBE. The LUT of the AES-MPPRM architecture designed in the Spartan 6 is reduced up to 15.45% when compared to the AES-BSRD.

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Schroeder, Jim. "Current results in fast algorithm computational complexity analysis, computer architecture design, and VLSI hardware advances with applications to digital signal processing." Digital Signal Processing 1, no. 1 (January 1991): 27–30. http://dx.doi.org/10.1016/1051-2004(91)90091-x.

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Liang, Wandi, Zixiong Wang, Guangyu Lu, and Yang Jiang. "A Compressed Sensing Recovery Algorithm Based on Support Set Selection." Electronics 10, no. 13 (June 25, 2021): 1544. http://dx.doi.org/10.3390/electronics10131544.

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The theory of compressed sensing (CS) has shown tremendous potential in many fields, especially in the signal processing area, due to its utility in recovering unknown signals with far lower sampling rates than the Nyquist frequency. In this paper, we present a novel, optimized recovery algorithm named supp-BPDN. The proposed algorithm executes a step of selecting and recording the support set of original signals before using the traditional recovery algorithm mostly used in signal processing called basis pursuit denoising (BPDN). We proved mathematically that even in a noise-affected CS system, the probability of selecting the support set of signals still approaches 1, which means supp-BPDN can maintain good performance in systems in which noise exists. Recovery results are demonstrated to verify the effectiveness and superiority of supp-BPDN. Besides, we set up a photonic-enabled CS system realizing the reconstruction of a two-tone signal with a peak frequency of 350 MHz through a 200 MHz analog-to-digital converter (ADC) and a signal with a peak frequency of 1 GHz by a 500 MHz ADC. Similarly, supp-BPDN showed better reconstruction results than BPDN.

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Journal articles on the topic 'Computer architectures; Digital signal processing'

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