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Relevant bibliographies by topics / Computer hardware

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Academic literature on the topic 'Computer hardware'

Author: Grafiati

Published: 4 June 2021

Last updated: 11 June 2025

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Journal articles on the topic "Computer hardware"

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Cage, Gary W. "Computer Hardware." Dermatologic Clinics 4, no. 4 (1986): 533–43. http://dx.doi.org/10.1016/s0733-8635(18)30781-2.

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De Vos, Alexis. "Reversible Computer Hardware." Electronic Notes in Theoretical Computer Science 253, no. 6 (2010): 17–22. http://dx.doi.org/10.1016/j.entcs.2010.02.003.

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Staudhammer, J. "Computer graphics hardware." IEEE Computer Graphics and Applications 11, no. 1 (1991): 42–44. http://dx.doi.org/10.1109/38.67698.

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Wijayana, Yenita. "SISTEM PAKAR KERUSAKAN HARDWARE KOMPUTER DENGAN METODE BACKWARD CHAINING BERBASIS WEB." MEDIA ELEKTRIKA 12, no. 2 (2020): 99. http://dx.doi.org/10.26714/me.12.2.2019.99-107.

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Computers are a major need to support human performance. Computers also often damage the hardware such as processor, memory, mouse, keyboard, hard disk, optical drive, monitor. Hardware damage is still rarely known by computer users. In this final project aims to build a knowledge-based system to diagnose damage to computer hardware or hardware in the form of websites using PHP using the waterfall model and the backward chaining method. Making a Computer Damage Expert System with Web-Based Backward Chaining Method is expected to be able to help computer users to solve problems on computer hardware, so users can save on technician costs and can save time.

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AL Hwaitat, Ahmad Kamel, Ameen Shaheen, Khalid Adhim, Enad N. Arkebat, and Aezz Aldain AL Hwiatat. "Computer Hardware Components Ontology." Modern Applied Science 12, no. 3 (2018): 35. http://dx.doi.org/10.5539/mas.v12n3p35.

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A computer system consists of Hardware components that integrate with each other .The purpose of this paper is to create the hardware components of a computer system by formalizing a number of concepts that represent the knowledge of this dolman. Description logic anddefensible logic are used in this paper to achieve our goal.

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Mitta, Sridhar. "Technology for Computer Hardware." IETE Technical Review 4, no. 9 (1987): 349–51. http://dx.doi.org/10.1080/02564602.1987.11438159.

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Tsuchiya, Mas. "Computer hardware/software architecture." Microprocessors and Microsystems 11, no. 4 (1987): 236. http://dx.doi.org/10.1016/0141-9331(87)90383-8.

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Kroon, Joseph R., and Robert F. Strayer. "A Computer Hardware Primer." Journal - American Water Works Association 78, no. 8 (1986): 30–35. http://dx.doi.org/10.1002/j.1551-8833.1986.tb05795.x.

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Król, Karol. "Hardware Heritage—Briefcase-Sized Computers." Heritage 4, no. 3 (2021): 2237–52. http://dx.doi.org/10.3390/heritage4030126.

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The computer industry was a vivid place in the 1980s. IT systems and technologies thrived, and the market offered ever better, smaller, and more useful machines. Innovative technical solutions or intelligent designs that satisfied customers’ needs are often listed as computer hardware milestones. Consequently, they became a permanent part of the computerisation history and can be considered hardware heritage artefacts. The purpose of the paper is to analyse the usability of selected portable computer systems. The foundation of the work is a literature review that includes technical specifications, industry reviews, and research papers. Archival materials were obtained from the Internet Archive. Studies have revealed that the main problems design engineers of portable computers had to tackle in the 1980s were the reduction of mass and size of the computer system, portable power (self-power), and the quality of the displayed image.

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Liu, Qian. "Hardware-Free Network Internals Exploration." International Journal of Innovative Teaching and Learning in Higher Education 5, no. 1 (2024): 1–16. http://dx.doi.org/10.4018/ijitlhe.339002.

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In undergraduate computer networking courses, the ideal scenario involves demonstrating network communications with multiple interconnected computers and a packet sniffer tool. However, practical challenges arise when attempting hands-on exercises, such as accessing or reconfiguring physical computers for online networking practice. Additionally, certain network concepts, like routing and switching, are typically discussed theoretically due to the limitations of observing external network packet transfers and the constraints faced by institutions in maintaining the necessary hardware for hands-on practice. This paper introduces a simulation-based approach to facilitate the teaching and learning of computer networking internals in an online environment, eliminating the need for dedicated hardware devices. The paper outlines various simulation activities and experiments designed to assist instructors in teaching and enable students to explore these internal networking concepts effectively.

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Dissertations / Theses on the topic "Computer hardware"

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Tarnoff, David. "Episode 1.1 – The Importance of Hardware Design." Digital Commons @ East Tennessee State University, 2020. https://dc.etsu.edu/computer-organization-design-oer/1.

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Rhodes, Daniel Thomas. "Hardware accelerated computer graphics algorithms." Thesis, Nottingham Trent University, 2008. http://irep.ntu.ac.uk/id/eprint/201/.

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The advent of shaders in the latest generations of graphics hardware, which has made consumer level graphics hardware partially programmable, makes now an ideal time to investigate new graphical techniques and algorithms as well as attempting to improve upon existing ones. This work looks at areas of current interest within the graphics community such as Texture Filtering, Bump Mapping and Depth of Field simulation. These are all areas which have enjoyed much interest over the history of computer graphics but which provide a great deal of scope for further investigation in the light of recent hardware advances. A new hardware implementation of a texture filtering technique, aimed at consumer level hardware, is presented. This novel technique utilises Fourier space image filtering to reduce aliasing. Investigation shows that the technique provides reduced levels of aliasing along with comparable levels of detail to currently popular techniques. This adds to the community's knowledge by expanding the range of techniques available, as well as increasing the number of techniques which offer the potential for easy integration with current consumer level graphics hardware along with real-time performance. Bump mapping is a long-standing and well understood technique. Variations and extensions of it have been popular in real-time 3D computer graphics for many years. A new hardware implementation of a technique termed Super Bump Mapping (SBM) is introduced. Expanding on the work of Cant and Langensiepen [1], the SBM technique adopts the novel approach of using normal maps which supply multiple vectors per texel. This allows the retention of much more detail and overcomes some of the aliasing deficiencies of standard bump mapping caused by the standard single vector approach and the non-linearity of the bump mapping process. A novel depth of field algorithm is proposed, which is an extension of the authors previous work [2][3][4]. The technique is aimed at consumer level hardware and attempts to raise the bar for realism by providing support for the 'see-through' effect. This effect is a vital factor in the realistic appearance of simulated depth of field and has been overlooked in real time computer graphics due to the complexities of an accurate calculation. The implementation of this new algorithm on current consumer level hardware is investigated and it is concluded that while current hardware is not yet capable enough, future iterations will provide the necessary functional and performance increases.

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Hemingway, Peter. "Computer display architecture." Thesis, University of Cambridge, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.256743.

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Nagaonkar, Yajuvendra. "FPGA-based Experiment Platform for Hardware-Software Codesign and Hardware Emulation." Diss., CLICK HERE for online access, 2006. http://contentdm.lib.byu.edu/ETD/image/etd1294.pdf.

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Mukre, Prakash. "Hardware accelerator for DNA code word searching." Diss., Online access via UMI:, 2008.

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Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Electrical and Computer Engineering, 2008.<br>Includes bibliographical references.

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Bissland, Lesley. "Hardware and software aspects of parallel computing." Thesis, University of Glasgow, 1996. http://theses.gla.ac.uk/3953/.

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Part 1 (Chapters 2,3 and 4) is concerned with the development of hardware for multiprocessor systems. Some of the concepts used in digital hardware design are introduced in Chapter 2. These include the fundamentals of digital electronics such as logic gates and flip-flops as well as the more complicated topics of rom and programmable logic. It is often desirable to change the network topology of a multiprocessor machine to suit a particular application. The third chapter describes a circuit switching scheme that allows the user to alter the network topology prior to computation. To achieve this, crossbar switches are connected to the nodes, and the host processor (a PC) programs the crossbar switches to make the desired connections between the nodes. The hardware and software required for this system is described in detail. Whilst this design allows the topology of a multiprocessor system to be altered prior to computation, the topology is still fixed during program run-time. Chapter 4 presents a system that allows the topology to be altered during run-time. The nodes send connection requests to a control processor which programs a crossbar switch connected to the nodes. This system allows every node in a parallel computer to communicate directly with every other node. The hardware interface between the nodes and the control processor is discussed in detail, and the software on the control processor is also described. Part 2 (Chapters 5 and 6) of this thesis is concerned with the parallelisation of a large molecular mechanics program. Chapter 5 describes the fundamentals of molecular mechanics such as the steric energy equation and its components, force field parameterisation and energy minimisation. The implementation of a novel programming (COMFORT) and hardware (the BB08) environment into a parallel molecular mechanics (MM) program is presented in Chapter 6. The structure of the sequential version of the MM program is detailed, before discussing the implementation of the parallel version using COMFORT and the BB08.

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Chilingirian, Berj Krikor. "Hashing hardware : identifying hardware during boot-time system verification." Thesis, Massachusetts Institute of Technology, 2017. http://hdl.handle.net/1721.1/112837.

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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Cataloged from student-submitted PDF version of thesis.<br>Includes bibliographical references (pages 85-90).<br>Modern systems measure the software loaded at boot-time to ensure the machine starts in a trusted state. Such measurements, however, do not include any information about the underlying hardware of the machine. Recent DRAM-based attacks and the growing complexity of the supply chain attest to the importance of measuring hardware at boot. In this thesis, we propose a technique for designing measurement schemes for hardware components. We then apply this technique to designing and implementing a hardware measurement scheme for DRAM on a real system without hardware modifications. Finally, we evaluate our DRAM hardware measurement scheme and demonstrate that it achieves 89% accuracy in mapping a DRAM measurement to the manufacturing process from which that DRAM was produced.<br>by Berj Krikor Chilingirian.<br>M. Eng.

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Hawkins, Stuart Philip. "Video replay in computer animation." Thesis, University of Cambridge, 1990. https://www.repository.cam.ac.uk/handle/1810/250977.

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Ray, Gavin Peter. "Computer network analysis and optimisation." Thesis, University of Plymouth, 1993. http://hdl.handle.net/10026.1/1639.

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This thesis presents a study and analysis of the major influences on network cost and their related performance. New methods have been devised to find solutions to network optimisation problems particular to the AT&T ISTEL networks in Europe and these are presented together with examples of their successful commercial application. Network performance is seen by the user in terms of network availability and traffic delay times. The network performance is influenced by many parameters, the dominating influences typically being the number of users accessing the network, the type of traffic demands they place upon it and the particular network configuration itself. The number of possible network configurations available to a network designer is vast if the full range of currently available equipment is taken into account. The aim of this research has been to assist in the selection of most suitable network designs for optimum performance and cost. This thesis looks at the current differing network technologies, their performance characteristics and the issues pertinent to any network design and optimisation procedures. A distinction is made between the network equipment providing user 'access' and that which constitutes the cross country, or *core\ data transport medium. This partitioning of the problem is exploited with the analysis concentrating on each section separately. The access side of the AT&T ISTEL - UK network is used as a basis for an analysis of the general access network. The aim is to allow network providers to analyse the root cause of excessive delay problems and find where small adjustments to access configurations might lead to real performance improvements from a user point of view. A method is developed to allow statistical estimates of performance and quality of service for typical access network configurations. From this a general method for the optimisation of cost expenditure and performance improvement is proposed. The optimisation of both circuit switched and packet switched computer networks is shown to be difficult and is normally tackled by the use of complex procedures on mainframe computers. The new work carried out in this study takes a fresh look at the basic properties of networks in order to develop a new heuristic method for the design and optimisation of circuit switched core networks on a personal computer platform. A fully functional design system was developed that implements time division multiplexed core network design. The system uses both a new heuristic method for improving the quality of the designs and a new 'speed up' algorithm for reducing times to find feasible routes, thereby dramatically improving overall design times. The completed system has since been used extensively to assist in the design of commercial networks across Europe.

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Schoepke, Olaf S. "Dense instruction set computer architecture." Thesis, University of Bath, 1992. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.332540.

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Books on the topic "Computer hardware"

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H, Fleer Charles, ed. Computer hardware. McGraw-Hill, 1989.

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Dominic, Fenn, and Key Note Publications, eds. Computer hardware. 5th ed. Key Note, 2003.

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Donna, Jones, and Key Note Ltd, eds. Computer hardware. Key Note Ltd, 1996.

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Jacob, Howard, and Key Note Publications, eds. Computer hardware. 4th ed. Key Note, 2001.

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Isla, Gower, and Key Note Publications, eds. Computer hardware. 6th ed. Key Note, 2005.

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Emma, Clarke, and Key Note Publications, eds. Computer hardware. 3rd ed. Key Note, 1999.

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Gorsline, George W. Computer organization: Hardware/software. 2nd ed. Prentice-Hall, 1986.

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Gorsline, G. W. Computer organization: Hardware/software. 2nd ed. Prentice-Hall, 1986.

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Mano, M. Morris. Computer engineering: Hardware design. Prentice Hall, 1988.

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Clements, Alan. Principles of computer hardware. 4th ed. Oxford University Press, 2006.

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Book chapters on the topic "Computer hardware"

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Smith, A. J. "Computer Hardware." In Computers and Quantity Surveyors. Macmillan Education UK, 1989. http://dx.doi.org/10.1007/978-1-349-10857-2_2.

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Stahlknecht, Peter, Frank Hohmann, Sven Küchler, Natascha Ruske, and Monica Sawhney. "Computer-Hardware." In Arbeitsbuch Wirtschaftsinformatik. Springer Berlin Heidelberg, 1996. http://dx.doi.org/10.1007/978-3-662-05814-5_2.

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Stahlknecht, Peter, and Ulrich Hasenkamp. "Computer-Hardware." In Springer-Lehrbuch. Springer Berlin Heidelberg, 1997. http://dx.doi.org/10.1007/978-3-662-06895-3_2.

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Stahlknecht, Peter. "Computer-Hardware." In Einführung in die Wirtschaftsinformatik. Springer Berlin Heidelberg, 1995. http://dx.doi.org/10.1007/978-3-662-06896-0_2.

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Stahlnecht, Peter. "Computer-Hardware." In Springer-Lehrbuch. Springer Berlin Heidelberg, 1993. http://dx.doi.org/10.1007/978-3-662-06897-7_2.

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Stahlknecht, Peter. "Computer-Hardware." In Springer-Lehrbuch. Springer Berlin Heidelberg, 1991. http://dx.doi.org/10.1007/978-3-662-06898-4_2.

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Stahlknecht, Peter. "Computer-Hardware." In Springer-Lehrbuch. Springer Berlin Heidelberg, 1989. http://dx.doi.org/10.1007/978-3-662-06899-1_2.

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Stahlknecht, Peter. "Computer-Hardware." In Heidelberger Taschenbücher. Springer Berlin Heidelberg, 1987. http://dx.doi.org/10.1007/978-3-662-06900-4_2.

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Stahlknecht, Peter. "Computer-Hardware." In Heidelberger Taschenbücher. Springer Berlin Heidelberg, 1985. http://dx.doi.org/10.1007/978-3-662-06901-1_2.

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Stahlknecht, Peter, and Ulrich Hasenkamp. "Computer-Hardware." In Springer-Lehrbuch. Springer Berlin Heidelberg, 1999. http://dx.doi.org/10.1007/978-3-662-06903-5_2.

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Conference papers on the topic "Computer hardware"

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Clemens, M. "Future of computer hardware." In IET 8th International Conference on Computation in Electromagnetics (CEM 2011). IET, 2011. http://dx.doi.org/10.1049/cp.2011.0007.

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Korenek, J. "Hardware acceleration in computer networks." In 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE, 2013. http://dx.doi.org/10.1109/ddecs.2013.6549780.

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Miller, N. L., and S. F. Quigley. "A reconfigurable integrated circuit for high performance computer arithmetic." In IEE Colloquium Evolvable Hardware Systems. IEE, 1998. http://dx.doi.org/10.1049/ic:19980206.

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Hoffman, Caio, Mario Cortes, Diego F. Aranha, and Guido Araujo. "Computer security by hardware-intrinsic authentication." In 2015 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS). IEEE, 2015. http://dx.doi.org/10.1109/codesisss.2015.7331377.

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Wu, Jerry, Harold Szu, Yuechen Chen, Ran Guo, and Xixi Gu. "Hardware enhance of brain computer interfaces." In SPIE Sensing Technology + Applications, edited by Harold H. Szu, Liyi Dai, and Yufeng Zheng. SPIE, 2015. http://dx.doi.org/10.1117/12.2184654.

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Hoffman, Caio, Diego F. Aranha, Mario Lúcio Côrtes, and Guido Costa Souza de Araújo. "Computer Security by Hardware-Intrinsic Authentication." In Anais Estendidos do Simpósio Brasileiro de Segurança da Informação e de Sistemas Computacionais. Sociedade Brasileira de Computação - SBC, 2020. http://dx.doi.org/10.5753/sbseg_estendido.2020.19264.

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The Internet of Things (IoT) has brought evident security concerns. New solutions in security for IoT will need to reduce the dependency on nonvolatile memory for key storage, promote easier means to uniquely identify billions of devices, etc. Physical Unclonable Functions (PUFs) have been adopted as the future for key derivation and hardware fingerprinting. This work presents CSHIA: a new computer architecture that takes into account limitations and strengths of PUFs to provide code and data integrity and authenticity in a seamless design that does not demand changes in processors microarchitecture or software. We describe and analyze a full-fledged FPGA deployment of the architecture and consider attack scenarios, including side-channel attacks on PUFs.

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Tyanev, Dimitar, and Yulka Petkova. "Hardware Divider." In CompSysTech'18: 19th International Conference on Computer Systems and Technologies. ACM, 2018. http://dx.doi.org/10.1145/3274005.3274009.

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Zavala, Antonio H., Jorge Avante R., Quetzalcoatl Duarte R., and J. David Valencia P. "RISC-based architecture for computer hardware introduction." In 2011 3rd International Conference on Computer Research and Development (ICCRD). IEEE, 2011. http://dx.doi.org/10.1109/iccrd.2011.5763964.

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Shanshan, Li, and Liu Weidong. "THINPAD Experimental Platform for Computer Hardware Experiment." In 2019 14th International Conference on Computer Science & Education (ICCSE). IEEE, 2019. http://dx.doi.org/10.1109/iccse.2019.8845431.

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Jackson, Sue. "Editing computer hardware procedures for multimedia presentation." In the 19th annual international conference. ACM Press, 2001. http://dx.doi.org/10.1145/501516.501530.

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Reports on the topic "Computer hardware"

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Elesina, S. I. Computer hardware. OFERNIO, 2018. http://dx.doi.org/10.12731/ofernio.2018.23687.

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Klymenko, Mykola V., and Andrii M. Striuk. Development of software and hardware complex of GPS-tracking. CEUR Workshop Proceedings, 2021. http://dx.doi.org/10.31812/123456789/4430.

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The paper considers the typical technical features of GPS-tracking systems and their development, as well as an analysis of existing solutions to the problem. Mathematical models for the operation of hardware and software of this complex have been created. An adaptive user interface has been developed that allows you to use this complex from a smartphone or personal computer. Methods for displaying the distance traveled by a moving object on an electronic map have been developed. Atmega162-16PU microcontroller software for GSM module and GPS receiver control has been developed. A method of data transfer from a GPS tracker to a web server has been developed. Two valid experimental samples of GPS-trackers were made and tested in uncertain conditions. The GPS-tracking software and hardware can be used to monitor the movement of moving objects that are within the coverage of GSM cellular networks.

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Wu, Sau Lan. Application of Quantum Machine Learning to High Energy Physics Analysis at LHC using IBM Quantum Computer Simulators and IBM Quantum Computer Hardware. Office of Scientific and Technical Information (OSTI), 2022. http://dx.doi.org/10.2172/1971973.

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Hatcher, Donald J., Terry L. DeVietti, and John A. D'Andrea. Computer Software and Hardware to Determine Contrast Sensitivity Using Three Methods: Tracking, Limits, and Constant Stimuli. Defense Technical Information Center, 1992. http://dx.doi.org/10.21236/ada265168.

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Current, W., P. Hurst, G. Ford, E. Shieh, I. Agi, and C. Nguyen. Radon transform computer'' and real-time multi-dimensional processing hardware designs'': Research activities, appendix 1 and 2. Office of Scientific and Technical Information (OSTI), 1989. http://dx.doi.org/10.2172/7184755.

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Oleksiuk, Vasyl P., and Olesia R. Oleksiuk. Exploring the potential of augmented reality for teaching school computer science. [б. в.], 2020. http://dx.doi.org/10.31812/123456789/4404.

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The article analyzes the phenomenon of augmented reality (AR) in education. AR is a new technology that complements the real world with the help of computer data. Such content is tied to specific locations or activities. Over the last few years, AR applications have become available on mobile devices. AR becomes available in the media (news, entertainment, sports). It is starting to enter other areas of life (such as e-commerce, travel, marketing). But education has the biggest impact on AR. Based on the analysis of scientific publications, the authors explored the possibilities of using augmented reality in education. They identified means of augmented reality for teaching computer science at school. Such programs and services allow students to observe the operation of computer systems when changing their parameters. Students can also modify computer hardware for augmented reality objects and visualize algorithms and data processes. The article describes the content of author training for practicing teachers. At this event, some applications for training in AR technology were considered. The possibilities of working with augmented reality objects in computer science training are singled out. It is shown that the use of augmented reality provides an opportunity to increase the realism of research; provides emotional and cognitive experience. This all contributes to engaging students in systematic learning; creates new opportunities for collaborative learning, develops new representations of real objects.

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Dufur and Chapman. PR-325-05216-R01 Turbocharger Performance Monitoring. Pipeline Research Council International, Inc. (PRCI), 2008. http://dx.doi.org/10.55274/r0010002.

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Turbocharger performance, especially on SIP-call engines, remains essentially unmeasured even though tracking information over time would provide critical information to help field engineers lower their engine emissions as well as the cost of operations. In 2006, with the assistance of funding from the Pipeline Research Council International Inc., ScavengeTech LLC developed and field tested a turbocharger monitoring system that consisted of a set of analog sensors to measure key turbocharger performance parameters and hardware to interface the sensor outputs to a computer. The collected data was then analyzed via a series of spreadsheets that normalized the data and trended it over time. While successfully demonstrated in the field, the hardware system was large and expensive. The anticipated sales price of $25,000 was outside the price point for widespread adoption by the industry.

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Begg, John, and Kenneth Bernstein. An Analysis of Costs of Computer Based Training Hardware and Courseware Development for the Model Training Program for Reserve Component Units. Defense Technical Information Center, 1986. http://dx.doi.org/10.21236/ada172572.

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Dufur and Chapman. PR-325-07205-R01 Development of a Turbocharger Monitoring System. Pipeline Research Council International, Inc. (PRCI), 2008. http://dx.doi.org/10.55274/r0010771.

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Turbocharger performance, especially on SIP-call engines, remains essentially unmeasured even though tracking information over time would provide critical information to help field engineers lower their engine emissions as well as the cost of operations. In 2006, with the assistance of funding from the Pipeline Research Council International Inc., ScavengeTech LLC developed and field tested a turbocharger monitoring system that consisted of a set of analog sensors to measure key turbocharger performance parameters and hardware to interface the sensor outputs to a computer. The collected data was then analyzed via a series of spreadsheets that normalized the data and trended it over time. While successfully demonstrated in the field, the hardware system was large and expensive. The anticipated sales price of $25,000 was outside the price point for widespread adoption by the industry. The objective of this project was to modify the turbocharger monitoring system to: 1) incorporate digital sensors, 2) decrease the footprint of the system, and 3) integrate the collected data and identified algorithms into one software package.

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Sokolovsky, Dmitry, Sergey Sokolov, and Alexey Rezaykin. e-learning course "Informatics". SIB-Expertise, 2024. http://dx.doi.org/10.12731/er0785.29012024.

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The e-learning course "Informatics" is compiled in accordance with the requirements of the Federal State Educational Standard of Higher Education in the specialty 33.05.01 Pharmacy (specialty level), approved by Order of the Ministry of Education and Science of the Russian Federation dated August 11, 2016 No. 1037, and taking into account the requirements of the professional standard 02.006 "Pharmacist", approved by order of the Ministry of Labor and Social Protection No. 91n of the Russian Federation dated March 9, 2016. The purpose of the course is to master the necessary amount of theoretical and practical knowledge in computer science for graduates to master competencies in accordance with the Federal State Educational Standard of Higher Education, capable and ready to perform the work functions required by the professional standard. Course objectives: to provide knowledge about the rules of working with spreadsheets; to provide knowledge about working in medical information systems and the Internet information and telecommunications network; to provide skills in working with computer science software and hardware used at various stages of obtaining and analyzing biomedical information; to learn how to use the knowledge gained to solve problems of pharmaceutical and biomedical content. The labor intensity of the course is 72 hours. The course consists of 12 didactic units.

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