Dissertations / Theses: 'Computer hardware'

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Tarnoff, David. "Episode 1.1 – The Importance of Hardware Design." Digital Commons @ East Tennessee State University, 2020. https://dc.etsu.edu/computer-organization-design-oer/1.

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Rhodes, Daniel Thomas. "Hardware accelerated computer graphics algorithms." Thesis, Nottingham Trent University, 2008. http://irep.ntu.ac.uk/id/eprint/201/.

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The advent of shaders in the latest generations of graphics hardware, which has made consumer level graphics hardware partially programmable, makes now an ideal time to investigate new graphical techniques and algorithms as well as attempting to improve upon existing ones. This work looks at areas of current interest within the graphics community such as Texture Filtering, Bump Mapping and Depth of Field simulation. These are all areas which have enjoyed much interest over the history of computer graphics but which provide a great deal of scope for further investigation in the light of recent hardware advances. A new hardware implementation of a texture filtering technique, aimed at consumer level hardware, is presented. This novel technique utilises Fourier space image filtering to reduce aliasing. Investigation shows that the technique provides reduced levels of aliasing along with comparable levels of detail to currently popular techniques. This adds to the community's knowledge by expanding the range of techniques available, as well as increasing the number of techniques which offer the potential for easy integration with current consumer level graphics hardware along with real-time performance. Bump mapping is a long-standing and well understood technique. Variations and extensions of it have been popular in real-time 3D computer graphics for many years. A new hardware implementation of a technique termed Super Bump Mapping (SBM) is introduced. Expanding on the work of Cant and Langensiepen [1], the SBM technique adopts the novel approach of using normal maps which supply multiple vectors per texel. This allows the retention of much more detail and overcomes some of the aliasing deficiencies of standard bump mapping caused by the standard single vector approach and the non-linearity of the bump mapping process. A novel depth of field algorithm is proposed, which is an extension of the authors previous work [2][3][4]. The technique is aimed at consumer level hardware and attempts to raise the bar for realism by providing support for the 'see-through' effect. This effect is a vital factor in the realistic appearance of simulated depth of field and has been overlooked in real time computer graphics due to the complexities of an accurate calculation. The implementation of this new algorithm on current consumer level hardware is investigated and it is concluded that while current hardware is not yet capable enough, future iterations will provide the necessary functional and performance increases.

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Hemingway, Peter. "Computer display architecture." Thesis, University of Cambridge, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.256743.

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Nagaonkar, Yajuvendra. "FPGA-based Experiment Platform for Hardware-Software Codesign and Hardware Emulation." Diss., CLICK HERE for online access, 2006. http://contentdm.lib.byu.edu/ETD/image/etd1294.pdf.

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Mukre, Prakash. "Hardware accelerator for DNA code word searching." Diss., Online access via UMI:, 2008.

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Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Electrical and Computer Engineering, 2008.
Includes bibliographical references.

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Bissland, Lesley. "Hardware and software aspects of parallel computing." Thesis, University of Glasgow, 1996. http://theses.gla.ac.uk/3953/.

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Part 1 (Chapters 2,3 and 4) is concerned with the development of hardware for multiprocessor systems. Some of the concepts used in digital hardware design are introduced in Chapter 2. These include the fundamentals of digital electronics such as logic gates and flip-flops as well as the more complicated topics of rom and programmable logic. It is often desirable to change the network topology of a multiprocessor machine to suit a particular application. The third chapter describes a circuit switching scheme that allows the user to alter the network topology prior to computation. To achieve this, crossbar switches are connected to the nodes, and the host processor (a PC) programs the crossbar switches to make the desired connections between the nodes. The hardware and software required for this system is described in detail. Whilst this design allows the topology of a multiprocessor system to be altered prior to computation, the topology is still fixed during program run-time. Chapter 4 presents a system that allows the topology to be altered during run-time. The nodes send connection requests to a control processor which programs a crossbar switch connected to the nodes. This system allows every node in a parallel computer to communicate directly with every other node. The hardware interface between the nodes and the control processor is discussed in detail, and the software on the control processor is also described. Part 2 (Chapters 5 and 6) of this thesis is concerned with the parallelisation of a large molecular mechanics program. Chapter 5 describes the fundamentals of molecular mechanics such as the steric energy equation and its components, force field parameterisation and energy minimisation. The implementation of a novel programming (COMFORT) and hardware (the BB08) environment into a parallel molecular mechanics (MM) program is presented in Chapter 6. The structure of the sequential version of the MM program is detailed, before discussing the implementation of the parallel version using COMFORT and the BB08.

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Chilingirian, Berj Krikor. "Hashing hardware : identifying hardware during boot-time system verification." Thesis, Massachusetts Institute of Technology, 2017. http://hdl.handle.net/1721.1/112837.

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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 85-90).
Modern systems measure the software loaded at boot-time to ensure the machine starts in a trusted state. Such measurements, however, do not include any information about the underlying hardware of the machine. Recent DRAM-based attacks and the growing complexity of the supply chain attest to the importance of measuring hardware at boot. In this thesis, we propose a technique for designing measurement schemes for hardware components. We then apply this technique to designing and implementing a hardware measurement scheme for DRAM on a real system without hardware modifications. Finally, we evaluate our DRAM hardware measurement scheme and demonstrate that it achieves 89% accuracy in mapping a DRAM measurement to the manufacturing process from which that DRAM was produced.
by Berj Krikor Chilingirian.
M. Eng.

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Hawkins, Stuart Philip. "Video replay in computer animation." Thesis, University of Cambridge, 1990. https://www.repository.cam.ac.uk/handle/1810/250977.

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Ray, Gavin Peter. "Computer network analysis and optimisation." Thesis, University of Plymouth, 1993. http://hdl.handle.net/10026.1/1639.

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This thesis presents a study and analysis of the major influences on network cost and their related performance. New methods have been devised to find solutions to network optimisation problems particular to the AT&T ISTEL networks in Europe and these are presented together with examples of their successful commercial application. Network performance is seen by the user in terms of network availability and traffic delay times. The network performance is influenced by many parameters, the dominating influences typically being the number of users accessing the network, the type of traffic demands they place upon it and the particular network configuration itself. The number of possible network configurations available to a network designer is vast if the full range of currently available equipment is taken into account. The aim of this research has been to assist in the selection of most suitable network designs for optimum performance and cost. This thesis looks at the current differing network technologies, their performance characteristics and the issues pertinent to any network design and optimisation procedures. A distinction is made between the network equipment providing user 'access' and that which constitutes the cross country, or *core\ data transport medium. This partitioning of the problem is exploited with the analysis concentrating on each section separately. The access side of the AT&T ISTEL - UK network is used as a basis for an analysis of the general access network. The aim is to allow network providers to analyse the root cause of excessive delay problems and find where small adjustments to access configurations might lead to real performance improvements from a user point of view. A method is developed to allow statistical estimates of performance and quality of service for typical access network configurations. From this a general method for the optimisation of cost expenditure and performance improvement is proposed. The optimisation of both circuit switched and packet switched computer networks is shown to be difficult and is normally tackled by the use of complex procedures on mainframe computers. The new work carried out in this study takes a fresh look at the basic properties of networks in order to develop a new heuristic method for the design and optimisation of circuit switched core networks on a personal computer platform. A fully functional design system was developed that implements time division multiplexed core network design. The system uses both a new heuristic method for improving the quality of the designs and a new 'speed up' algorithm for reducing times to find feasible routes, thereby dramatically improving overall design times. The completed system has since been used extensively to assist in the design of commercial networks across Europe.

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Schoepke, Olaf S. "Dense instruction set computer architecture." Thesis, University of Bath, 1992. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.332540.

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Lyons, Michael John. "Toward a Hardware Accelerated Future." Thesis, Harvard University, 2014. http://pqdtopen.proquest.com/#viewpdf?dispub=3600206.

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Hardware accelerators provide a rare opportunity to achieve orders-of-magnitude performance and power improvements with customized circuit designs.

Many forms of hardware acceleration exist—attributes and trade-offs of each approach is discussed. Single-algorithm accelerators, which maximize efficiency gains through maximum specialization, are one such approach. By combining many of these into a many-accelerator system, high specialization is possible with fewer specialization limits.

The development of one such single-algorithm hardware accelerator for managing compressed Bloom filters in wireless sensor networks is presented. Results from the development of the accelerator highlight scalability deficiencies in the way accelerators are currently integrated into processors, and that the majority of accelerator area is consumed by generic SRAM memory rather than algorithm-specific logic.

These results motivate development of the accelerator store, a system architecture designed for the needs of many-accelerator systems. In particular, the accelerator store improves inter-accelerator communication and includes support for sharing accelerator SRAM memories. Using a security application as an example, the accelerator store architecture is able to reduce total processor area by 30% with less than 1% performance overhead.

Using the accelerator store as a base, the ShrinkFit framework allows accelerators to grow and shrink, to achieve accelerated performance within small FPGA budgets and efficiently expand for more performance when larger FPGA budgets are available. The ability to resize accelerators is particularly useful for hybrid systems combining GP-CPUs and FPGA resources, in which applications may deploy accelerators to a shared FPGA fabric. ShrinkFit performance overheads for small and large FPGA resources are found to be low using a robotic bee brain workload and FPGA prototype.

Finally, future directions are briefly discussed along with details about the production of the robotic bee helicopter brain prototype.

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Brooks, Piete. "Distribution of functions in computer networks." Thesis, University of Cambridge, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.335601.

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Higgi, A. H. M. "Computer architecture with high performance peripherals." Thesis, Bucks New University, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.373587.

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Anderson, Paul. "Computer architecture for wafer scale integration." Thesis, City University London, 1990. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.333768.

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Coughlin, Michael. "Enabling User Space Secure Hardware." Thesis, University of Colorado at Boulder, 2018. http://pqdtopen.proquest.com/#viewpdf?dispub=10791863.

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User space software allows developers to customize applications beyond the limits of the privileged operating system. In this dissertation, we extend this concept to the hardware in the system, providing applications with the ability to define secure hardware; effectively enabling hardware to be treated as a user space resource. This addresses a significant challenge facing industry today, which has an increasing need for secure hardware. With the ever increasing leaks of private data, increasing use of a variety of computing platforms controlled by third parties, and increasing sophistication of attacks, secure hardware, now more than ever, is needed to provide protections we need. However, the current ecosystem of secure hardware is fractured and limited. Developers are left with few choices of platforms to implement their applications and oftentimes the choices don’t fully meet their needs. Instead of relying on manufacturers to make the correct design decisions and ensuring that these platforms are implemented correctly, we enable applications to define the exact secure hardware that it needs to protect itself and its data.

This vision leverages the emergence of programmable hardware, specifically FPGAs, to serve as the basis of user space secure hardware. The challenges of this, however, are that (i) sharing of FPGA resources among multiple applications is not currently practical, and (ii) the reprogrammability of FPGAs compromises the security properties of secure hardware. We address these challenges by introducing two systems, Cloud RTR and Software Defined Secure Hardware, which individually solve each challenge, and then combine these solutions together to realize the complete vision. Cloud RTR solves the first challenge by leveraging cloud compilation to allow for an FPGA to be shared between applications, making hardware into a user space resource. SDSHW solves the second challenge by introducing a self-provisioning system that allows for an FPGA to provisioned into a secure state, allowing for secure hardware to be run in an FPGA. We then combine these two systems to implement the user space hardware provided by Cloud RTR on the secure platform provided by SDSHW, which provides our vision of user space secure hardware.

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Ibbitson, I. R. "The design and development of a microprocessor based system for computer aided design and computer aided learning." Thesis, University of Sunderland, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.372552.

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Baddam, Karthik. "Hardware level countermeasures against differential power analysis." Thesis, University of Southampton, 2012. https://eprints.soton.ac.uk/300786/.

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Hardware implementations of mathematically secure algorithms unintentionally leak side channel information, that can be used to attack the device. Such attacks, known as side channel attacks, are becoming an increasingly important aspect of designing security systems. In this thesis, power analysis attacks are discussed along with existing countermeasures. In the first part of the thesis, the theory and practice of side-channel attacks is introduced. In particular, it is shown that plain implementations of block ciphers are highly susceptible to power-analysis attacks. Dual rail precharge (DRP) circuits have already been proposed as an effective countermeasure against power analysis attacks. DRP circuits suffer from an implementation problem; balancing the routing capacitance of differential signals. In this thesis we propose a new countermeasure, path switching, to address the routing problem in DRP circuits which has very low overheads compared to existing methods. The proposed countermeasure is tested with simulations and experimentally on an FPGA board. Results from these tests show a minimum of 75 times increase in the power traces required for a first order DPA attack. Some of the existing countermeasures to address the routing problem in DRP circuits do not consider coupling capacitance between differential signals. In this thesis we propose a new method, divided backend duplication that effectively addresses balanced the routing problem of DRP circuits. The proposed countermeasure is tested with simulations and results show a minimum of 300 times increase in the power traces required for a first order DPA attack. Randomisation as a DPA countermeasure is also explored. It is found that randomising the power consumption of the cryptographic device itself has little impact on DPA. Randomising the occurrence of intermediate results, on which DPA relies on, has better effect at mitigating DPA.

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Mitchell, David Anthony Paul. "Fast algorithms and hardware for 3D computer graphics." Thesis, University of Sheffield, 1992. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.299571.

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Roy, Shaunak S. M. Massachusetts Institute of Technology. "Future value chains in the computer hardware industry." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/38568.

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Thesis (S.M.)--Massachusetts Institute of Technology, Engineering Systems Division, Technology and Policy Program; and, (M. Eng. in Logistics)--Massachusetts Institute of Technology, Engineering Systems Division, 2006.
Includes bibliographical references (leaves 96-97).
Companies in the computer hardware industry can benefit by incorporating future business scenarios in their present decision-making processes. Any decision regarding strategic supply chain design is one such area where long-range planning can especially help. This is primarily because investments in new supply chains have a long return period, which also influence the chances of future success of a company. However, developing such long-range views of the whole industry is a challenging task, because of inherent uncertainties of the future and rapid changes in the computer industry itself. This paper takes a step towards achieving this goal by introducing several frameworks for the development of future scenarios and their analysis.
by Shaunak Roy.
M.Eng.in Logistics
S.M.

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Pace-Pequeño, Catherine. "Crafton Hills College computer hardware/software tracking system." CSUSB ScholarWorks, 1998. https://scholarworks.lib.csusb.edu/etd-project/1364.

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Dimitrov, Martin. "Architectural support for improving system hardware/software reliability." Doctoral diss., University of Central Florida, 2010. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4533.

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It is a great challenge to build reliable computer systems with unreliable hardware and buggy software. On one hand, software bugs account for as much as 40% of system failures and incur high cost, an estimate of $59.5B a year, on the US economy. On the other hand, under the current trends of technology scaling, transient faults (also known as soft errors) in the underlying hardware are predicted to grow at least in proportion to the number of devices being integrated, which further exacerbates the problem of system reliability. We propose several methods to improve system reliability both in terms of detecting and correcting soft-errors as well as facilitating software debugging. In our first approach, we detect instruction-level anomalies during program execution. The anomalies can be used to detect and repair soft-errors, or can be reported to the programmer to aid software debugging. In our second approach, we improve anomaly detection for software debugging by detecting different types of anomalies as well as by removing false-positives. While the anomalies reported by our first two methods are helpful in debugging single-threaded programs, they do not address concurrency bugs in multi-threaded programs. In our third approach, we propose a new debugging primitive which exposes the non-deterministic behavior of parallel programs and facilitates the debugging process. Our idea is to generate a time-ordered trace of events such as function calls/returns and memory accesses in different threads. In our experience, exposing the time-ordered event information to the programmer is highly beneficial for reasoning about the root causes of concurrency bugs.
ID: 028916717; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (Ph.D.)--University of Central Florida, 2010.; Includes bibliographical references (p. 110-119).
Ph.D.
Doctorate
School of Electrical Engineering and Computer Science
Engineering and Computer Science

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Jassim, A. R. "Performance modelling of fault tolerant computer networks." Thesis, University of Nottingham, 1985. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.371127.

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Medeiros, J. C. de. "Aspects of an HF interactive computer link." Thesis, University of Kent, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.374421.

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Stephenson, David Ian. "Creatures : a fine grained parallel computer architecture." Thesis, University of York, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.282322.

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Butt, Wajeeh U. N. "Load balancing strategies for distributed computer systems." Thesis, Loughborough University, 1993. https://dspace.lboro.ac.uk/2134/14162.

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The study investigates various load balancing strategies to improve the performance of distributed computer systems. A static task allocation and a number of dynamic load balancing algorithms are proposed, and their performances evaluated through simulations. First, in the case of static load balancing, the precedence constrained scheduling heuristic is defined to effectively allocate the task systems with high communication to computation ratios onto a given set of processors. Second, the dynamic load balancing algorithms are studied using a queueing theoretic model. For each algorithm, a different load index has been used to estimate the host loads. These estimates are utilized in simple task placement heuristics to determine the probabilities for transferring tasks between every two hosts in the system. The probabilities determined in this way are used to perform dynamic load balancing in a distributed computer system. Later, these probabilities are adjusted to include the effects of inter-host communication costs. Finally, network partitioning strategies are proposed to reduce the communication overhead of load balancing algorithms in a large distributed system environment. Several host-grouping strategies are suggested to improve the performance of load balancing algorithms. This is achieved by limiting the exchange of load information messages within smaller groups of hosts while restricting the transfer of tasks to long distance remote hosts which involve high communication costs. Effectiveness of the above-mentioned algorithms is evaluated by simulations. The model developed in this study for such simulations can be used in both static and dynamic load balancing environments.

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Lyons, Michael John. "Toward a Hardware Accelerated Future." Thesis, Harvard University, 2013. http://dissertations.umi.com/gsas.harvard:11152.

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Lüthi, Martin. "Electronic Commerce im IT-Hardware-Markt : ausgeführt anhand zweier Fallbeispiele aus dem Computer-Hardware- und dem Data-Communication-Hardware-Markt /." [S.l.] : [s.n.], 1999. http://www.ub.unibe.ch/content/bibliotheken_sammlungen/sondersammlungen/dissen_bestellformular/index_ger.html.

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Cheng, Chih Kang. "Hardware implementation of the complex Hopfield neural network." CSUSB ScholarWorks, 1995. https://scholarworks.lib.csusb.edu/etd-project/1016.

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Milligan, Graeme Richard. "Reconfigurable hardware for control applications." Thesis, University of Glasgow, 2008. http://theses.gla.ac.uk/456/.

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This portfolio document is intended to present the work carried out in order to meet the requirements of the Engineering Doctorate (EngD) program undertaken at the Institute for System Level Integration (ISLI). This program was undertaken in partnership with the Universities of Glasgow, Edinburgh, Strathclyde and Heriott Watt and was funded by EPSRC and SLI Ltd. The use of control systems is becoming ubiquitous with even the simplest of systems now employing some kind of control logic. For this reason the project investigated the use and development of reconfigurable hardware for control applications. This first involved a detailed analysis of the current state of the art in the reconfigurable field as well as some selected applications where it is thought this technology may be of benefit. The main body of the project was separated into three distinct areas of research and is hence presented as a collection of three technical documents. The first of these areas was the use of reconfigurable hardware for the implementation of Finite State Machines (FSM) with particular reference to reducing the size of the hardware block required to implement these structures. From this a novel implementation method was developed based on the principle of Forward Transition Expressions which are capable of implementing FSMs on a reconfigurable device using run-time reconfiguration. The second area of research was the investigation of the characteristics of reconfigurable devices with a view to estimating the amount of hardware required within a device from high level parameters. The final area of research was the development of a custom reconfigurable device specifically tailored for the implementation of FSM.

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Chau, Man Ping Grace. "Goal-oriented hardware design." Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/45853.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.
Includes bibliographical references (p. 145-146).
This thesis presents Fide, a hardware design system that uses Goal-oriented programming. Goal-oriented programming is a programming framework to specify open-ended decision logic. This approach relies on two fundamental concepts-Goals and Techniques. Goals encode decision points and Techniques are scripts that describe how to satisfy Goals. In Fide, Goals represent the functional requirements (e.g., addition of two 32-bit binary integers) of the target circuit. Techniques represent hardware implementation alternatives that fulfill the functions. Techniques may declare their own subgoals, allowing a hierarchical decomposition of the functions. A Planner selects among Techniques based on the Goals declared to generate an implementation of the target circuit automatically. Users' preferences can be added to generate circuits for different scenarios: for different hardware environments, under different circuit constraints, or different implementation criteria etc. A Beta processor is implemented using Fide. The quality of the implementation is comparable to those optimized manually.
by Man Ping Grace Chau.
S.M.

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Baba, Mohd Dani. "Fault tolerance in distributed real-time computer systems." Thesis, University of Sussex, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.307238.

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A distributed real-time computer system consists of several processing nodes interconnected by communication channels. In a safety critical application, the real-time system should maintain timely and dependable services despite component failures or transient overloads due to changes in application environment. When a component fails or an overload occurs, the hard real-time tasks may miss their timing constraints, and it is desired that the system to degrade in a graceful, predictable manner. The approach adopted to the problem in this thesis is by integrating the resource scheduling with fault tolerance mechanism. This thesis provides a basis for the modelling and design of an adaptive fault tolerant distributed real-time computer system. The main issue is to determine a priori the worst case timing response of the given hard realtime tasks. In this thesis the worst case timing response of the given hard real-time task of the distributed system using the Controller Area Network (CAN) communication protocol is evaluated as to whether they can satisfy their timing deadlines. In a hard real-time system, the task scheduling is the most critical problem since the scheduling strategy ensures that tasks meet their deadlines. In this thesis several fixed priority scheduling schemes are evaluated to select the most efficient scheduler in terms of the bus utilisation and access time. Static scheduling is used as it can be considered to be most appropriate for safety critical applications since the schedulability can easily be verified. Furthermore for a typical industrial application, the hard real-time system has to be adaptable to accommodate changes in the system or application requirements. This .goal of flexibility can be achieved by integrating the static scheduler using an imprecise computation technique with the fault tolerant mechanism which uses active redundant components.

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Ayyad, Abdulkarim Ahmad. "The design of a macro-dataflow computer system." Thesis, University of Brighton, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.335148.

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McCormack, Michelle Mary. "The design and evaluation of computer music interfaces." Thesis, City University London, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.339694.

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Moore, Michael Peter. "The construction and control of an MIMD computer." Thesis, University of Southampton, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.305513.

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Fleming, Robert Renka Robert Joseph. "General purpose programming on modern graphics hardware." [Denton, Tex.] : University of North Texas, 2008. http://digital.library.unt.edu/permalink/meta-dc-6112.

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Busch, Holger. "Hardware design by proven transformations." Thesis, Brunel University, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.293219.

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Li, Juan. "Application-directed DVFS using multiple clock domains on graphics hardware." Worcester, Mass. : Worcester Polytechnic Institute, 2008. http://www.wpi.edu/Pubs/ETD/Available/etd-011409-144732/.

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Thesis (M.S.)--Worcester Polytechnic Institute.
Keywords: Dynamic Voltage and Frequency Scaling(DVFS); Energy; Graphics Process Unit(GPU); Multiple Clock Domain(MCD). Includes bibliographical references (leaves 78-81).

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Fu, Yan Kit. "Some software and hardware implementations of the fast Hartley transform." Thesis, University of British Columbia, 1990. http://hdl.handle.net/2429/29940.

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The fast Hartley transform (FHT) is a new tool for converting data between time and frequency domains. In this thesis, some speed-optimized software implementations of the radix-2 and split-radix FHT algorithms are presented initially, and then applied to the problems of convolution, computation of power spectra, image degradation, and image restoration. Subsequent work involved the development of a new bit-reversal algorithm. This algorithm is fast and efficient, and can be used to increase the throughput of the FHT. Finally, several hardware implementations are presented for the discrete Hartley transform (DHT) and the FHT with architectures using a single butterfly unit, pipelining and superparallelism. The advantages of each implementation are stressed. The data processing rates of these hardware implementations are analyzed.
Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate

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Mash, Peter William Tudor. "Hardware implications for efficient production of computer-generated holograms." Thesis, University of Cambridge, 2007. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.612930.

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Stamoulis, Iakovos. "Computer graphics hardware using ASICs, FPGAs and embedded logic." Thesis, University of Sussex, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.313943.

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The introduction of new technologies such as Field Programmable Gate Arrays (FPGAs) with high gate counts and embedded memory Applications Specific Integrated Circuits (ASICs) gives greater scope to the design of computer graphics hardware. This thesis investigates the features of the current generation of FPGAs and complex programmable logic devices (CPLD) and assesses their suitability as replacements for ASIC technologies, and as prototyping tools for their verification prior to fabrication. The traditional methodologies and techniques used for digital systems are examined for application to FPGA devices and novel design flow and implementation techniques are proposed. The new methodology and design flow uses a contemporary top down approach using hardware description languages and combines the flexibility of those methods with the efficiency of detailed low level design techniques. As an example of this methodology, a set of floating point arithmetic units consisting of a adder/subtraction, multiplication and division were designed using novel alternative algorithms that significantly outperformed algorithms designed with traditional methods in terms of both size and performance.T hese techniquesu sed were used to form a ToolKit that can accelerateth e design of systems that use floating point units for computer graphics systems. This ToolKit, in combination with a precision investigation methods can be used to generate floating point arithmetic units that have the required precision with minimum required hardware resources. Another emerging technology is that of embedded memory. Recent advancements in semiconductor fabrication processes make it feasible to integrate large amounts of DRAM, SRAM and logic on a single silicon die. This thesis will show the changes in the design flow that are require to take advantage of this new technology. A new embedded logic ToolKit was created that facilitates the exploitation of this technology. Finally, as an example to this methodology, a novel processor oriented towards 3D graphics was designedA. n architecturale xploration driven by novel trace-drivenp erformancea nalysism ethods is detailed that was used to model and tune the processor for the execution of global illumination computer graphics algorithms. The adaptation of these algorithms for execution in our processor is demonstrateda nd the performancea dvantagesth at can be extracteda re shown

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Bartzoudis, Nikolaos. "Using embedded hardware monitor cores in critical computer systems." Thesis, Loughborough University, 2006. https://dspace.lboro.ac.uk/2134/33928.

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The integration of FPGA devices in many different architectures and services makes monitoring and real time detection of errors an important concern in FPGA system design. A monitor is a tool, or a set of tools, that facilitate analytic measurements in observing a given system. The goal of these observations is usually the performance analysis and optimisation, or the surveillance of the system. However, System-on-Chip (SoC) based designs leave few points to attach external tools such as logic analysers. Thus, an embedded error detection core that allows observation of critical system nodes (such as processor cores and buses) should enforce the operation of the FPGA-based system, in order to prevent system failures. The core should not interfere with system performance and must ensure timely detection of errors. This thesis is an investigation onto how a robust hardware-monitoring module can be efficiently integrated in a target PCI board (with FPGA-based application processing features) which is part of a critical computing system.

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BRUHNS, THOMAS VICTOR. "HARDWARE AND SOFTWARE FOR A COMPUTER CONTROLLED LIDAR SYSTEM." Diss., The University of Arizona, 1985. http://hdl.handle.net/10150/188042.

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The hardware and software for a computer controlled optical radar, or lidar, system are described. The system builds on a previously installed pulsed ruby backscatter lidar, capable of acquiring data at controlled azimuth and elevation angles through the atmosphere. The described system replaces hardwired logic with computer control. Two coupled computers are used to allow a degree of real time control while data are processed. One of these computers reads and controls mount elevation angle, reads the laser energy monitor, and senses firing of the laser. The other computer serves as a user interface, and receives the lidar return data from a digitizer and memory, and the angle and energy information from the other computer. The second computer also outputs data to a disc drive. The software provided with the system is described, and the feasibility of additional software for both control and data processing is explored. Particular attention is given to data integrity and instrument and computer operation in the presence of the high energy pulses used to drive the laser. A previously described laser energy monitor has been improved to isolate it from laser transients. Mount elevation angles are monitored with an absolute angle readout. As a troubleshooting aid, a simulator with an output that approximates the lidar receiver output was developed. Its output is digitally generated and provides a known repetitive signal. Operating procedures are described for standard data acquisition, and troubleshooting is outlined. The system can be used by a relatively inexperienced operator; English sentences are displayed on the system console CRT terminal to lead the operator through data acquisition once the system hardware is turned on. A brief synopsis of data acquired on the system is given. Those data are used as the basis of other referenced papers. It constitutes soundings for over one hundred days. One high point has been operation of the system in conjunction with a balloon borne atmospheric particulate sampling package. The system has also been used occasionally as the transmitter of a lidar system with physically separated receiver and transmitter.

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Chen, Hao. "Toward hardware-oriented defensive network infrastructure." Thesis, State University of New York at Binghamton, 2015. http://pqdtopen.proquest.com/#viewpdf?dispub=3713553.

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The prosperity of the Internet has made it attractive to hackers and malicious attackers. Distributed attacks, such as: DDoS attacks and Internet worms have become major threats towards the network infrastructure. Collaborating existent single-point-deployed security applications over multi-domains for distributed defense is promising. Taking advantage of the small-world network model, a three-layered network modeling platform was developed for exploring behaviors of collaborative defense under the scope of a complex system. Using this platform, a comparison study between two major collaborative defense schemes was conducted. Their performance and eectiveness against signature-embedded worm attacks were evaluated accordingly.

Given the rapid evolution of attack methods and toolkits, software-based solutions to secure the network infrastructure have become overburdened. The performance gap between the execution speed of security software and the amount of data to be processed is ever widening. A common solution to close this performance gap is through hardware implementation of security functions. After a comprehensive survey on major recongurable hardware-based approaches application on network infrastructure security area, an optimized design of FPGA-based Power Spectral Density (PSD) data converter for online Shrew DDoS attack detection was proposed and prototyped. Combining an innovative component-reusable Auto-Correlation (AC) algorithm and the adapted 2N-point real-valued Discrete Fourier Transform (DFT) algorithm, a maximum reduction of 61.8% processing time from 27471.4 us to 10504.8 us was achieved. These ecient hardware realization enabled the implementation of this design to a Xilinx Virtex2 Pro FGPA.

The scalability issue against continuously expanding signature databases is another major impediment aecting hardware application for network intrusion detection. With the observation that signature patterns are constructed from combinations of a limited number of primary patterns, a two-stage decomposition approach was developed to solve this issue. The evaluation results show that a reduction in size of over 77% can be achieved on top of signature patterns extracted from the Snort rule database after decomposition.

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Massoumi, Mehran Mokhtar 1961. "HARDWARE PROGRAM SIMULATOR: THE INTERACTIVE VERSION." Thesis, The University of Arizona, 1987. http://hdl.handle.net/10150/276502.

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Every effective simulation system should offer enough flexibility to allow thorough examination of the simulation object. HPSIM is a non-interactive function level Hardware Program SIMulator which is used to simulate synchronous clock mode sequential circuits. HPSIM, although a powerful design tool, lacks the flexibility to let the user carry out a "trial and error" simulation or inspect the behavior of the circuit for several inputs without having to prepare separate input files and re-run the entire program for every input. This thesis explores the drawbacks of HPSIM and offers solutions to produce a more effective design tool. The result is the interactive version of HPSIM or HPSIM/I which includes all features of HPSIM plus several added capabilities.

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Othman, A. T. "Performance analysis and control of computer communication network models." Thesis, University of Bradford, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.384333.

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Lei, Li. "Hardware/Software Interface Assurance with Conformance Checking." PDXScholar, 2015. https://pdxscholar.library.pdx.edu/open_access_etds/2323.

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Hardware/Software (HW/SW) interfaces are pervasive in modern computer systems. Most of HW/SW interfaces are implemented by devices and their device drivers. Unfortunately, HW/SW interfaces are unreliable and insecure due to their intrinsic complexity and error-prone nature. Moreover, assuring HW/SW interface reliability and security is challenging. First, at the post-silicon validation stage, HW/SW integration validation is largely an ad-hoc and time-consuming process. Second, at the system deployment stage, transient hardware failures and malicious attacks make HW/SW interfaces vulnerable even after intensive testing and validation. In this dissertation, we present a comprehensive solution for HW/SW interface assurance over the system life cycle. This solution is composited of two major parts. First, our solution provides a systematic HW/SW co-validation framework which validates hardware and software together; Second, based on the co-validation framework, we design two schemes for assuring HW/SW interfaces over the system life cycle: (1) post-silicon HW/SW co-validation at the post-silicon validation stage; (2) HW/SW co-monitoring at the system deployment stage. Our HW/SW co-validation framework employs a key technique, conformance checking which checks the interface conformance between the device and its reference model. Furthermore, property checking is carried out to verify system properties over the interactions between the reference model and the driver. Based on the conformance between the reference model and the device, properties hold on the reference model/driver interface also hold on the device/driver interface. Conformance checking discovers inconsistencies between the device and its reference model thereby validating device interface implementations of both sides. Property checking detects both device and driver violations of HW/SW interface protocols. By detecting device and driver errors, our co-validation approach provides a systematic and ecient way to validate HW/SW interfaces. We developed two software tools which implement the two assurance schemes: DCC (Device Conformance Checker), a co-validation framework for post-silicon HW/SW integration validation; and CoMon (HW/SW Co-monitoring), a runtime verication framework for detecting bugs and malicious attacks across HW/SW interfaces. The two software tools lead to discovery of 42 bugs from four industry hardware devices, the device drivers, and their reference models. The results have demonstrated the signicance of our approach in HW/SW interface assurance of industry applications.

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López-Lagunas, Abelardo. "Hardware support for fine-grain parallel architectures." Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/14970.

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Fong, Anthony Shi Sheung. "A computer architecture with system attributes on individual instruction operands." Thesis, University of Sunderland, 2003. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.270381.

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Stubbfält, Erik. "Hardware Architecture Impact on Manycore Programming Model." Thesis, Uppsala universitet, Institutionen för informationsteknologi, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-441739.

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This work investigates how certain processor architectures can affectthe implementation and performance of a parallel programming model.The Ericsson Many-Core Architecture (EMCA) is compared and contrastedto general-purpose multicore processors, highlighting differencesin their memory systems and processor cores. A proof-of-conceptimplementation of the Concurrency Building Blocks (CBB) programmingmodel is developed for x86-64 using MPI. Benchmark tests showhow CBB on EMCA handles compute-intensive and memory-intensivescenarios, compared to a high-end x86-64 machine running the proofof-concept implementation. EMCA shows its strengths in heavy computationswhile x86-64 performs at its best with high degrees of datareuse. Both systems are able to utilize locality in their memory systemsto achieve great performance benefits.

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Nguyen, Andrew T. "Investigation of hardware transactional memory." Thesis, Massachusetts Institute of Technology, 2015. http://hdl.handle.net/1721.1/100643.

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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 45-47).
Hardware transactional memory is a new method of optimistic concurrency control that can be used to solve the synchronization problem in multicore software. It is a promising solution due to its simple semantics and good performance relative to traditional approaches. Before we can incorporate this nascent technology into high-performing concurrent programs, it is necessary to investigate the physical capacity constraints and performance characteristics of hardware transactions in order to better inform programmers of their abilities and limitations. Our investigation involves the first empirical study of the "capacity envelope" of HTM in Intel's Haswell and IBM's Power8 architectures. We additionally survey how contention parameters, such as transaction size or write ratio, affect HTM performance and we capture these trends in a regression model for predicting the throughput of HTM-enabled concurrent programs. Through our investigation, we aim to provide what we believe is a much needed understanding of the extent to which one can use HTM to replace locks.
by Andrew T. Nguyen.
M. Eng.

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Dissertations / Theses on the topic 'Computer hardware'

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