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1
Tarnoff, David. "Episode 4.03 – Combinational Logic." Digital Commons @ East Tennessee State University, 2020. https://dc.etsu.edu/computer-organization-design-oer/31.
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Individual logic gates are not very practical. Their power comes when you combine them to create combinational logic. This episode takes a look at combinational logic by working through an example in order to generate its truth table.
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Tarnoff, David. "Episode 5.02 – NAND Logic." Digital Commons @ East Tennessee State University, 2020. https://dc.etsu.edu/computer-organization-design-oer/39.
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Tarnoff, David. "Episode 4.01 – Intro to Logic Gates." Digital Commons @ East Tennessee State University, 2020. https://dc.etsu.edu/computer-organization-design-oer/29.
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Logic gates are the fundamental building blocks of digital circuits. In this episode, we take a look at the four most basic gates: AND, OR, exclusive-OR, and the inverter, and show how an XOR gate can be used to compare two digital values. Click here to read the show transcript.
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Giesecke, Normen. "Ternary quantum logic." PDXScholar, 2006. https://pdxscholar.library.pdx.edu/open_access_etds/4092.
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The application of Moore's Law would not be feasible by using the computing systems fabrication principles that are prevalent today. Fundamental changes in the field of computing are needed to keep Moore's Law operational. Different quantum technologies are available to take the advancement of computing into the future. Logic in quantum technology uses gates that are very different from those used in contemporary technology. Limiting itself to reversible operations, this thesis presents different methods to realize these logic gates. Two methods using Generalized Ternary Gates and Muthukrishnan Stroud Gates are presented for synthesis of ternary logic gates. Realizations of well-known quantum gates like the Feynman gate, Toffoli Gate, 2-qudit and 3-qudit SW AP gates are shown. In addition a new gate, the Inverse SW AP gate, is proposed and its realization is also presented.
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Tarnoff, David. "Episode 4.04 – NAND, NOR, and Exclusive-NOR Logic." Digital Commons @ East Tennessee State University, 2020. https://dc.etsu.edu/computer-organization-design-oer/32.
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The simplest combinational logic circuits are made by inverting the output of a fundamental logic gate. Despite this simplicity, these gates are vital. In fact, we can realize any truth table using a circuit made only from AND gates with inverted outputs.
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Wilkinson, Toby. "Enriched coalgebraic modal logic." Thesis, University of Southampton, 2013. https://eprints.soton.ac.uk/354112/.
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We formalise the notion of enriched coalgebraic modal logic, and determine conditions on the category V (over which we enrich), that allow an enriched logical connection to be extended to a framework for enriched coalgebraic modal logic. Our framework uses V-functors L: A → A and T: X → X, where L determines the modalities of the resulting modal logics, and T determines the coalgebras that provide the semantics. We introduce the V-category Mod(A, α) of models for an L-algebra (A, α), and show that the forgetful V-functor from Mod(A, α) to X creates conical colimits. The concepts of bisimulation, simulation, and behavioural metrics (behavioural approximations),are generalised to a notion of behavioural questions that can be asked of pairs of states in a model. These behavioural questions are shown to arise through choosing the category V to be constructed through enrichment over a commutative unital quantale (Q, Ⓧ, I) in the style of Lawvere (1973). Corresponding generalisations of logical equivalence and expressivity are also introduced,and expressivity of an L-algebra (A, α) is shown to have an abstract category theoretic characterisation in terms of the existence of a so-called behavioural skeleton in the category Mod(A, α). In the resulting framework every model carries the means to compare the behaviour of its states, and we argue that this implies a class of systems is not fully defined until it is specified how states are to be compared or related.
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Fidjeland, Andreas Kirkeby. "Custom computer architectures for logic programming." Thesis, Imperial College London, 2007. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.439777.
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Luongo, Kevin. "Nanoparticle-Based Spintronic Computer Logic Switch." FIU Digital Commons, 2019. https://digitalcommons.fiu.edu/etd/3962.
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Spintronics is a rapidly growing research field due to scalability, integrablility within existing VLSI architecture, significantly reduced switching energy and latency while maintaining stable bit orientation (Spin-up, Spin-down). For the first time sub-5nm Spin Transfer Torque –Magnetic Tunneling Junctions (STT-MTJ) were investigated utilizing various Integrated Circuit (IC) fabrication techniques to evaluate novel concepts in logic switches.
Tunneling Magnetoresistance (TMR) was measured in STT-MTJ stacks of Ta/CoFeB/MgO/CoFeB/Ta with differing diameter ferrimagnetic CoFe2O4 nanoparticles (10nm, 4nm and 2nm) embedded in the MgO layer. MR was detected in the 2nm and 4nm particle devices and demonstrated evidence of single electron transport.
Tri-layer STT-MTJ devices were fabricated using a thin film stack of Ta/Ru/Ta/CoFeB(M1)/MgO/CoFeB(M2)/MgO/CoFeB(M3)/Ta. The overall diameter of the stack was reduced to sub-20nm using Focused Ion Beam (FIB) to mill away extra material. The coercivities of the ferrimagnetic CoFeB layers were modified during thin film deposition by altering sputter conditions. Field Applied- Magnetic Force Microscopy (FA-MFM) was used to detect four different magnetic intensities corresponding to three discreet resistances in the singly addressed device, making this architecture a candidate for neuromorphic computational applications.
Lastly a lithographic-less architecture was developed to mass fabricate and electo-mechanically probe multi-layered, single point, sub-5nm particle based STT-MTJ devices using off-the-shelf anodized nanoporous alumina. Once fabricated, the devices were probed to measure their IV characteristics and magnetoresistance (MR). The unprecedented MR changes on the order of 50,000% at room temperature suggest quantum mechanical behavior.
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Nguyen, Loc Bao. "Logic design using programmable logic devices." PDXScholar, 1988. https://pdxscholar.library.pdx.edu/open_access_etds/4103.
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The Programmable Logic Devices, PLO, have caused a major impact in logic design of digital systems in this decade. For instance, a twenty pin PLO device can replace from three hundreds to six hundreds Transistor Transistor Logic gates, which people have designed with since the 60s. Therefore, by using PLD devices, designers can squeeze more features, reduce chip counts, reduce power consumption, and enhance the reliability of the digital systems.
This thesis covers the most important aspects of logic design using PLD devices. They are Logic Minimization and State Assignment. In addition, the thesis also covers a seldomly used but very useful design style, Self-Synchronized Circuits.
The thesis introduces a new method to minimize Two-Level Boolean Functions using Graph Coloring Algorithms and the result is very encouraging. The raw speed of the coloring algorithms is as fast as the Espresso, the industry standard minimizer from Berkeley, and the solution is equally good.
The thesis also introduces a rule-based state assignment method which gives equal or better solutions than STASH (an Intel Automatic CAD tool) by as much as twenty percent.
One of the problems with Self-Synchronized circuits is that it takes many extra components to implement the circuit. The thesis shows how it can be designed using PLD devices and also suggests the idea of a Clock Chip to reduce the chip count to make the design style more attractive.
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Kabiri, Chimeh Mozhgan. "Data structures for SIMD logic simulation." Thesis, University of Glasgow, 2016. http://theses.gla.ac.uk/7521/.
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Due to the growth of design size and complexity, design verification is an important aspect of the Logic Circuit development process. The purpose of verification is to validate that the design meets the system requirements and specification. This is done by either functional or formal verification. The most popular approach to functional verification is the use of simulation based techniques. Using models to replicate the behaviour of an actual system is called simulation. In this thesis, a software/data structure architecture without explicit locks is proposed to accelerate logic gate circuit simulation. We call thus system ZSIM. The ZSIM software architecture simulator targets low cost SIMD multi-core machines. Its performance is evaluated on the Intel Xeon Phi and 2 other machines (Intel Xeon and AMD Opteron). The aim of these experiments is to: • Verify that the data structure used allows SIMD acceleration, particularly on machines with gather instructions ( section 5.3.1). • Verify that, on sufficiently large circuits, substantial gains could be made from multicore parallelism ( section 5.3.2 ). • Show that a simulator using this approach out-performs an existing commercial simulator on a standard workstation ( section 5.3.3 ). • Show that the performance on a cheap Xeon Phi card is competitive with results reported elsewhere on much more expensive super-computers ( section 5.3.5 ). To evaluate the ZSIM, two types of test circuits were used: 1. Circuits from the IWLS benchmark suit [1] which allow direct comparison with other published studies of parallel simulators.2. Circuits generated by a parametrised circuit synthesizer. The synthesizer used an algorithm that has been shown to generate circuits that are statistically representative of real logic circuits. The synthesizer allowed testing of a range of very large circuits, larger than the ones for which it was possible to obtain open source files. The experimental results show that with SIMD acceleration and multicore, ZSIM gained a peak parallelisation factor of 300 on Intel Xeon Phi and 11 on Intel Xeon. With only SIMD enabled, ZSIM achieved a maximum parallelistion gain of 10 on Intel Xeon Phi and 4 on Intel Xeon. Furthermore, it was shown that this software architecture simulator running on a SIMD machine is much faster than, and can handle much bigger circuits than a widely used commercial simulator (Xilinx) running on a workstation. The performance achieved by ZSIM was also compared with similar pre-existing work on logic simulation targeting GPUs and supercomputers. It was shown that ZSIM simulator running on a Xeon Phi machine gives comparable simulation performance to the IBM Blue Gene supercomputer at very much lower cost. The experimental results have shown that the Xeon Phi is competitive with simulation on GPUs and allows the handling of much larger circuits than have been reported for GPU simulation. When targeting Xeon Phi architecture, the automatic cache management of the Xeon Phi, handles and manages the on-chip local store without any explicit mention of the local store being made in the architecture of the simulator itself. However, targeting GPUs, explicit cache management in program increases the complexity of the software architecture. Furthermore, one of the strongest points of the ZSIM simulator is its portability. Note that the same code was tested on both AMD and Xeon Phi machines. The same architecture that efficiently performs on Xeon Phi, was ported into a 64 core NUMA AMD Opteron. To conclude, the two main achievements are restated as following: The primary achievement of this work was proving that the ZSIM architecture was faster than previously published logic simulators on low cost platforms. The secondary achievement was the development of a synthetic testing suite that went beyond the scale range that was previously publicly available, based on prior work that showed the synthesis technique is valid.
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Günzel, Stephan, Michael Liebe, and Dieter Mersch. "Logic and structure of the computer game." Universität Potsdam, 2010. http://opus.kobv.de/ubp/volltexte/2010/4302/.
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This paper comprises four parts. Firstly, an overview of the mathematics of decision logic in relation to games and of the construction of narration and characters is given. This includes specific limits of the use of decision logic pertaining to games in general and to storytelling in particular. Secondly, the rule system as the medial unconsciousness is focused on. Thirdly, remarks are made on the debate between ludology and narratology, which had to fail as it missed the crucial point: the computer game as a medium. Finally, gaming in general, as well as its relationship to chance, coincidence, emergence, and event is discussed.
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Strikic, Ana. "Linear Algebra in Computer Graphics." Thesis, Linnéuniversitetet, Institutionen för matematik (MA), 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:lnu:diva-89168.
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In this thesis, we will investigate the rapidly developing eld of computergraphics by giving an insight into the calculations behind the most im-portant topics in perspectives, shading and distance. We will delve intofrequently used shading algorithms and perspective transforms in areas ofcomputer science, architecture and photography, such as pseudo sh-eyelenses and wide-angle lenses.
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Xu, Leeka. "Synthesis and optimisation of combinational logic using universal logic module networks." Thesis, Edinburgh Napier University, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.295379.
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Ramakrishnan, Lakshmi Narasimhan. "SDMLp - Secure Differential Multiplexer Logic : Logic Design for DPA-Resistant Cryptographic Circuits." University of Cincinnati / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1311691925.
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Coughlin, Devin. "Type-Intertwined Separation Logic." Thesis, University of Colorado at Boulder, 2015. http://pqdtopen.proquest.com/#viewpdf?dispub=3704668.
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Static program analysis can improve programmer productivity and software reliability by definitively ruling out entire classes of programmer mistakes. For mainstream imperative languages such as C, C++, and Java, static analysis about the heap---memory that is dynamically allocated at run time---is particularly challenging because heap memory acts as global, mutable state. This dissertation describes how to soundly combine two static analyses that each take vastly different approaches to reasoning about the heap: type systems and separation logic. Traditional type systems take an alias-agnostic, global view of the heap that affords both fast verification and light-weight annotation of invariants holding over the entire program. Separation logic, in contrast, provides an alias-aware, local view of the heap in which invariants can vary at each program point. In this work, I show how type systems and separation logic can be safely and efficiently combined. The result is type-intertwined separation logic, an analysis that applies traditional type-based reasoning to some regions of the program and separation logic to others---converting between analysis representations at region boundaries---and summarizes some portions of the heap with coarse type invariants and others with precise separation logic invariants. The key challenge that this dissertation addresses is the communication and preservation of heap invariants between analyses. I tackle this challenge with two core contributions. The first is type-consistent summarization and materialization, which enables type-intertwined separation logic to both leverage and selectively violate the global type invariant. This mechanism allows the analysis to efficiently and precisely verify invariants that hold almost everywhere. Second, I describe gated separating conjunction, a non-commutative strengthening of standard separating conjunction that expresses local dis-pointing relationships between sub-heaps. Gated separation enables local heap reasoning by permitting the separation logic to frame out portions of memory and prevent the type system from interfering with its contents---an operation that would be unsound in type-intertwined analysis with only standard separating conjunction. With these two contributions, type-intertwined separation logic combines the benefits of both type-like global reasoning and separation-logic-style local reasoning in a single analysis.
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Quigley, Claire Louise. "A programming logic for Java bytecode programs." Thesis, University of Glasgow, 2004. http://theses.gla.ac.uk/3030/.
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One significant disadvantage of interpreted bytecode languages, such as Java, is their low execution speed in comparison to compiled languages like C. The mobile nature of bytecode adds to the problem, as many checks are necessary to ensure that downloaded code from untrusted sources is rendered as safe as possible. But there do exist ways of speeding up such systems. One approach is to carry out static type checking at load time, as in the case of the Java Bytecode Verifier. This reduces the number of runtime checks that must be done and also allows certain instructions to be replaced by faster versions. Another approach is the use of a Just In Time (JIT) Compiler, which takes the bytecode and produces corresponding native code at runtime. Some JIT compilers also carry out some code optimization. There are, however, limits to the amount of optimization that can safely be done by the Verifier and JITs; some operations simply cannot be carried out safely without a certain amount of runtime checking. But what if it were possible to prove that the conditions the runtime checks guard against would never arise in a particular piece of code? In this case it might well be possible to dispense with these checks altogether, allowing optimizations not feasible at present. In addition to this, because of time constraints, current JIT compilers tend to produce acceptable code as quickly as possible, rather than producing the best code possible. By removing the burden of analysis from them it may be possible to change this. We demonstrate that it is possible to define a programming logic for bytecode programs that allows the proof of bytecode programs containing loops. The instructions available to use in the programs are currently limited, but the basis is in place to extend these. The development of this logic is non-trivial and addresses several difficult problems engendered by the unstructured nature of bytecode programs.
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Kusalik, Anthony Joseph. "Logic programming as a formalism for specification and implementation of computer systems." Thesis, University of British Columbia, 1988. http://hdl.handle.net/2429/28848.
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The expressive power of logic-programming languages allows utilization of conventional constructs
in development of computer systems based on logic programming. However, logic-programming languages have many novel features and capabilities. This thesis investigates how advantage can be taken of these features in the development of a logic-based computer system. It demonstrates that innovative
approaches to software, hardware, and computer system design and implementation are feasible in a logic-programming context and often preferable to adaptation of conventional ones. The investigation
centers on three main ideas: executable specification, declarative I/O, and implementation through transformation and meta-interpretation. A particular class of languages supporting parallel computation, committed-choice logic-programming languages, are emphasized. One member of this class, Concurrent
Prolog, serves as the machine, specification, and implementation language.
The investigation has several facets. Hardware, software, and overall system models for a logic-based computer are determined and examined. The models are described by logic programs. The computer
system is represented as a goal for resolution. The clauses involved in the subsequent reduction steps constitute its specification. The same clauses also describe the manner in which the computer system
is initiated. Frameworks are given for developing models of peripheral devices whose actions and interactions can be declaratively expressed. Interactions do not rely on side-effects or destructive assignment, and are term-based. A methodology is presented for realizing (prototypic) implementations from device specifications. The methodology is based on source-to-source transformation and meta-interpretation. A magnetic disk memory is used as a representative example, resulting in an innovative approach to secondary storage in a logic-programming environment. Building on these accomplishments,
a file system for a logic-based computer system is developed. The file system follows a simple model and supports term-based, declarative I/O. Throughout the thesis, features of the logic-programming paradigm are demonstrated and exploited. Interesting and innovative concepts established include: device processes and device processors; restartable and perpetual devices and systems; peripheral
devices modelled as function computations or independent logical (inference) systems; unique, compact representations of terms; lazy term expansion; files systems as perpetual processes maintaining local states; and term- and unification-based file abstractions. Logic programs are the sole formalism for specifications and implementations.Science, Faculty of
Computer Science, Department of
Graduate
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Lapointe, Stéphane. "Induction of recursive logic programs." Thesis, University of Ottawa (Canada), 1992. http://hdl.handle.net/10393/7467.
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Botha, Leonard. "DevelopinThe Bayesian Description Logic BALC." Master's thesis, University of Cape Town, 2018. http://hdl.handle.net/11427/29350.
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Description Logics (DLs) that support uncertainty are not as well studied as their crisp alternatives. This limits their application in many real world domains, which often require reasoning about uncertain or contradictory information. In this thesis we present the Bayesian Description Logic BALC, which takes existing work on Bayesian Description Logics and applies it to the classical Description Logic ALC. We define five reasoning problems for BALC; two versions of concept satisfiability (called total and partial respectively), knowledge base consistency, three subsumption problems (positive subsumption, p-subsumption, exact subsumption), instance checking, and the most likely context problem. Consistency, satisfiability, and instance checking have not previously been studied in the context of contextual Bayesian DLs and as such this is new work. We then go on to provide algorithms that solve all of these reasoning problems, with the exception of the most likely context problem. We found that all reasoning problems in BALC are in the same complexity class as their classical variants, provided that the size of the Bayesian Network is included in the size of the knowledge base. That is, all reasoning problems mentioned above (excluding most likely context) are exponential in the size of the knowledge base and the size of the Bayesian Network.
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Ho, Phuong Minh. "Parallel architectures for solving combinatorial problems of logic design." PDXScholar, 1989. https://pdxscholar.library.pdx.edu/open_access_etds/3872.
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This thesis presents a new, practical approach to solve various NP-hard combinatorial problems of logic synthesis, logic programming, graph theory and related areas. A problem to be solved is polynomially time reduced to one of several generic combinatorial problems which can be expressed in the form of the Generalized Propositional Formula (GPF) : a Boolean product of clauses, where each clause is a sum of products of negated or non-negated literals.
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Tibbits, Skylar J. E. "Logic matter : digital logic as heuristics for physical self-guided-assembly." Thesis, Massachusetts Institute of Technology, 2010. http://hdl.handle.net/1721.1/64566.
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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Architecture; and, (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 123-124).
Given the increasing complexity of the physical structures surrounding our everyday environment -- buildings, machines, computers and almost every other physical object that humans interact with -- the processes of assembling these complex structures are inevitably caught in a battle of time, complexity and human/machine processing power. If we are to keep up with this exponential growth in construction complexity we need to develop automated assembly logic embedded within our material parts to aid in construction. In this thesis I introduce Logic Matter as a system of passive mechanical digital logic modules for self-guided-assembly of large-scale structures. As opposed to current systems in self-reconfigurable robotics, Logic Matter introduces scalability, robustness, redundancy and local heuristics to achieve passive assembly. I propose a mechanical module that implements digital NAND logic as an effective tool for encoding local and global assembly sequences. I then show a physical prototype that successfully demonstrates the described mechanics, encoded information and passive self-guided-assembly. Finally, I show exciting potentials of Logic Matter as a new system of computing with applications in space/volume filling, surface construction, and 3D circuit assembly.
by Skylar J.E. Tibbits.
S.M.
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McKenzie, Lynn Mhairi. "Logic synthesis and optimisation using Reed-Muller expansions." Thesis, Edinburgh Napier University, 1995. http://researchrepository.napier.ac.uk/Output/4276.
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This thesis presents techniques and algorithms which may be employed to represent, generate and optimise particular categories of Exclusive-OR Sum- Of-Products (ESOP) forms. The work documented herein concentrates on two types of Reed-Muller (RM) expressions, namely, Fixed Polarity Reed-Muller (FPRM) expansions and KROnecker (KRO) expansions (a category of mixed polarity RM expansions). Initially, the theory of switching functions is comprehensively reviewed. This includes descriptions of various types of RM expansion and ESOP forms. The structure of Binary Decision Diagrams (BDDs) and Reed-Muller Universal Logic Module (RM-ULM) networks are also examined. Heuristic algorithms for deriving optimal (sub-optimal) FPRM expansions of Boolean functions are described. These algorithms are improved forms of an existing tabular technique [1]. Results are presented which illustrate the performance of these new minimisation methods when evaluated against selected existing techniques. An algorithm which may be employed to generate FPRM expansions from incompletely specified Boolean functions is also described. This technique introduces a means of determining the optimum allocation of the Boolean 'don't care' terms so as to derive equivalent minimal FPRM expansions. The tabular technique [1] is extended to allow the representation of KRO expansions. This new method may be employed to generate KRO expansions from either an initial incompletely specified Boolean function or a KRO expansion of different polarity. Additionally, it may be necessary to derive KRO expressions from Boolean Sum-Of-Products (SOP) forms where the product terms are not minterms. A technique is described which forms KRO expansions from disjoint SOP forms without first expanding the SOP expressions to minterm forms. Reed-Muller Binary Decision Diagrams (RMBDDs) are introduced as a graphical means of representing FPRM expansions. RMBDDs are analogous to the BDDs used to represent Boolean functions. Rules are detailed which allow the efficient representation of the initial FPRM expansions and an algorithm is presented which may be employed to determine an optimum (sub-optimum) variable ordering for the RMBDDs. The implementation of RMBDDs as RM-ULM networks is also examined. This thesis is concluded with a review of the algorithms and techniques developed during this research project. The value of these methods are discussed and suggestions are made as to how improved results could have been obtained. Additionally, areas for future work are proposed.
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Alqahtani, Saeed Masaud H. "Cloud intrusion detection systems : fuzzy logic and classifications." Thesis, University of Nottingham, 2017. http://eprints.nottingham.ac.uk/45430/.
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Cloud Computing (CC), as defned by national Institute of Standards and Technology (NIST), is a new technology model for enabling convenient, on-demand network access to a shared pool of configurable computing resources such as networks, servers, storage, applications, and services that can be rapidly provisioned and released with minimal management effort or service-provider interaction. CC is a fast growing field; yet, there are major concerns regarding the detection of security threats, which in turn have urged experts to explore solutions to improve its security performance through conventional approaches, such as, Intrusion Detection System (IDS). In the literature, there are two most successful current IDS tools that are used worldwide: Snort and Suricata; however, these tools are not flexible to the uncertainty of intrusions. The aim of this study is to explore novel approaches to uplift the CC security performance using Type-1 fuzzy logic (T1FL) technique with IDS when compared to IDS alone. All experiments in this thesis were performed within a virtual cloud that was built within an experimental environment. By combining fuzzy logic technique (FL System) with IDSs, namely SnortIDS and SuricataIDS, SnortIDS and SuricataIDS for detection systems were used twice (with and without FL) to create four detection systems (FL-SnortIDS, FL-SuricataIDS, SnortIDS, and SuricataIDS) using Intrusion Detection Evaluation Dataset (namely ISCX). ISCX comprised two types of traffic (normal and threats); the latter was classified into four classes including Denial of Service, User-to-Root, Root-to-Local, and Probing. Sensitivity, specificity, accuracy, false alarms and detection rate were compared among the four detection systems. Then, Fuzzy Intrusion Detection System model was designed (namely FIDSCC) in CC based on the results of the aforementioned four detection systems. The FIDSCC model comprised of two individual systems pre-and-post threat detecting systems (pre-TDS and post-TDS). The pre-TDS was designed based on the number of threats in the aforementioned classes to assess the detection rate (DR). Based on the output of this DR and false positives of the four detection systems, the post-TDS was designed in order to assess CC security performance. To assure the validity of the results, classifier algorithms (CAs) were introduced to each of the four detection systems and four threat classes for further comparison. The classifier algorithms were OneR, Naive Bayes, Decision Tree (DT), and K-nearest neighbour. The comparison was made based on specific measures including accuracy, incorrect classified instances, mean absolute error, false positive rate, precision, recall, and ROC area. The empirical results showed that FL-SnortIDS was superior to FL-SuricataIDS, SnortIDS, and SuricataIDS in terms of sensitivity. However, insignificant difference was found in specificity, false alarms and accuracy among the four detection systems. Furthermore, among the four CAs, the combination of FL-SnortIDS and DT was shown to be the best detection method. The results of these studies showed that FIDSCC model can provide a better alternative to detecting threats and reducing the false positive rates more than the other conventional approaches.
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Melnikoff, Stephen Jonathan. "Speech recognition in programmable logic." Thesis, University of Birmingham, 2003. http://etheses.bham.ac.uk//id/eprint/16/.
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Speech recognition is a computationally demanding task, especially the decoding part, which converts pre-processed speech data into words or sub-word units, and which incorporates Viterbi decoding and Gaussian distribution calculations. In this thesis, this part of the recognition process is implemented in programmable logic, specifically, on a field-programmable gate array (FPGA). Relevant background material about speech recognition is presented, along with a critical review of previous hardware implementations. Designs for a decoder suitable for implementation in hardware are then described. These include details of how multiple speech files can be processed in parallel, and an original implementation of an algorithm for summing Gaussian mixture components in the log domain. These designs are then implemented on an FPGA. An assessment is made as to how appropriate it is to use hardware for speech recognition. It is concluded that while certain parts of the recognition algorithm are not well suited to this medium, much of it is, and so an efficient implementation is possible. Also presented is an original analysis of the requirements of speech recognition for hardware and software, which relates the parameters that dictate the complexity of the system to processing speed and bandwidth. The FPGA implementations are compared to equivalent software, written for that purpose. For a contemporary FPGA and processor, the FPGA outperforms the software by an order of magnitude.
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Hale, Roger William Stephen. "Programming in temporal logic." Thesis, University of Cambridge, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.305467.
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Quintero, Jacinto Alfonso Davila. "Agents in logic programming." Thesis, Imperial College London, 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.263219.
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Carvalho, A. M. B. R. "Logic grammars and pronominal anaphora." Thesis, University of Reading, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.234787.
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Farrow, P. F. "Logic, dependencies, and specification engineering." Thesis, University of Southampton, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.328298.
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Duan, Zhenhua. "An extended interval temporal logic and a framing technique for temporal logic programming." Thesis, University of Newcastle Upon Tyne, 1996. http://hdl.handle.net/10443/2075.
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Temporal logic programming is a paradigm for specification and verification of concurrent programs in which a program can be written, and the properties of the program can be described and verified in a same notation. However, there are many aspects of programming in temporal logics that are not well-understood. One such an aspect is concurrent programming, another is framing and the third is synchronous communication for parallel processes. This thesis extends the original Interval Temporal Logic (ITL) to include infinite models, past operators, and a new projection operator for dealing with concurrent computation, synchronous communication, and framing in the context of temporal logic programming. The thesis generalizes the original ITL to include past operators such as previous and past chop, and extends the model to include infinite intervals. A considerable collection of logic laws regarding both propositional and first order logics is formalized and proved within model theory. After that, a subset of the extended ITL is formalized as a programming language, called extended Tempura. These extensions, as in their logic basis, include infinite models, the previous operator, projection and framing constructs. A normal form for programs within the extended Tempura is demonstrated. Next, a new projection operator is introduced. In the new construct, the sub-processes are autonomous; each process has the right to specify its own interval over which it is executed. The thesis presents a framing technique for temporal logic programming, which includes the definitions of new assignments, the assignment flag and the framing operator, the formalization of algebraic properties of the framing operator, the minimal model semantics of framed programs, as well as an executable framed interpreter. The synchronous communication operator await is based directly on the proposed framing technique. It enables us to deal with concurrent computation. Based on EITL and await operator, a framed concurrent temporal logic programming language, FTLL, is formally defined within EITL. Finally, the thesis describes a framed interpreter for the extended Tempura which has been developed in SICSTUS prolog. In the new interpreter, the implementation of new assignments, the frame operator, the await operator, and the new projection operator are all included.
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Hinman, Roderick Thornton. "Recovered energy logic--a logic family and power supply featuring very high efficiency." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/12015.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.Includes bibliographical references (p. 215-220).
by Roderick Thornton Hinman.
Ph.D.
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Cermak-Sassenrath, Daniel. "The logic of play in everyday human-computer interaction." Universität Potsdam, 2010. http://opus.kobv.de/ubp/volltexte/2010/4272/.
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Communication, simulation, interactive narrative and ubiquitous computing are widely accepted as perspectives in humancomputer interaction. This paper proposes play as another possible perspective. Everyday uses of the computer increasingly show signs of similarity to play. This is not discussed with regard to the so-called media society, the playful society, the growing cultural acceptance of the computer, the spread of computer games or a new version of Windows, but in view of the playful character of interaction with the computer that has always been part of it. The exploratory learning process involved with new software and the creative tasks that are often undertaken when using the computer may support this argument. Together with its high level of interactivity, these observations point to a sense of security, autonomy and freedom of the user that produce play and are, in turn, produced by play. This notion of play refers not to the playing of computer games, but to an implicit, abstract (or symbolic) process based on a certain attitude, the play spirit. This attitude is discussed regarding everyday computer use and related to the other mentioned perspectives.
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Polak, Mark John. "Adaptive logic networks in a brain-computer interface system." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape3/PQDD_0012/NQ59652.pdf.
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Hardy, Martin Charles. "Control logic evaluation of bespoke computer controlled machine tools." Thesis, University of Huddersfield, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.359143.
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Stamoulis, Iakovos. "Computer graphics hardware using ASICs, FPGAs and embedded logic." Thesis, University of Sussex, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.313943.
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The introduction of new technologies such as Field Programmable Gate Arrays (FPGAs) with high gate counts and embedded memory Applications Specific Integrated Circuits (ASICs) gives greater scope to the design of computer graphics hardware. This thesis investigates the features of the current generation of FPGAs and complex programmable logic devices (CPLD) and assesses their suitability as replacements for ASIC technologies, and as prototyping tools for their verification prior to fabrication. The traditional methodologies and techniques used for digital systems are examined for application to FPGA devices and novel design flow and implementation techniques are proposed. The new methodology and design flow uses a contemporary top down approach using hardware description languages and combines the flexibility of those methods with the efficiency of detailed low level design techniques. As an example of this methodology, a set of floating point arithmetic units consisting of a adder/subtraction, multiplication and division were designed using novel alternative algorithms that significantly outperformed algorithms designed with traditional methods in terms of both size and performance.T hese techniquesu sed were used to form a ToolKit that can accelerateth e design of systems that use floating point units for computer graphics systems. This ToolKit, in combination with a precision investigation methods can be used to generate floating point arithmetic units that have the required precision with minimum required hardware resources. Another emerging technology is that of embedded memory. Recent advancements in semiconductor fabrication processes make it feasible to integrate large amounts of DRAM, SRAM and logic on a single silicon die. This thesis will show the changes in the design flow that are require to take advantage of this new technology. A new embedded logic ToolKit was created that facilitates the exploitation of this technology. Finally, as an example to this methodology, a novel processor oriented towards 3D graphics was designedA. n architecturale xploration driven by novel trace-drivenp erformancea nalysism ethods is detailed that was used to model and tune the processor for the execution of global illumination computer graphics algorithms. The adaptation of these algorithms for execution in our processor is demonstrateda nd the performancea dvantagesth at can be extracteda re shown
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Al-Jassani, ban Adil. "Computer aided synthesis and optimisation of electronic logic circuits." Thesis, Edinburgh Napier University, 2011. http://researchrepository.napier.ac.uk/Output/6658.
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In this thesis, a variety of algorithms for synthesis and optimisation of combinational and sequential logic circuits are developed. These algorithms could be part of new commercial EGAD package for future VLSI digital designs. The results show that considerable saving in components can be achieved resulting in simpler designs that are smaller, cheaper, consume less power and easier to test. The purpose of generating different sets of coefficients related to Reed Muller (RM) is that they contain different number of terms; therefore the minimum one can be selected to design the circuits with reduced gate count. To widen the search space and achieve better synthesis tools, representations of Mixed Polarity Reed Muller (MPRM), Mixed Polarity Dual Reed Muller (MPDRM), and Pseduo Kronecker Reed Muller (PKRO RM) expansions are investigated. Efficient and fast combinatorial techniques and algorithms are developed for the following: â Bidirectional conversion between MPRM/ MPDRM form and Fixed Polarity Reed Muller forms (FPRM)/Fixed Polarity Dual Reed Muller forms (FPDRM) form respectively. The main advantages for these techniques are their simplicity and suitability for single and multi output Boolean functions. â Computing the coefficients of any polarity related to PKRO_RM class starting from FPRM coefficients or Canonical Sum of Products (CSOP). â Computing the coefficients of any polarity related to MPRM/or MPDRM directly from standard form of CSOP/Canonical Product of sums (CPOS) Boolean functions, respectively. The proposed algorithms are efficient in terms of CPU time and can be used for large functions. For optimisation of combinational circuits, new techniques and algorithms based on algebraic techniques are developed which can be used to generate reduced RM expressions to design circuits in RM/DRM domain starting from FPRM/FPDRM, respectively. The outcome for these techniques is expansion in Reed Muller domain with minimal terms. The search space is 3`" Exclusive OR Sum of Product (ESOP)/or Exclusive NOR Product of Sums (ENPOS) expansions. Genetic Algorithms (GAs) are also developed to optimise combinational circuits to find optimal MPRM/MPDRM among 3° different polarities without the need to do exhaustive search. These algorithms are developed for completely and incompletely specified Boolean functions. The experimental results show that GA can find optimum solutions in a short time compared with long time required running exhaustive search in all the benchmarks tested. Multi Objective Genetic Algorithm (MOGA) is developed and implemented to determine the optimal state assignment which results in less area and power dissipation for completely and incompletely specified sequential circuits. The goal is to find the best assignments which reduce the component count and switching activity simultaneously. The experimental results show that saving in components and switching activity are achieved in most of the benchmarks tested compared with recently published research. All algorithms are implemented in C++.
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Lambiri, Cristian. "Temporal logic models for distributed systems." Thesis, University of Ottawa (Canada), 1995. http://hdl.handle.net/10393/10056.
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Since the beginning of the 1980's, the way the computer systems are conceived has changed dramatically. This is a direct result of the appearance, on a large scale, of personal computers and engineering workstations. As a result, networks of independent systems have appeared. This thesis presents a formal specification framework that can be used in the design of distributed systems. The abstract models that are presented are based on a systemic view of distributed systems and discrete event systems. Two base abstract models called deterministic discrete event systems (DDES) and discrete event automaton (DEA) are presented. For the DEA the series and parallel compositions as well as feedback connection are defined. Universal algebra is employed to study the parallel composition of DEAs. From the DDES/DEA an abstract model for distributed systems is obtained. Subsequently, linear time temporal logic is modified for use with the abstract chosen model of distributed systems. The logic is described in three aspects: syntax, semantics and axiomatics. The syntax is modified by the addition of two operators. The semantics of the logic is given over the abstract models. Five axioms are added to the axiomatic system for the two new operators. A programming language called TLL, based on the theoretical framework, links the theory with practice. The syntax and semantics of the programming language are presented. Finally an example of modeling in the framework is given.
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Ngom, Alioune. "Set logic foundation of carrier computing." Thesis, University of Ottawa (Canada), 1995. http://hdl.handle.net/10393/10321.
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Set logic algebra (SLA) is a special case of multiple-valued logic algebra. As an ultra higher-valued logic system, a set-valued logic (SVL) system offers a potential and an essential solution to the interconnection problems that occur in highly parallel VLSI systems. The fundamental concept inherent to a SVL system is multiplex computing or logic values multiplexing: which means the simultaneous transmission of logic values. This basic concept enables the realization of superchips free from interconnection problems. Parallel processing with multiplexable information carriers makes possible to construct large-scale highly parallel system with reduced interconnections. Since the multiplexing of logic values increases the information density, several binary functions can be executed in parallel in a single module. Therefore a great reduction of interconnections can be achieved using optimal multiplexing scheme. Possible approaches to the implementation of the SVL system are based on frequencies multiplexing, waves multiplexing and molecules multiplexing, and are called carrier computing systems. Our research focuses on the study of completeness properties in SLA under compositions with union ($\bigcup$), intersection ($\bigcap$) and complement ($\sp-$) functions. More precisely, the question is what kind of set logic functions can be constructed from given set of functions which includes $\bigcup,$ $\bigcap,$ and $\sp-,$ i.e. whether any set logic function can be constructed from such set. We classify the set logic functions according to their ability to participate in a base (complete irredundant sets of functions) and describe all bases once the classification is done. We develop also some algorithms (programs) for classification and enumeration of functions and bases, which are very useful for a general completeness analysis.
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Chen, Liang-Ting. "On a purely categorical framework for coalgebraic modal logic." Thesis, University of Birmingham, 2014. http://etheses.bham.ac.uk//id/eprint/4882/.
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A category CoLog of distributive laws is introduced to unify different approaches to modal logic for coalgebras, based merely on the presence of a contravariant functor P that maps a state space to its collection of predicates. We show that categorical constructions, including colimits, limits, and compositions of distributive laws as a tensor product, in CoLog generalise and extend existing constructions given for Set coalgebraic logics and that the framework does not depend on any particular propositional logic or state space. In the case that P establishes a dual adjunction with its dual functor S, we show that a canonically defined coalgebraic logic exists for any type of coalgebras. We further restrict our discussion to finitary algebraic logics and study equational coalgebraic logics. Objects of predicate liftings are used to characterise equational coalgebraic logics. The expressiveness problem is studied via the mate correspondence, which gives an isomorphism between CoLog and the comma category from the pre-composition to the post-composition with S. Then, the modularity of the expressiveness is studied in the comma category via the notion of factorisation system.
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Monroe, W. John. "Computer construction of (4,4,v)-threshold schemes from Steiner Quadruple Systems /." Online version of thesis, 1989. http://hdl.handle.net/1850/10582.
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Zhao, Guoxing. "A complete reified temporal logic and its applications." Thesis, University of Greenwich, 2008. http://gala.gre.ac.uk/8200/.
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Temporal representation and reasoning plays a fundamental and increasingly important role in some areas of Computer Science and Artificial Intelligence. A natural approach to represent and reason about time-dependent knowledge is to associate them with instantaneous time points and/or durative time intervals. In particular, there are various ways to use logic formalisms for temporal knowledge representation and reasoning. Based on the chosen logic frameworks, temporal theories can be classified into modal logic approaches (including prepositional modal logic approaches and hybrid logic approaches) and predicate logic approaches (including temporal argument methods and temporal reification methods). Generally speaking, the predicate logic approaches are more expressive than the modal logic approaches and among predicate logic approaches, temporal reification methods are even more expressive for representing and reasoning about general temporal knowledge. However, the current reified temporal logics are so complicate that each of them either do not have a clear definition of its syntax and semantics or do not have a sound and complete axiomatization. In this thesis, a new complete reified temporal logic (CRTL) is introduced which has a clear syntax, semantics, and a complete axiomatic system by inheriting from the initial first order language. This is the main improvement made to the reification approaches for temporal representation and reasoning. It is a true reified logic since some meta-predicates are formally defined that allow one to predicate and quantify over prepositional terms, and therefore provides the expressive power to represent and reason about both temporal and non-temporal relationships between prepositional terms. For a special case, the temporal model of the simplified CRTL system (SCRTL) is defined as scenarios and graphically represented in terms of a directed, partially weighted or attributed, simple graph. Therefore, the problem of matching temporal scenarios is transformed into conventional graph matching. For the scenario graph matching problem, the traditional eigen-decomposition graph matching algorithm and the symmetric polynomial transform graph matching algorithm are critically examined and improved as two new algorithms named meta-basis graph matching algorithm and sort based graph matching algorithm respectively, where the meta-basis graph matching algorithm works better for 0-1 matrices while the sort based graph matching algorithm is more suitable for continuous real matrices. Another important contribution is the node similarity graph matching framework proposed in this thesis, based on which the node similarity graph matching algorithms can be defined, analyzed and extended uniformly. We prove that that all these node similarity graph matching algorithms fail to work for matching circles.
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Wetsel, Gerhard. "Abductive and constraint logic programming." Thesis, Imperial College London, 1997. http://hdl.handle.net/10044/1/7212.
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Ormerod, T. C. "Cognitive processes in logic programming." Thesis, University of Sunderland, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.382171.
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Martin, Jonathan Charles. "Judgement day : terminating logic programs." Thesis, University of Southampton, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.326732.
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Chen, Kailiang. "Circuit design for logic automata." Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/52781.
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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (p. 143-148).
The Logic Automata model is a universal distributed computing structure which pushes parallelism to the bit-level extreme. This new model drastically differs from conventional computer architectures in that it exposes, rather than hides, the physics underlying the computation by accommodating data processing and storage in a local and distributed manner. Based on Logic Automata, highly scalable computing structures for digital and analog processing have been developed; and they are verified at the transistor level in this thesis. The Asynchronous Logic Automata (ALA) model is derived by adding the temporal locality, i.e., the asynchrony in data exchanges, in addition to the spacial locality of the Logic Automata model. As a demonstration of this incrementally extensible, clockless structure, we designed an ALA cell library in 90 nm CMOS technology and established a "pick-and-place" design flow for fast ALA circuit layout. The work flow gracefully aligns the description of computer programs and circuit realizations, providing a simpler and more scalable solution for Application Specific Integrated Circuit (ASIC) designs, which are currently limited by global constraints such as the clock and long interconnects. The potential of the ALA circuit design flow is tested with example applications for mathematical operations. The same Logic Automata model can also be augmented by relaxing the digital states into analog ones for interesting analog computations. The Analog Logic Automata (AnLA) model is a merge of the Analog Logic principle and the Logic Automata architecture, in which efficient processing is embedded onto a scalable construction.
(cont.) In order to study the unique property of this mixed-signal computing structure, we designed and fabricated an AnLA test chip in AMI 0.5[mu]m CMOS technology. Chip tests of an AnLA Noise-Locked Loop (NLL) circuit as well as application tests of AnLA image processing and Error-Correcting Code (ECC) decoding, show large potential of the AnLA structure.
by Kailiang Chen.
S.M.
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Patino, Alberto. "Reversible Logic Synthesis Using a Non-blocking Order Search." PDXScholar, 2010. https://pdxscholar.library.pdx.edu/open_access_etds/162.
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Reversible logic is an emerging area of research. With the rapid growth of markets such as mobile computing, power dissipation has become an increasing concern for designers (temperature range limitations, generating smaller transistors) as well as customers (battery life, overheating). The main benefit of utilizing reversible logic is that there exists, theoretically, zero power dissipation. The synthesis of circuits is an important part of any design cycle. The circuit used to realize any specification must meet detailed requirements for both layout and manufacturing. Quantum cost is the main metric used in reversible logic. Many algorithms have been proposed thus far which result in both low gate count and quantum cost. In this thesis the AP algorithm is introduced. The goal of the algorithm is to drive quantum cost down by using multiple non-blocking orders, a breadth first search, and a quantum cost reduction transformation. The results shown by the AP algorithm demonstrate that the resulting quantum cost for well-known benchmarks are improved by at least 9% and up to 49%.
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Eyoh, Imo. "Interval type-2 Atanassov-intuitionistic fuzzy logic for uncertainty modelling." Thesis, University of Nottingham, 2018. http://eprints.nottingham.ac.uk/51441/.
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This thesis investigates a new paradigm for uncertainty modelling by employing a new class of type-2 fuzzy logic system that utilises fuzzy sets with membership and non-membership functions that are intervals. Fuzzy logic systems, employing type-1 fuzzy sets, that mark a shift from computing with numbers towards computing with words have made remarkable impacts in the field of artificial intelligence. Fuzzy logic systems of type-2, a generalisation of type-1 fuzzy logic systems that utilise type-2 fuzzy sets, have created tremendous advances in uncertainty modelling. The key feature of the type-2 fuzzy logic systems, with particular reference to interval type-2 fuzzy logic systems, is that the membership functions of interval type-2 fuzzy sets are themselves fuzzy. These give interval type-2 fuzzy logic systems an advantage over their type-1 counterparts which have precise membership functions. Whilst the interval type-2 fuzzy logic systems are effective in modelling uncertainty, they are not able to adequately handle an indeterminate/neutral characteristic of a set, because interval type-2 fuzzy sets are only specified by membership functions with an implicit assertion that the non-membership functions are complements of the membership functions (lower or upper). In a real life scenario, it is not necessarily the case that the non-membership function of a set is complementary to the membership function. There may be some degree of hesitation arising from ignorance or a complete lack of interest concerning a particular phenomenon. Atanassov intuitionistic fuzzy set, another generalisation of the classical fuzzy set, captures this thought process by simultaneously defining a fuzzy set with membership and non-membership functions such that the sum of both membership and non-membership functions is less than or equal to 1. In this thesis, the advantages of both worlds (interval type-2 fuzzy set and Atanassov intuitionistic fuzzy set) are explored and a new and enhanced class of interval type-2 fuzzy set namely, interval type-2 Atanassov intuitionistic fuzzy set, that enables hesitation, is introduced. The corresponding fuzzy logic system namely, interval type-2 Atanassov intuitionistic fuzzy logic system is rigorously and systematically formulated. In order to assess this thesis investigates a new paradigm for uncertainty modelling by employing a new class of type-2 fuzzy logic system that utilises fuzzy sets with membership and non-membership functions that are intervals. Fuzzy logic systems, employing type-1 fuzzy sets, that mark shift from computing with numbers towards computing with words have made remarkable impacts in the field of artificial intelligence. Fuzzy logic systems of type-2, a generalisation of type-1 fuzzy logic systems that utilise type-2 fuzzy sets, have created tremendous advances in uncertainty modelling. The key feature of the type-2 fuzzy logic systems, with particular reference to interval type-2 fuzzy logic systems, is that the membership functions of interval type-2 fuzzy sets are themselves fuzzy. These give interval type-2 fuzzy logic systems an advantage over their type-1 counterparts which have precise membership functions. Whilst the interval type-2 fuzzy logic systems are effective in modelling uncertainty, they are not able to adequately handle an indeterminate/neutral characteristic of a set, because interval type-2 fuzzy sets are only specified by membership functions with an implicit assertion that the non-membership functions are complements of the membership functions (lower or upper). In a real life scenario, it is not necessarily the case that the non-membership function of a set is complementary to the membership function. There may be some degree of hesitation arising from ignorance or a complete lack of interest concerning a particular phenomenon. Atanassov intuitionistic fuzzy set, another generalisation of the classical fuzzy set, captures this thought process by simultaneously defining a fuzzy set with membership and non-membership functions such that the sum of both membership and non-membership functions is less than or equal to 1. In this thesis, the advantages of both worlds (interval type-2 fuzzy set and Atanassov intuitionistic fuzzy set) are explored and a new and enhanced class of interval type-2 fuzz set namely, interval type-2 Atanassov intuitionistic fuzzy set, that enables hesitation, is introduced. The corresponding fuzzy logic system namely, interval type-2 Atanassov intuitionistic fuzzy logic system is rigorously and systematically formulated. In order to assess the viability and efficacy of the developed framework, the possibilities of the optimisation of the parameters of this class of fuzzy systems are rigorously examined. First, the parameters of the developed model are optimised using one of the most popular fuzzy logic optimisation algorithms such as gradient descent (first-order derivative) algorithm and evaluated on publicly available benchmark datasets from diverse domains and characteristics. It is shown that the new interval type-2 Atanassov intuitionistic fuzzy logic system is able to handle uncertainty well through the minimisation of the error of the system compared with other approaches on the same problem instances and performance criteria. Secondly, the parameters of the proposed framework are optimised using a decoupledextended Kalman filter (second-order derivative) algorithm in order to address the shortcomings of the first-order gradient descent method. It is shown statistically that the performance of this new framework with fuzzy membership and non-membership functions is significantly better than the classical interval type-2 fuzzy logic systems which have only the fuzzy membership functions, and its type-1 counterpart which are specified by single membership and non-membership functions. The model is also assessed using a hybrid learning of decoupled extended Kalman filter and gradient descent methods. The proposed framework with hybrid learning algorithm is evaluated by comparing it with existing approaches reported in the literature on the same problem instances and performance metrics. The simulation results have demonstrated the potential benefits of using the proposed framework in uncertainty modelling. In the overall, the fusion of these two concepts (interval type-2 fuzzy logic system and Atanassov intuitionistic fuzzy logic system) provides a synergistic capability in dealing with imprecise and vague information.
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Boyd, Richard Victor 1942. "PLAN GENERATION AND PROLOG (LOGIC, DECLARATIVE, WARPLAN)." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/291278.
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Long, Byron L. "Validity in a variant of separation logic." [Bloomington, Ind.] : Indiana University, 2009. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:3378369.
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Thesis (Ph.D.)--Indiana University, Dept. of Computer Science, 2009.Title from PDF t.p. (viewed on Jul 9, 2010). Source: Dissertation Abstracts International, Volume: 70-10, Section: B, page: 6348. Adviser: Daniel Leivant.
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Boskovitz, Agnes. "Data editing and logic : the covering set method from the perspective of logic /." View thesis entry in Australian Digital Theses, 2008. http://thesis.anu.edu.au/public/adt-ANU20080314.163155/index.html.
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Xu, Qing. "Optimization techniques for distributed logic simulation." Thesis, McGill University, 2011. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=96665.
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Gate level simulation is a necessary step to verify the correctness of a circuitdesign before fabrication. It is a very time-consuming application, especially in lightof current circuit sizes. Since circuits are continually growing in size and complexity,there is a need for more efficient simulation techniques to keep the circuit verificationtime acceptably small. The use of parallel or distributed simulation is such a technique.When executed on a network of workstations, distributed simulation is alsoa very cost-effective technique. This research focuses on optimization techniques forTime Warp based gate-level logic simulations. The techniques which are described inthis thesis are oriented towards distributed platforms. The first major contributionof this thesis was the creation of an object oriented distributed simulator, XTW. Ituses an optimistic synchronization algorithm and incorporates a number of knownoptimization techniques targeting different aspects of distributed logic simulation.XEQ, an O(1) event scheduling algorithm for this simulator was developed for usein XTW. XEQ enabled us to execute gate level simulations up to 9.4 times fasterthan the same simulator using a skip-list (O(lg n)) event queue. rb-messagea mechanism which reduces the cost of rollback in Time Warp was also developedfor use in XTW. Our experiments revealed that the rb-message mechanism reducedthe number of anti-messages sent in a Time Warp based logic simulation by 76%on average. Moreover, based on the observations that (1)not all circuits should besimulated in parallel and (2) different circuits achieve their best parallel simulationperformance with a different number of compute nodes, an algorithm that uses theK-NN machine learning algorithm was devised to determine the most effective softwareand hardware combination for a logic simulation. After an extensive trainingregime, it was shown to make a correct prediction 99% of the time on whether touse a parallel or sequential simulator. The predicted number of nodes to use on aparallel platform was shown to produce an average execution time which was notmore than 12% of the smallest execution time. The configuration which resulted inthe minimal execution time was picked 61% of the time. A final contribution of thisthesis is an effort to link together commercial single processor simulators making useof Verilog PLI.La simulation "gate-level" est une tape ncessaire pour vrifier la conformit dela conception d'un circuit avant sa fabrication. C'est un programme qui prendbeaucoup de temps, compte tenu particulirement de la taille actuelle des circuits.Ceux-ci ne cessant de se dvelopper en taille et en complexit, il y a un rel besoin detechniques de simulation plus efficaces afin de maintenir la dure de vrification ducircuit raisonnablement courte. Une de ces techniques consiste utiliser la simulationparallle ou distribue. Quand excute sur un rseau de postes de travail, la simulationdistribue se rvle galement tre une technique trs rentable. Cette recherche se concentresur l'optimisation des techniques de simulations "gate-level" logiques bases surTime Warp. Les techniques qui sont dcrites dans cet expos sont orientes vers lesplateformes distribues. La premire contribution majeure de cet expos a t la crationd'un simulateur distribu orient sur l'objet, XTW. Il utilise un algorithme de synchronisationoptimiste et incorpore un certain nombre de techniques d'optimisationconnues visant diffrents aspects de la simulation distribue logique. XEQ, un algorithmeprogrammateur d'vnements O(1) pour ce simulateur a t dvelopp pour treutilis dans XTW. XEQ nous permet d'excuter des simulations "gate-level" jusqu'9,4 fois plus rapides qu'avec le mme simulateur utilisant une suite d'vnement en"skip-list" (O(lg n)). "rb-message" – un mcanisme qui diminue le co?t de rductiondans Time Warp a galement t mis au point pour tre utilis dans XTW. Nos essaisont rvl que le mcanisme de "rb-message" permettait de diminuer le nombre des antimessagesenvoys au cours d'une simulation logique base sur Time Warp de 76 % enmoyenne. Il a t en outre con?u, en se basant sur les observations que (1) certainscircuits ne devraient pas tre simuls en parallle et (2) que diffrents circuits atteignentleur meilleure performance de simulation parallle avec un nombre diffrent de noeudsde calculs, un algorithme utilisant l'algorithme d'apprentissage de la machine K-NNafin de dterminer quelle tait l'association de logiciel et de matriel la plus efficacedans le cadre d'une simulation logique. l'issue d'un entra?nement approfondi, ilest apparu qu'il pouvait faire un pronostic juste 99 % tablissant quand utiliser unsimulateur parallle ou squentiel. Le nombre annonc de noeuds utiliser sur une plateformeparallle s'est avr permettre une dure d'excution moyenne gale 12 % de la pluscourte dure d'excution. La configuration ayant abouti la dure d'excution minimalea t reprise dans 61 % des cas. Dernire contribution apporte par cet expos, relier lessimulateurs commerciaux processeur unique utilisant Verilog PLI.