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1

Gössel, Michael. Memory architecture & parallel access. Amsterdam: Elsevier, 1994.

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2

Grun, Peter. Memory architecture exploration for programmable embedded systems. Boston, MA: Kluwer Academic Publishers, 2002.

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3

Grun, Peter. Memory architecture exploration for programmable embedded systems. Boston: Kluwer Academic Publishers, 2003.

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4

Tick, Evan. Memory performance of prolog architectures. Boston: Kluwer Academic Publishers, 1988.

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5

Grun, Peter. Memory architecture exploration for programmable embedded systems. Boston: Kluwer Academic Publishers, 2003.

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6

R, Van Rosendale John, and Institute for Computer Applications in Science and Engineering., eds. Programming distributed memory architectures using KALI. Hampton, VA: Institute for Computer Applications in Science and Engineering, NASA Langley Research Center, 1990.

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7

Eva, Kühn, ed. Virtual shared memory for distributed architectures. Huntington, N.Y: Nova Science Publishers, 2001.

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8

Memory systems and pipelined processors. Sudbury, Mass: Jones and Bartlett, 1996.

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9

Memory storage patterns in parallel processing. Boston: Kluwer Academic, 1987.

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10

Standley, Hilda M. Computer architecture evaluation for structural dynamics computations: Final technial report, project summary. Toledo, Ohio: Dept. of Computer Science, University of Toledo, 1989.

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11

Tobias, Orloff, Langley Research Center, and Institute for Computer Applications in Science and Engineering., eds. A parallel rendering algorithm for MIMD architectures. Hampton, Va: National Aeronautics and Space Administration, Langley Research Center, 1991.

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12

1953-, Dubois Michel, and Thakkar S. S, eds. Cache and interconnect architectures in multiprocessors. Boston: Kluwer Academic Publishers, 1990.

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13

International Symposium on Computer Architecture (26th 1999 Atlanta, Ga.). Proceedings of the 26th International Symposium on Computer Architecture: May 2-4, 1999, Atlanta, Georgia. Los Alamitos, Calif: IEEE Computer Society, 1999.

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14

Dufrasne, Bertrand. IBM XIV Storage System: Concepts, architecture, and usage. 2nd ed. [Poughkeepse, NY]: IBM, International Technical Support Organization, 2009.

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15

Corporation, International Business Machines, ed. IBM XIV Storage System: Concepts, architecture, and usage. Poughkeepsie, NY: IBM, 2009.

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16

Oualha, Nouha. Peer-to-peer storage: Security and protocols. New York: Nova Science Publishers, 2010.

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17

Programmed visions: Software and memory. Cambridge, Mass: MIT Press, 2011.

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18

Balasubramonian, Rajeev. Multi-core cache hierarchies. San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA): Morgan & Claypool, 2011.

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19

Analysis of cache performance for operating systems and multiprogramming. Boston: Kluwer Academic Publishers, 1989.

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20

Machinery, Association for Computing, and IEEE Computer Society, eds. ASPLOS-VII proceedings: Seventh International Conference on Architectural Support for Programming Languages and Operating Systems, Cambridge, Massachusetts, October 1-5, 1996. New York: Association for Computing Machinery, 1996.

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21

Baram, Yoram. Ground-state coding in partially connected neural networks. Moffett Field, Calif: National Aeronautics and Space Administration, Ames Research Center, 1989.

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22

Center, Ames Research, ed. Ground-state coding in partially connected neural networks. Moffett Field, Calif: National Aeronautics and Space Administration, Ames Research Center, 1989.

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23

Baram, Yoram. Ground-state coding in partially connected neural networks. Moffett Field, Calif: National Aeronautics and Space Administration, Ames Research Center, 1989.

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24

Tick, Evan. Memory Performance of Prolog Architectures. Boston, MA: Springer US, 1987.

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25

N, Jayasimha D., Pillay Sasi Kumar, and Lewis Research Center. Institute for Computational Mechanics in Propulsion., eds. Parallel Navier-Stokes computations on shared and distributed memory architectures. [Cleveland, Ohio]: National Aeronautics and Space Administration, Lewis Research Center, Institute for Computational Mechanics in Propulsion, 1995.

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26

N, Jayasimha D., Pillay Sasi Kumar, and Lewis Research Center. Institute for Computational Mechanics in Propulsion., eds. Parallel Navier-Stokes computations on shared and distributed memory architectures. [Cleveland, Ohio]: National Aeronautics and Space Administration, Lewis Research Center, Institute for Computational Mechanics in Propulsion, 1995.

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27

N, Jayasimha D., Pillay Sasi Kumar, and Lewis Research Center. Institute for Computational Mechanics in Propulsion., eds. Parallel Navier-Stokes computations on shared and distributed memory architectures. [Cleveland, Ohio]: National Aeronautics and Space Administration, Lewis Research Center, Institute for Computational Mechanics in Propulsion, 1995.

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28

Hadimioglu, Haldun. High Performance Memory Systems. New York, NY: Springer New York, 2004.

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29

Overman, Andrea L. Mapping implicit spectral methods to distributed memory architectures. Hampton, Va: Institute for Computer Applications in Science and Engineering, NASA Langley Research Center, 1991.

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30

William, Stallings. Computer organization and architecture: Designing for performance. 7th ed. Upper Saddle River, NJ: Pearson Prentice Hall, 2006.

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31

William, Stallings. Computer organization and architecture: Designing for performance. 4th ed. London: Prentice-Hall International (UK), 1996.

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32

William, Stallings. Computer organization and architecture: Designing for performance. 5th ed. Upper Saddle River, N.J: Prentice Hall, 2000.

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33

William, Stallings. Computer organization and architecture: Designing for performance. 6th ed. Upper Saddle River, NJ: Pearson Education, 2003.

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34

William, Stallings. Computer organization and architecture: Designing for performance. 4th ed. Upper Saddle River, N.J: Prentice Hall, 1996.

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35

William, Stallings. Computer organization and architecture: Designing for performance. 6th ed. Upper Saddle River, N.J: Prentice Hall Pearson Education International, 2003.

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36

E, Hayder M., Pillay S. K, and United States. National Aeronautics and Space Administration., eds. Parallelizing Navier-Stokes computations on a variety of architectural platforms. [Washington, D.C: National Aeronautics and Space Administration, 1997.

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37

E, Hayder M., Pillay S. K, and United States. National Aeronautics and Space Administration., eds. Parallelizing Navier-Stokes computations on a variety of architectural platforms. [Washington, D.C: National Aeronautics and Space Administration, 1997.

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38

E, Hayder M., Pillay S. K, and United States. National Aeronautics and Space Administration., eds. Parallelizing Navier-Stokes computations on a variety of architectural platforms. [Washington, D.C: National Aeronautics and Space Administration, 1997.

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39

E, Hayder M., Pillay S. K, and United States. National Aeronautics and Space Administration., eds. Parallelizing Navier-Stokes computations on a variety of architectural platforms. [Washington, D.C: National Aeronautics and Space Administration, 1997.

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40

Kogge, Peter M. Processor-In-Memory (PIM) based architectures for petaflops potential massively parallel processing: Final report, NASA grant NAG 5-2998. [Washington, DC: National Aeronautics and Space Administration, 1996.

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41

United States. National Aeronautics and Space Administration., ed. Processor-In-Memory (PIM) based architectures for petaflops potential massively parallel processing: Final report, NASA grant NAG 5-2998. [Washington, DC: National Aeronautics and Space Administration, 1996.

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42

United States. National Aeronautics and Space Administration., ed. Processor-In-Memory (PIM) based architectures for petaflops potential massively parallel processing: Final report, NASA grant NAG 5-2998. [Washington, DC: National Aeronautics and Space Administration, 1996.

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43

United States. National Aeronautics and Space Administration., ed. Processor-In-Memory (PIM) based architectures for petaflops potential massively parallel processing: Final report, NASA grant NAG 5-2998. [Washington, DC: National Aeronautics and Space Administration, 1996.

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44

Institute for Computer Applications in Science and Engineering., ed. Parallel volume ray-casting for unstructured-grid data on distributed-memory architectures. Hampton, VA: Institute for Computer Applications in Science and Engineering, NASA Langley Research Center, 1995.

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45

Institute for Computer Applications in Science and Engineering., ed. Parallel volume ray-casting for unstructured-grid data on distributed-memory architectures. Hampton, VA: Institute for Computer Applications in Science and Engineering, NASA Langley Research Center, 1995.

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46

T, Chronopoulos A. Implementation of s-step methods on parallel vector architectures. Urbana, IL (1304 W. Springfield Ave., Urbana 61801): Dept. of Computer Science, University of Illinois at Urbana-Champaign, 1987.

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47

William, Stallings. Computer organization and architecture: Principles of structure and function. New York: Macmillan, 1987.

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48

William, Stallings. Computer organization and architecture: Principles of structure and function. 2nd ed. New York: Macmillan, 1990.

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49

William, Stallings, and William Stallings. Computer organization and architecture: Principles of structure and function. 3rd ed. New York: Macmillan, 1993.

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50

Macii, Alberto. Memory Design Techniques for Low Energy Embedded Systems. Boston, MA: Springer US, 2002.

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