Dissertations / Theses on the topic 'Conception et mesures de circuits'
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Hély, David. "Conception en vue du test de circuits sécurisés." Montpellier 2, 2005. http://www.theses.fr/2005MON20123.
Full textOuchelouche, Larbi. "Conception et réalisation d'un adaptateur électronique microonde programmable pour mesures de bruit sous pointes." Limoges, 1993. http://www.theses.fr/1993LIMO0187.
Full textRazafindraibe, Hanitriniaina Mamitiana Alin. "Analyse et amélioration de la logique double rail pour la conception de circuits sécurisés." Montpellier 2, 2006. http://www.theses.fr/2006MON20117.
Full textSaliva, Marine. "Circuits dédiés à l'étude des mécanismes de vieillissement dans les technologies CMOS avancées : conception et mesures." Thesis, Aix-Marseille, 2015. http://www.theses.fr/2015AIXM4337.
Full textIn the circuit development, specific attention must be paid to the MOS device reliability as a building block as well as a prototype reference circuit (CMOS) during the technology development. At device level, the different degradation mechanisms are characterized. In the final prototype, the product is characterized in accelerated aging conditions, but only the macroscopic parameters can be extracted. One objective of this thesis has been to link the circuit or system reliability and its building blocks. Also, the second important point has consisted in the development of 'smart' test solutions to improve testability and gain up structures so as to highlight the circuits aging monitoring and degradation compensation. Another family of ‘smart’ solutions has involved reproducing directly in the structure the excitement or the actual configuration as it is seen by elementary circuits or devices during their usage life (lab in situ)
Almustafa, Mohamad. "Modélisation des micro-plasmas, conception des circuits micro-ondes, Coupleur Directionnel Hybride pour Mesures et des applications en Télécommunication." Phd thesis, Toulouse, INPT, 2013. http://oatao.univ-toulouse.fr/14170/1/almustafa.pdf.
Full textBérubé, Benoit-Louis. "Développement d'une technologie NMOS pour la conception de fonctions électroniques avancées." Mémoire, Université de Sherbrooke, 2010. http://savoirs.usherbrooke.ca/handle/11143/1567.
Full textLeloir, Sébastien. "Etude, conception et réalisation d'un banc de caractérisation " Source-Pull / Load-Pull multiharmonique " pour applications radars." Rouen, 2005. http://www.theses.fr/2005ROUES010.
Full textThis study presents the investigation, the design and the realization of a Source-Pull / Load-Pull multiharmonic bench able to experimentally characterize microwave power devices entering the radar's line up. In CW or pulsed mode, the bench is able to make a synthesis of impedances at the fundamental frequency and at the two first harmonics, and is also able to reconstitute, in real time, the temporal waveforms at both components ports. Perfectly adapted to the needs of Thales Air Defence, this tool will allow in long term : to design the microwave non-linear circuit optimised with power added, power efficiency; to validate non-linear models of devices used in the simulation softwares. The characterization system implemented is independent of the work frequency, the component nature and the power levels. In order to show the interest of its exploitation in radar's domain, a first characterization has been realized on HBT transistor
Kasbari, Abed-Elhak. "Conception et caractérisation de circuits synchrones en logiques ECL pour les communications à 40 Gbits/s." Cergy-Pontoise, 2003. http://www.theses.fr/2003CERG0179.
Full textThis work is our contribution to the design and characterisation methods for very high speed integrated circuits. These circuits are essential to the long haul optical fiber communication systems. We present some specific design problems of high speed circuits. A design method for the emitter coupled logic (ECL) elementary blocks is developed. Furthermore, new CAD tools are introduced to minimise the switching times. The measurement setup has been improved to allow circuits characterisation at 40 Gbit/s. Integrated circuits have been designed and fabricated to validate this methods. Two different heterojunction bipolar transistor technologies have been used: a production-level SiGe technology and a high frequency performances InP technology. This work led to excellent experimental results. DFF circuits show full-rate clock operation beyond 40 Gbit/s and demultiplexers achieve 40 Gbit/s. Characterisation at a higher bit rate has been limited by the measurement setup
Tounsi, Patrick. "Méthodologie de la conception thermique des circuits électroniques hybrides et problèmes connexes." Toulouse, INSA, 1992. http://www.theses.fr/1992ISAT0039.
Full textBelhaj, Mohamed Moez. "Conception et caractérisation des dispositifs micro-ondes pour la fabrication de circuits à base de graphène." Thesis, Lille 1, 2016. http://www.theses.fr/2016LIL10048/document.
Full textThis work was carried out under the project involving GRACY IEMN and other research laboratories: CALISTO and IMS Bordeaux. This manuscript reports a comprehensive overview of studies and advanced conducted as part of this thesis in the Institute of Electronics, Microelectronics and Nanotechnology (IEMN) in CARBON group. The main reflection axis of this work is based on the design, modeling and characterization of active and passive devices on flexible and rigid substrates for the development of new components and electronic circuits with increasingly important performance criteria. During this work, the focus was mainly focused on the essential steps to achieving integrated circuit millimeter wave using coplanar technology by inkjet printing and field effect transistors based on graphene (GFETs). This memory in particular shows the importance and potential of graphene for integration into electronic circuits. In addition, special attention was paid on modeling and characterization techniques related to passive devices on flexible substrates. Therefore, a characterization bench of these elements on flexible substrate has been developed during this thesis to verify and consolidate their behavior experimentally
Belquin, Jean-Maxence. "Développement de bancs de mesures et de modèles de bruit de HEMT pour la conception de circuits "faible bruit" en gamme d'ondes millimétriques." Lille 1, 1997. http://www.theses.fr/1997LIL10035.
Full textKabouche, Riad. "Caractérisations de composants et Conceptions de circuits à base d’une filière émergente AlN/GaN pour applications de puissance en gamme d’ondes millimétriques." Thesis, Lille 1, 2017. http://www.theses.fr/2017LIL10200/document.
Full textGallium Nitride (GaN) technology is now the ideal candidate for high power applications in the millimeter wave range. The characteristics of this material enable high voltage operation at high frequency, as illustrated by its breakdown field and high electron saturation velocity. This research work has initially allowed the development of a test bench capable of "Large Signal" characterization, called LoadPull up to Q band, in continuous-wave and pulsed mode of this emerging technology. Indeed, the high power density generated by the GaN technology has made the development of this bench unavoidable and relatively unique. In addition, this study has focused on the characterization of several innovative types of devices that have demonstrated state-of-the-art performance, with a power added efficiency (PAE) above 46% associated to a power density of 4.5 W/mm obtained for an operating frequency of 40 GHz in continuous-wave. Finally, this work aimed the design and fabrication of two power amplifiers on silicon substrate (based on the industrial OMMIC technology) in the Ka-band, showing the possibility of achieving MMIC type circuits from advanced GaN transistors technology. These two amplifiers were designed for specific purposes: combining high power and high PAE performance and pushing bandwidth limits
Pham, Thi Dao. "Conception et développement d’étalons pour la mesure des paramètres S en mode mixte de circuits intégrés et méthodes associées." Thesis, Université Paris-Saclay (ComUE), 2019. http://www.theses.fr/2019SACLT032/document.
Full textDifferential circuits are widely used in the design of high frequency components mainly because of their better noise immunity. These circuits can be characterized using mixed-mode S parameters (differential- and common-mode S-parameters and cross-mode terms). Furthermore, the trend toward miniaturization and integration of microwave devices increases the need for planar or coplanar microwave integrated circuits such as micro-strip lines or coplanar waveguides. The ungrounded coplanar waveguide structure with all the conductors located on the same side of the substrate eliminates the need for via-holes, and thus simplifies manufacturing and prevents the appearance of some parasitic elements. From the viewpoint of electrical metrology, it is necessary to establish the traceability of the mixed-mode S-parameter measurements to the International System of Units (SI). The Multimode Thru-Reflect-Line (TRL) calibration method, derived from the commonly-used TRL calibration for S-parameter measurements of single-ended circuits, is particularly well suited for this purpose as the standards are traceable via dimensional measurements. The characteristic impedance, which defines the reference impedance of the measurement system, can be achieved from the propagation constants determined during the Multimode TRL calibration and the capacitances per unit length of the transmission line.We present the first design and realization of Multimode TRL calibration and verification kits using coupled coplanar lines in the "Ground - Signal - Ground - Signal - Ground" configuration on quartz (SiO2), the low-loss substrate, for on-wafer mixed-mode S-parameter measurements from 1 GHz to 40 GHz. Measurements are performed using two methods: the “one-tier” technique, based on the Multimode TRL calibration procedure, determines and corrects all systematic errors. The “two-tier” approach, in which the Multimode TRL is applied at the second-tier, is applied to measurement data that were partially corrected by the first calibration. The feasibility and the validation of the methods are demonstrated by measurements of matched, mismatched and unbalanced lines and T-attenuators showing good agreement between simulated and measured results.The propagation of uncertainty can be derived by the calculation of partial derivatives using the Metas.Unclib tool or by the numerical approach based on the Monte Carlo technique. The accuracy of on-wafer S-parameter measurements depends on sources of influence attributed to the measurements and to the imperfections of the standards such as the VNA noise and non-linearity, the cable stability, the measurement repeatability, and the sensitivity in calibration standards’ realization. We focus, first and foremost, on the propagation of uncertainties related to the repeatability of the standards and the device under test measurements to the corrected mixed-mode S-parameters of the mismatched line. The results show that the partial derivatives approach based on an approximation of the first-order Taylor series cannot be accurately used due to the significant influences of non-linear functions in the Multimode TRL algorithm. The Monte Carlo method is then more precise although it requires very long computation time
Kaiser, Andreas. "Conception de filtres continus CMOS micropuissance et leur application dans un système de mesure de déplacement linéaire." Lille 1, 1990. http://www.theses.fr/1990LIL1A001.
Full textLeroy, Damien. "Étude des modes de perturbation et susceptibilité des circuits numériques aux collisions de particules et aux attaques laser." Metz, 2006. http://docnum.univ-lorraine.fr/public/UPV-M/Theses/2006/Leroy.Damien.SMZ0628.pdf.
Full textMore and more sensitive data are stored inside smart cards, like bank account or car access codes. Recently, these security circuits have become a target for hackers who try to abuse these data. To achieve this goal, these attackers use the state of the art technologies like fault injection. To comply with the smart card market requirements, designers have to build protections against these attacks while keeping design costs as low as possible. These constraints should lead to a cost-efficient design and benefit from dedicated automatic protection methodologies. In this thesis we first study radiation sources able to tamper with silicon circuit behavior, and then we reveal similarities between laser attacks and radiation effects on a circuit. Then we show the specificities of secure circuit design and the spectrum of attacks used by hackers. The third part characterizes Single Event Transients (SET). A design methodology is proposed and implemented in two circuits, one dedicated to measuring laser-induced SET duration in logic gates, the other dedicated to measuring gate sensitivity to neutrons. This work concludes the review of results obtained after a laser shooting experiment campaign
Defrance, Nicolas. "Caractérisation et modélisation de dispositifs de la filière nitrure pour la conception de circuits intégrés de puissance hyperfréquences." Lille 1, 2007. https://pepite-depot.univ-lille.fr/LIBRE/Th_Num/2007/50376-2007-Defrance.pdf.
Full textTournier, Eric. "Conception et intégration silicium de circuits et SoC analogiques et numériques micro-ondes appliqués à la synthèse agile de fréquences." Habilitation à diriger des recherches, Université Paul Sabatier - Toulouse III, 2010. http://tel.archives-ouvertes.fr/tel-00629717.
Full textGoral, Benoit. "Technique et Méthodologie de Conception du Réseau de Distribution d'Alimentation d'une Carte Electronique Rapide à Haute Densité d'Interconnexion." Thesis, Université Paris-Saclay (ComUE), 2017. http://www.theses.fr/2017SACLN037/document.
Full textToday's economical context leads electronics and high-tech corporations not only to innovate with a sustained rhythm but also to reduce the design cycle of new products. In order to remain competitive, these corporations must release regularly new products with new functionalities or enhancing performances of the last generation of this product. The enhancement from one generation of the product to the other can be quantified by the speed of execution of a task, the package size or form factor, the battery life and power consumption.The design methodology following these constraints is thus very tough. Indeed, integration of new functionalities as miniaturization of products imply a densification of the printed circuit board. The number of layer in the stack up is increased, isolation between nets is reduced, the use of integrated circuits embedding different functions as SOC or SIP implies a multiplication of the number of voltages. Moreover the increase of circuit performances implies a increasing data rate exchanged between component of the same printed circuit board and occasioning a widening of the reference clock and signal frequency spectrum. These design constraints are the root cause of the apparition of electromagnetic compatibility, signal integrity and power integrity issues. Failure risks must then be limited by fully understanding phenomenon occurring on the board by, on one side, realizing a precise dimensioning pre layout analysis aiming the elimination or reduction of the issues at the beginning of the design cycle, and on the other side, validating the layout by post layout simulation once the printed circuit board routed.This study proposed by Thales Communication and Security in collaboration with public research laboratory SATIE (System and Application of Energy and Information Technologies) of Ecole Normale Supérieure de Cachan within a industrial convention for development through research aims to develop a design methodology for power delivery network of digital printed circuit board with the goal of ensuring good behavior without or by reducing the number of prototypes.The first chapter of this manuscript include an introduction to the context of the study, a precise description of the studied system and the physical phenomenon ruling its behavior, and finally a state of the art of the power integrity technique analysis. A presentation of the test vehicle, designed during the work and support of all measurement results will constitute the focus of second chapter. This chapter presents and describes all the scenarios and implementations created for the observation and measurement of Power Integrity phenomenon and realise measurement-simulation results correlation. In a third part, modeling techniques of each element of the Power Delivery Network are described. The validity of the models is proven by correlating simulation results of each element with measurement results. The fourth chapter presents the analysis and design methodology developed from the results of the different modeling techniques presented in the previous chapter. Simulation tools and their configuration are precisely described and simulation results are compared with measurement results obtained on the test vehicle for the whole system. In the fifth chapter, the interest of power delivery network model will be extended to signal integrity analysis demonstrating how including this model allows to obtain simulation results closer from measurement results by running Signal Integrity Power aware simulation. Finally, the last part of this document synthetizes the work realized and presented in this document, takes a critical look on it and proposes future works and orientations to extend knowledges and understanding of Power Integrity Phenomenon
Vũ, Văn Yêm. "Conception et réalisation d'un sondeur de canal multi-capteur utilisant les corrélateurs cinq-ports pour la mesure de propagation à l'intérieur des bâtiments /." Paris : École nationale supérieure des télécommunications, 2006. http://catalogue.bnf.fr/ark:/12148/cb40208331v.
Full textLucas, de Peslouan Pierre-Olivier. "Conception orientée délai : étude, développement et réalisation d’une boucle à verrouillage de phase large bande stabilisée par une boucle à verrouillage de délai." Thesis, Bordeaux 1, 2011. http://www.theses.fr/2011BOR14265/document.
Full textThe explosion of the wireless communication market is largely responsible of the expansion for RF communication standards for voice and data. Nowadays, each one of them must be integrated in one mobile terminal.However, this trend is opposed to the constraints of low cost, which tend to reduce the size of the electronics in a mobile terminal, but also the constraints of reduced consumption for greater autonomy for wireless systems. It is then around these technological and technical barriers that focus an important part of efforts to « R & D » today. Thus, the objective of the work presented is based on research and development of an architecture that contributes to improve the performances of the central block of transceivers: the local oscillator.The innovative architecture of multistandard synthesizer realized is based on the principle of Delay Oriented Design (DOD). A new technique of stabilization, based on the superposition of a delay and a phase locked loop, is proposed to expand the bandwidth. From study system to measurements through the behavioral comportment and implementation of the circuit, the various stages when designing an RF system are presented. Simulations and measurements have demonstrated the ability of the synthesizer to cover a frequency band between 1.6 and 3.5 GHz with a reference signal at 500MHz, but also to stabilize a broadband architecture
Chauvel, Dominique. "Mise en oeuvre de techniques de mesures cryogéniques pour la caractérisation hyperfréquences de circuits supraconducteurs à haute Tc : Application aux résonateurs planaires et conception d'oscillateurs à transistors HEMT refroidis." Lille 1, 1993. http://www.theses.fr/1993LIL10173.
Full textSkika, Abdelali. "Conception et caracterisation des circuits micro-ondes a base de supraconducteur a haut t c : mesure de l'impedance caracteristique mesure de l'impedance de surface." Paris 6, 1999. http://www.theses.fr/1999PA066649.
Full textLelong, Lionel. "Architecture SoC-FPGA pour la mesure temps réel par traitement d'images. Conception d'un système embarqué : imageur CMOS et circuit logique programmable." Saint-Etienne, 2005. http://www.theses.fr/2005STET4008.
Full textThe measurements method by PIV (Particle Image Velocimetry) is a technique to measure a motion vector field in a non-intrusive way and multi points. This technique uses the cross-correlation algorithm between two images to estimate the motion. The computation quantity required by this method limits its use to off-line processing with computer. The computers performances remain insufficient for this type of applications under constraint real time on high data rates. Within sight of these specific needs, the definition and the design of dedicated architectures seem to be an adequate solution to reach significant performances. The evolution of the integration levels allows the development of structures dedicated to image processing in real time at low prices. We propose a hardware implementation of cross-correlation algorithm adapted to internal architecture of FPGA with an aim of obtaining the real time PIV. In this thesis, we were interested in the architecture design of System on-a-Chip dedicated to physical measurements of parameters by real time image processing. This is a hierarchical and modular architecture dedicated to applications of “Dominant input data flow”. This hierarchical description allows a modification of number and/or nature of elements without architecture modifications. For one measurement computation, it needs 267 µs with a FPGA at the frequency of 50 MHz. To estimate the system performances, a CMOS image sensor was connected directly to the FPGA. That makes it possible to carry out a compact, dedicated and easily reuse system. An architecture made up of 5 computation modules allows satisfying the constraint of real time processing with this prototype
Vũ, Văn Yem. "Conception et réalisation d'un sondeur de canal multi-capteur utilisant les corrélateurs "cinq-ports" pour la mesure de propagation à l'intérieur des bâtiments." Paris, ENST, 2005. http://www.theses.fr/2005ENST0052.
Full textThe five-port correlator in microstrip technology consists of a ring with 5 arms and three diode power detectors. The ratio of two waves (Radio Frequency and Local Oscillator) is determined as a linear combination of the power levels measured at the five -port's outputs. Advantages of using five-port are its low-cost, its less sensibility to phase and amplitude imbalances and its operation in a wide frequency band. We propose a spatio-temporal channel sounder that consists of an 8 quasi-Yagi antenna elements and of 8 five-ports at reception The channel sounder designed for indoor propagation measurements follows us to measure time delay (TOA: Time Of Arrival) and Direction Of Arrival (DOA) in azimuth and in elevation of multi-path signals simultaneously. The DOA is estimated by measuring the phase difference of signals picked up by an antenna array and the estimation of TOA is based on the phase difference measured at two successive frequencies in the band from 2. 3 GHz to 2. 5 GHz with frequency step of 4 MHz at one five-port. The high resolution algorithm MUSIC (Multiple Signal Classification) associated with spatial smoothing pre-processing is used for TOA and DOA estimation. The simulation and measurement results show that we can estimate a number of signals bigger than the number of antenna elements. The proposed channel sounder has a low-cost and the measurement is performed simultaneously
Gomina, Kamil. "Méthodologie et développement de solutions pour la sécurisation des circuits numériques face aux attaques en tensions." Thesis, Saint-Etienne, EMSE, 2014. http://www.theses.fr/2014EMSE0751.
Full textGeneral use products as mobile phones or smartcards manipulate confidential data. As such, the circuits composing them are more and more prone to physical attacks, which involve a threat for their security. As a result, SoC designers have to develop efficient countermeasures without increasing overall cost and complexity of the final application. The analysis of existing attacks on digital circuits leads to consider power attacks, in advanced technology nodes.First of all, the power signature of a circuit was determined at design time. To do so, an electrical model was suggested based on the current consumption and the overall power grid capacitance. The methodology to extract these parameters, as well as the evaluation of the model are presented. This model allows designers to anticipate information leakage at design time and to quantify the protection of countermeasures, as the use of integrated decoupling capacitors. Then, the study was dedicated to power glitch attacks. The different fault injection mechanisms were analyzed in details. From then on, a set of detection circuits were suggested and evaluated at design time and on silicon by electrical tests. Both the theoretical analysis and the given methodology were confirmed by the test campaigns.This work demonstrated that the design of low-cost solutions against passive and active power attacks can be achieved, and used in a large scale product development
Joaquim, da Rolt Jean. "Testabilité versus Sécurité : Nouvelles attaques par chaîne de scan & contremesures." Thesis, Montpellier 2, 2012. http://www.theses.fr/2012MON20168.
Full textIn this thesis, we firstly analyze the vulnerabilities induced by test infrastructures onto embedded secrecy in digital integrated circuits dedicated to cryptography. Then we propose new scan-based attacks and effective countermeasures. Scan chains insertion is the most used technique to ensure the testability of digital cores, providing high-fault coverage. However, for ICs dealing with secret information, scan chains can be used as back doors for accessing secret data, thus becominga threat to device's security. We start by describing a series of new attacks that exploit information leakage out of advanced Design-for-Testability structures such as response compaction, X-Masking and partial scan. Conversely to some previous works that proposed that these structures are immune to scan-based attacks, we show that our new attacks can reveal secret information that is embedded inside the chip boundaries. Regarding the countermeasures, we propose three new solutions. The first one moves the comparison between test responses and expected responses from the AutomaticTest Equipment to the chip. This solution has a negligible area overhead, no effect on fault coverage. The second countermeasure aims to protect the circuit against unauthorized access, for instance to the test mode, and also ensure the authentication of the circuit. For thatpurpose, mutual-authentication using Schnorr protocol on Elliptic Curves is implemented. As the last countermeasure, we propose that Differential Analysis Attacks algorithm-level countermeasures, suchas point-blinding and scalar-blinding can be reused to protect the circuit against scan-based attacks
Margueron, Xavier. "Élaboration sans prototypage du circuit équivalent de transformateurs de type planar." Université Joseph Fourier (Grenoble), 2006. http://www.theses.fr/2006GRE10168.
Full textPlanar technology is very interesting for transformer used in aeronautical equipment because components are very thin so they can be used into small space. Unfortunately, dimensioning such transformers, when they work at frequencies upper than 100 KHz, is a difficult work because rules and tools conception are not the same as in standard winding transformers. In this thesis, transformers are represented by equivalent circuits and they are identified by impedance measurements. Due to the high number of circuit parameters, optimization of such component will be compromised if parameters computations were based on fem simulations. That is why we have focused this work on analytical computation. The goal is to deduce equivalent circuit parameters with analytical calculation based on physic and geometric caracterisitics. For example, each element of the static leakeage transformer can be deduced using PEEC formulas. Then, problems due to parallel windings, which always appear when transformer current are close to hundred Amperes, are studied. A simple analytical calculation based on one dimensional propagation enable to realize equivalent circuit and Pspice simulations in order to find quickly the best arrangement of windings conductors. In the last part, copper losses in transformers and also in rectangular conductors are studied. Solutions are tested by fem simulations in order to reduce eddy current losses. Multipolar development is finally used for optimizing these losses
Chambon, Cédric. "Etude du bruit électrique dans les dispositifs fonctionnant en régime non linéaire. Application à la conception d'amplificateurs micro-ondes faible bruit." Phd thesis, Université Paul Sabatier - Toulouse III, 2007. http://tel.archives-ouvertes.fr/tel-00206284.
Full textHaboubi, Walid. "Développements de circuits Rectennae bi-polarisation, bi-bande pour la récupération et conversion d’énergie électromagnétique à faible niveau." Thesis, Paris Est, 2014. http://www.theses.fr/2014PEST1089/document.
Full textImproving energy autonomy of communication systems constitutes one of the major concerns for their massive deployment in our environment. We want to make these electronic devices (sensors and sensor networks) completely autonomous, avoiding the embedded energy sources that require replacement operations or periodic charging. Among the available energy sources that can be harvested, there are electromagnetic waves. The device that can capture this energy and convert it into useful DC power is called Rectenna (Rectifying antenna), combining antenna with diode-based rectifier. In recent few years, rectennas have reached a significant number of papers in the literature. The main challenge consists in improving performances in term of efficiency, in an attempt to overcome the electromagnetic wave attenuation and the low available field level. According to this context, this PhD work supported by the ANR project REC-EM has taken place. In this study, we have developed, designed and characterized planar structures that have interesting properties:- In term of orthogonal polarizations, so energy harvesting becomes feasable regardless the arbitrary orientation of the incident wave on the rectenna. A dual-circularly polarized rectenna at 2.45 GHz with dual-access will be set up to overcome the 3 dB power loss in the case of linearly-polarized incident wave with unknown orientation.- In term of multiple resonances, so the amount of total RF power collected by the antenna can be increased and consequently the converted DC power level can also be improved. A dual-frequency rectenna (1.8 and 2.45 GHz) with single access will be designed, as well as a rectenna based upon a dual-frequency antenna array.- In term of size compactness by avoiding the use of the HF filter between the antenna and the rectifier for all developed rectenna structures during this work. In all cases, it will be necessary to define the most suitable rectifier topology to each antenna and select, if it is appropriated, the optimum DC recombination technique to overcome the effects of RF power imbalance that may occur between the different antenna accesses. Besides, single-diode circuits will be designed and fulfilled for each structure. Finally, we will miniaturize the dual-circularly polarized dual-access antenna, and exploit it to power a LCD display temperature sensor. To enhance the DC voltage level required to activate the sensor, a DC-DC converter is inserted between the rectenna and the sensor. Such energy management device should be able to operate under low delivered DC power. Two converters will be used. The first one is developed by Ampere Lab at Ecole Centrale de Lyon and SATIE Lab at ENS Cachan. This converter was the subject of another dissertation also supported by the ANR under the REC-EM project
Majek, Cédric. "CONTRIBUTION A L'ETUDE D'UN SYNTHETISEUR DE FREQUENCE POUR OBJETS COMMUNICANTS MULTISTANDARDS EN TECHNOLOGIE CMOS SOI." Phd thesis, Université Sciences et Technologies - Bordeaux I, 2006. http://tel.archives-ouvertes.fr/tel-00188659.
Full textVrignon, Bertrand. "Caractérisation et optimisation de l'émission électromagnétique de systèmes sur puce." Toulouse, INSA, 2005. http://eprint.insa-toulouse.fr/archive/00000157/.
Full textChusseau, Laurent. "Contribution à la conception de circuits intégrés AsGa : modélisation du MESFET AsGa et étude des effets de propagation et de couplage dans les CI logiques BFL AsGa : caractérisation en bruit des transistors hyperfréquence faible bruit AsGa." Paris 11, 1986. http://www.theses.fr/1986PA112024.
Full textThis work presents two contributions to the CAO of GaAs Monolithic Integrated Circuits. A/ The study of the effects of propagation and coupling on GaAs BFL logic circuits with a new time simulator : MACPRO. A MESFET model adapted to high speed digital circuits was established as well as the signal degradation in BFL circuits due to signal carrying lines as well as bias lines ( Thesis n°3862, Paris-Sud University, Orsay) b/ The design of an automatic noise measurement set up for law-noise microwave GaAs transistors. A programmable input tuner was fabricated and a new method for the numerical extraction of the four noise parameters from the measurements was validated. The results obtained for a short gate length TEGFET are included
Narasigadu, Caleb. "Conception d'une micro-cellule pour mesures d'équilibres de phases : mesures et modélisation." Phd thesis, École Nationale Supérieure des Mines de Paris, 2011. http://pastel.archives-ouvertes.fr/pastel-00679369.
Full textMalladi, Venkata Subba Rao Saucier Gabrièle. "Conception électrique et implantation de circuits intégrés." S. l. : Université Grenoble 1, 2008. http://tel.archives-ouvertes.fr/tel-00300500.
Full textFouilhoux, Pierre. "Graphes k-partis et conception de circuits VLSI." Clermont-Ferrand 2, 2004. http://www.theses.fr/2004CLF21555.
Full textGarcia, Florent. "Conception et optimisation de cellules d'interface." Montpellier 2, 1998. http://www.theses.fr/1998MON20246.
Full textBOULOUARD, ANDRE. "Conception de circuits et d'antennes hybrides et monolithiques micro-ondes." Rennes 1, 1996. http://www.theses.fr/1996REN10161.
Full textThuau, Ghislaine Saucier Gabrièle. "Conception logique et topologique en technologie MOS." S.l. : Université Grenoble 1, 2008. http://tel.archives-ouvertes.fr/tel-00308676.
Full textRegnery, Baptiste. "Les mesures compensatoires pour la biodiversité : conception et perspectives d'application." Paris 6, 2013. http://www.theses.fr/2013PA060563.
Full textDevelopment projects are currently one of the greatest threats to biodiversity. In this context, an increasing number of States are implementing offset policies to reconcile development projects with biodiversity conservation. However, biodiversity offsets have been challenged until know, both conceptually and practically. This thesis aims to strengthen scientific bases in offset designing and to provide tools to improve offset practices. Therefore, I first attempted to clarify the concepts of biodiversity offset and to highlight the main parameters to assess ecological losses and gains. Secondly, I studied at a national scale how offset measures for protected species were designed at a national scale. Among several results, I showed that taxonomic equivalences were strongly influenced by characteristics of impacted sites. I also pointed that current offsets took little account of common species and ecological functions. Thirdly, I studied the indicator value of tree microhabitats in forest. I showed that tree microhabitats can explain taxonomic and functional variations among birds and bats. These results provide opportunities to assess ecological trajectories and could help to improve offset designing in forest ecosystems. Finally, I attempted to provide solutions to take better into account spatial and temporal issues of biodiversity conservation through offset
Poupin, Yannick. "Conception et optimisation d'une base compacte millimétrique de mesures d'antennes." Limoges, 2002. http://www.theses.fr/2002LIMO0030.
Full textAntenna measurements require quasi-plane wave propagation between transmitter and receiver. Compact antenna test ranges (CATR) ensure this far-field condition at relatively short distances, generating a quasi-plane wave in near-field. This document presents all conception stages of a CATR, working from 10GHz to 50GHz, based on blended paraboloidal reflector. The study deals with FDTD characterization of a scale model reflector. Diffracted fields emitted from a fourth order surface discontinuity, a surface state (roughness) and minimal curvature of blended rolled edges, are quantificated. Performances are optimal when parasitic fields are minimized; reflector's behavior can be evaluated with a fast ray tracing (geometrical optics method). Then, conclusions are applied to the real device which can not be studied with FDTD method : space memory and computer time prohibitives
Beuchat, Jean-Luc. "Etude et conception d'opérateurs arithmétiques optimisés pour circuits programmables /." [S.l.] : [s.n.], 2001. http://library.epfl.ch/theses/?nr=2426.
Full textGachet, Pierrick. "Conception d'algorithmes et d'architectures systoliques synthèse automatique de circuits /." Grenoble 2 : ANRT, 1987. http://catalogue.bnf.fr/ark:/12148/cb37605243d.
Full textLevant, Jean-Luc. "Mise en place d'une démarche d'intégration des contraintes CEM dans le flot de conception des circuits intégrés." Rennes, INSA, 2007. http://www.theses.fr/2007ISAR0018.
Full textBouchelouk, Lakhdar. "Conception et validation de sondes pour les mesures en champ proche." Paris 11, 2006. http://www.theses.fr/2006PA112188.
Full textNowadays, technological progress allows to develop circuits with higher speed and smaller size. However, these improvements have also increased the problems of electromagnetic interferences (EMI) which are difficult to diagnose with conventional measurement systems. Accordingly, the IRSEEM has developed a test bench which allow to measure the electromagnetic field in the close vicinity of devices by using small probes and thus makes it possible to understand the various electromagnetic phenomena inherent to circuits operation. The aim of this work is to design probes which accurately reproduce the electromagnetic behaviour of circuits under test. Two types of probes were developed: the electric probes mainly made up of small electric dipoles are used to measure tangential components of the electric field. The monopole probe is better adapted for measuring the normal component of the electric field. The probes made up of small magnetic loops allow to measure the various components of the magnetic field. The performances of these wire and planar probes are studied according to their geometrical parameters. Parallel to measurements, simulations carried out by using various numerical techniques allow the validation of the various probes models. A confrontation between simulations and measurements results shows that small probes are qualitatively best adapted
Rios, José. "Etude et conception de dispositifs MOS-Thyristor autoamorçables et à blocage commandé." Toulouse 3, 1996. http://www.theses.fr/1996TOU30014.
Full textCoulibaly, Yacouba. "Conception et fabrication de circuits intégrés monolothiques microondes pour radiocommunications." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape17/PQDD_0007/MQ38670.pdf.
Full textLogeais, Elisabeth. "Conception et optimisation de circuits magnétiques polarisés application aux contacteurs /." Grenoble 2 : ANRT, 1988. http://catalogue.bnf.fr/ark:/12148/cb376152904.
Full textMartin, Didier. "Méthodologie de conception et d'optimisation de circuits ultrarapides pour télécommunications." Montpellier 2, 1995. http://www.theses.fr/1995MON20279.
Full textLogeais, Elisabeth. "Conception et optimisation de circuits magnétiques polarisés : application aux contacteurs." Grenoble INPG, 1988. http://www.theses.fr/1988INPG0098.
Full textLafond, Olivier. "Antennes et circuits actifs en ondes millimétriques - Etude et conception d'antennes reconfigurables." Habilitation à diriger des recherches, Université Rennes 1, 2008. http://tel.archives-ouvertes.fr/tel-00464648.
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