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Relevant bibliographies by topics / Configurable logic blocks

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Academic literature on the topic 'Configurable logic blocks'

Author: Grafiati

Published: 4 June 2025

Last updated: 8 July 2025

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Journal articles on the topic "Configurable logic blocks"

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Zhang, Jun Bin, Jin Yan Cai, and Dan Yang Li. "A Novel Fault Orientation Technique of FPGA Configurable Logic Blocks Based on Improved Shift Register." Applied Mechanics and Materials 347-350 (August 2013): 1602–6. http://dx.doi.org/10.4028/www.scientific.net/amm.347-350.1602.

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With the development of digital integrate circuit system which is based on Field Programmable Gate Arrays (FPGA), the request on FPGA test technique is becoming higher and higher. The Boundary Scan Technique and Built-In Self-Test (BIST) technique appear in succession, however, these techniques dont implement Configurable Logic Block (CLB) fault diagnose and fault orientation. Arrays-based technique was advanced, which also have some problems about masking of faults and too many reconfiguration times. According to these problems, A Novel Shift Register-based technique for Fault Orientation of FPGA Configurable Logic Blocks was advanced. The paper analyses the design theory about core circuit configure, and has important significance impact on Fault Orientation of FPGA Configurable Logic Blocks.

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Melnyk, Oleksandr, Viktoriia Kozarevych, and Mykola Butok. "Micro- and Nanocircuits with Configurable Logic." Electronics and Control Systems 3, no. 77 (2023): 47–52. http://dx.doi.org/10.18372/1990-5548.77.18003.

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The work considers controversial problems with the introduction of specialized and at the same time universal large integrated circuits, which are clarified at the initial stages of automated hierarchical design. Universal micro- and nanocircuits with configurable logic are created in the article to increase the efficiency of automated design systems. The article provides effective methods of programming multiplexer micro- and nanocircuits with configured logic for implementing Boolean and majority logic functions. The obtained results are used to configure the multiplexer functional blocks. With the help of modern automated design systems, comparative modeling of logic micro- and nanocircuits with configured logic was performed, which proved the adequacy of their functioning, the advantages of frequency and disadvantages of temperature characteristics of nanomultiplexer circuits.

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Ran, Y., and M. Marek-Sadowska. "Designing via-configurable logic blocks for regular fabric." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14, no. 1 (2006): 1–14. http://dx.doi.org/10.1109/tvlsi.2005.863196.

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Gan, Victor M., Yibin Liang, Lianjun Li, Lingjia Liu, and Yang Yi. "A Cost-Efficient Digital ESN Architecture on FPGA for OFDM Symbol Detection." ACM Journal on Emerging Technologies in Computing Systems 17, no. 4 (2021): 1–15. http://dx.doi.org/10.1145/3440017.

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The echo state network (ESN) is a recently developed machine-learning paradigm whose processing capabilities rely on the dynamical behavior of recurrent neural networks. Its performance outperforms traditional recurrent neural networks in nonlinear system identification and temporal information processing applications. We design and implement a cost-efficient ESN architecture on field-programmable gate array (FPGA) that explores the full capacity of digital signal processor blocks on low-cost and low-power FPGA hardware. Specifically, our scalable ESN architecture on FPGA exploits Xilinx DSP48E1 units to cut down the need of configurable logic blocks. The proposed architecture includes a linear combination processor with negligible deployment of configurable logic blocks and a high-accuracy nonlinear function approximator. Our work is verified with the prediction task on the classical NARMA dataset and a symbol detection task for orthogonal frequency division multiplexing systems using a wireless communication testbed built on a software-defined radio platform. Experiments and performance measurement show that the new ESN architecture is capable of processing real-world data efficiently for low-cost and low-power applications.

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Raj, Marshal, Lakshminarayanan Gopalakrishnan, Seok-Bum Ko, Nagi Naganathan, and N. Ramasubramanian. "Configurable Logic Blocks and Memory Blocks for Beyond-CMOS FPGA-Based Embedded Systems." IEEE Embedded Systems Letters 12, no. 4 (2020): 113–16. http://dx.doi.org/10.1109/les.2020.2966791.

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K., V. B. V. Rayudu, Jahagirdar, and Srihari Rao P. "Modern design approach of faults (toggling faults,bridge faults and SAT) of reduced ordered binary decision diagram based on combo & sequential blocks." International Journal of Reconfigurable and Embedded Systems 9, no. 2 (2020): 158–68. https://doi.org/10.11591/ijres.v9.i2.pp158-168.

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In this Research we are going to develop ROBDD (Reduced Ordered Binary Decision Diagram) designs to detect toggling faults, bridge faults and SAT (Stuck at Fault), Here we are going to develop sequential blocks using ROBDD and applying to the mux to detect stuck at faults and also connecting the combo & Sequential blocks to find the toggling faults by connecting or using automatic test pattern generator. In this research we are going to develop the bridges between the blocks of ROBDD designs and converting them to and or logic to find the bridge faults of the design. Finding bridge and toggle faults are more difficult in logic designs, here we use an advance technique to find the faults of the design by calculating the path delays of the individual blocks of the design. More concentrating on the path delays by using basic stuck at faults methods to refer the faults (toggling and bridge faults) at mux output. In our research the basic design modules are ROBDD circuit of both combinational and sequential blocks are designed and tested using Multiplexer and K-map Simplification Methods. The main purpose of the research to find the faults at all levels of all logic designs which involves in both combinational and sequential blocks of the design.

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Kubica, Marcin, and Dariusz Kania. "Area–Oriented Technology Mapping for LUT–Based Logic Blocks." International Journal of Applied Mathematics and Computer Science 27, no. 1 (2017): 207–22. http://dx.doi.org/10.1515/amcs-2017-0015.

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Abstract One of the main aspects of logic synthesis dedicated to FPGA is the problem of technology mapping, which is directly associated with the logic decomposition technique. This paper focuses on using configurable properties of CLBs in the process of logic decomposition and technology mapping. A novel theory and a set of efficient techniques for logic decomposition based on a BDD are proposed. The paper shows that logic optimization can be efficiently carried out by using multiple decomposition. The essence of the proposed synthesis method is multiple cutting of a BDD. A new diagram form called an SMTBDD is proposed. Moreover, techniques that allow finding the best technology mapping oriented to configurability of CLBs are presented. In the experimental section, the presented method (MultiDec) is compared with academic and commercial tools. The experimental results show that the proposed technology mapping strategy leads to good results in terms of the number of CLBs.

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Rajesh, A., Basha SK Jameer, Xavier Francis, and Babu S. Hari. "A BIST Methodology to test CLB Resources on an SRAM-Based FPGA using Complementary Gates Configuration." International Journal of Innovative Technology and Exploring Engineering (IJITEE) 9, no. 12 (2020): 217–20. https://doi.org/10.35940/ijitee.L7985.1091220.

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This paper primarily focuses on designing a new Built in self test (BIST) methodology to test the configurable logic blocks (CLBs) which is the heart of field programmable gate array (FPGA). The proposed methodology targets stuck-at-0/1 faults on a RAM cell in an LUT which constitutes about 90% of the total faults in the CLBs. No extra area overhead is needed to accommodate the test pattern generators (TPGs) and output responses analyzers (ORAs) as they are realized by the already existing configurable resources on the FPGA.A group of CLBs chosen as block under test (BUT) are configured as complementary gates (AND/NAND, OR/NOR, XOR/XNOR) to successfully test the aforementioned faults. The proposed BIST structure when implemented on Xilinx Virtex-4 FPGA proved 100% fault coverage and minimized test configurations.

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Moškon, Miha, Žiga Pušnik, Nikolaj Zimic, and Miha Mraz. "Field-programmable biological circuits and configurable (bio)logic blocks for distributed biological computing." Computers in Biology and Medicine 128 (January 2021): 104109. http://dx.doi.org/10.1016/j.compbiomed.2020.104109.

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Zia, Razia, Muzaffar Rao, Arshad Aziz, and Pervez Akhtar. "Efficient Utilization of FPGA Using LUT-6 Architecture." Applied Mechanics and Materials 241-244 (December 2012): 2548–54. http://dx.doi.org/10.4028/www.scientific.net/amm.241-244.2548.

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Field Programmable gate array (FPGA) technology is continuously gaining market share and becoming essential part of the today’s modern embedded systems. The most common FPGA architecture consists of an array of logic blocks called Configurable Logic Block (CLB), I/O pads, and routing channels. In general, a logic block (CLB) consists of logical cells called Slices and other dedicated resources. A typical cell consists of LUTs (Look up table). In modern FPGAs, there are 6-input LUTs instead of 4-input LUTs. In this paper we present the use of 6-input LUT architecture for some Boolean functions (Mux8, Mux16, Mux32, Mux64, SOP64, OR40 and AND40).we show our results in terms of LUTs and Slices and these results are much better as compare to previously reported results that based on 4-input LUTs.

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Dissertations / Theses on the topic "Configurable logic blocks"

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Erxleben, Fredo. "Graphical Support for the Design and Evaluation of Configurable Logic Blocks." Thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2016. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-175486.

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Developing a tool supporting humans to design and evaluate CLB-based circuits requires a lot of know-how and research from different fields of computer science. In this work, the newly developed application q2d, especially its design and implementation will be introduced as a possible tool for approaching CLB circuit development with graphical UI support. Design decisions and implementation will be discussed and a workflow example will be given.

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Modi, Harmish Rajeshkumar. "In-System Testing of Configurable Logic Blocks in Xilinx 7-Series FPGAs." Thesis, Virginia Tech, 2015. http://hdl.handle.net/10919/55123.

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FPGA fault recovery techniques, such as bitstream scrubbing, are only limited to detecting and correcting soft errors that corrupt the configuration memory. Scrubbing and related techniques cannot detect permanent faults within the FPGA fabric, such as short circuits and open circuits in FPGA transistors that arise from electromigration effects. Several Built-In Self-Test (BIST) techniques have been proposed in the past to detect and isolate such faults. These techniques suffer from routing congestion problems in modern FPGAs that have a large number of logic blocks. This thesis presents an improved BIST architecture for all Xilinx 7-Series FPGAs that is scalable to large arrays. The two primary sources of overhead associated with FPGA BIST, the test time and the memory required for storing the BIST configurations, are also reduced when compared to previous FPGA-BIST approaches. The BIST techniques presented here also eliminate the need for using any of the user I/O pins, such as a clock, a reset, and test observation pins; therefore, it is suitable for immediate deployment on any system with Xilinx 7-Series FPGAs. With faults detected, isolated, and corrected, the effective MTBF of a system can be extended.<br>Master of Science

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Al-aqeeli, Abulqadir. "Reconfigurable wavelet-based architecture for pattern recognition applications using a field programmable gate array." Ohio University / OhioLINK, 1998. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1177008904.

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Balijepalli, Heman. "Design, Implementation, and Test of Novel Quantum-dot Cellular Automata FPGAs for the beyond CMOS Era." University of Toledo / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1333730938.

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Liang, Fang-jia, and 梁芳嘉. "Design and implementation of Configurable Self-timed Logic Blocks." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/40469447266170277626.

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碩士<br>大同大學<br>資訊工程研究所<br>91<br>System-on-a-chip (SOC) design with IP (Intellectual Property) reuse becomes a key factor of IA design, and enables system or chip designer to increase the performance of the chip and decrease the time to market. A CAD tool, called SOCAD, for SOC design and Hardware/Software co-design based on self-timed technology is proposed. SOCAD provides the specification tool with Java programming language to describe system behaviors, translation tools to compile the Java programs into graph-based specifications represented by UML activity diagrams and to translate the graph-based specifications into VHDL codes automatically. FPGAs, it is simpler and faster than ASICs be used to verify Hardware design. However, all current commercial FPGAs don’t have self-timed FPGA system. All of them design the systems with synchronous, because asynchronous systems is very complexity and difficult to design. This thesis will present the Configurable Self-timed Logic Block (CSLB) architecture of FPGA, implementation the self-timed Cells of SOCAD and SOCAD design.

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Ghani, A., Chan H. See, Hassan S. O. Migdadi, Rameez Asif, Raed A. Abd-Alhameed, and James M. Noras. "Reconfigurable neurons - making the most of configurable logic blocks (CLBs)." 2015. http://hdl.handle.net/10454/9152.

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No<br>An area-efficient hardware architecture is used to map fully parallel cortical columns on Field Programmable Gate Arrays (FPGA) is presented in this paper. To demonstrate the concept of this work, the proposed architecture is shown at the system level and benchmarked with image and speech recognition applications. Due to the spatio-temporal nature of spiking neurons, this has allowed such architectures to map on FPGAs in which communication can be performed through the use of spikes and signal can be represented in binary form. The process and viability of designing and implementing the multiple recurrent neural reservoirs with a novel multiplier-less reconfigurable architectures is described.

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Erxleben, Fredo. "Graphical Support for the Design and Evaluation of Configurable Logic Blocks." Thesis, 2015. https://tud.qucosa.de/id/qucosa%3A28833.

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Developing a tool supporting humans to design and evaluate CLB-based circuits requires a lot of know-how and research from different fields of computer science. In this work, the newly developed application q2d, especially its design and implementation will be introduced as a possible tool for approaching CLB circuit development with graphical UI support. Design decisions and implementation will be discussed and a workflow example will be given.:1 Introduction 1.1 Forethoughts 1.2 Theoretical Background 1.2.1 Definitions 1.2.2 Expressing Connections between Circuit Elements 1.2.3 Global Context and Target Function 1.2.4 Problem formulation as QBF and SAT 2 Description of the Implemented Tool 2.1 Design Decisions 2.1.1 Choice of Language, Libraries and Frameworks 2.1.2 Solving the QBF Problem 2.1.3 Design of the Internally Used Meta-Model 2.1.4 User Interface Ergonomics 2.1.5 Aspects of Schematic Visualization 2.1.6 Limitations 2.2 Implemented Features 2.2.1 Basic Interaction 2.2.2 User-Defined Components 2.2.3 Generation of Circuit Symbols 2.2.4 Methods for Specifying Functional Behaviour 3 Implementation Details 3.1 Classes Involved in the Component Meta-Model 3.2 The Document Entry Class and its Factory 3.3 Model and View 3.3.1 The Model Element Hierarchy 3.3.2 The Schematics Element Hierarchy 3.4 The Quantor Interface 4 An Example Workflow 4.1 The Task 4.2 A Component Descriptor for Xilinx’ LUT6-2 4.3 Designing the Model 4.4 Computing the Desired Configuration 5 Summary and Outlook 5.1 Achieved Results 5.2 Suggested Improvements References A Acronyms and Glossary B UML Diagrams

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Li, Mei-Chen, and 李梅禎. "Standard Cell Like Via-Configurable Logic Block Design for Structured ASICs." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/24568116981195847583.

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碩士<br>元智大學<br>資訊工程學系<br>95<br>The popular IC design styles, standard cell design and FPGA, are facing a big challenge: attaining a proper balance between mask cost and performance. Structured ASIC retains some properties of standard cell designs such as higher performance and smaller area and also possesses some properties of FPGA such as low non-recurring engineering cost and re-configurability. It emerges as a good solution to the above challenge. A structured ASIC consists of some prefabricated transistors, prefabricated masks for some metal layers, and a couple of un-customized masks for vias (sometimes metal layers). A base block for structured ASICs must provide powerful functional expression, high integration density, and flexibility to meet various application requirements. Moreover, it should also minimize the efforts of developing tools for chip designs. In this thesis, we propose a standard cell like VCLB that can leverage existing standard cell design tools to perform chip designs using our VCLBs. We create a standard cell library based on our VCLB and perform chip designs using this cell library. Experimental results show that the designs using the cells in our library achieve a delay of 1.34 times that attained by the designs using a commercial standard cell library at the expense of 278% increase in chip area.

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Liu, Hsin-Hung, and 劉信宏. "SRAM Compiler for Structured ASIC with Via Configurable Logic Block and Routing Fabric." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/28398344293157622867.

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碩士<br>元智大學<br>資訊工程學系<br>99<br>With the advances in integrated circuit(IC) process, IC design issues that need to be handled will be more difficult. Since a chip consists of numerous pattern formational layers, mask cost becomes very large for an advanced manufacturing process. To reduce the cost of IC design and manufacturing, structured ASIC emerges as a new design alternative. A structured ASIC consists of some prefabricated transistors, prefabricated masks for some metal layers, and a couple of un-customized masks for vias (sometimes metal layers). A base block for structured ASICs must provide powerful functional expression, high integration density, and flexibility to meet various application requirements. Memory IP is an important component for structured ASIC. One of the most widely used is the static random access memory (SRAM). In this thesis, we propose a via-configurable logic block (VCLB) which can be use to implemented all the elements of memory IP. We also develop a SRAM compiler to automatically generate SRAM with our VCLB and routing fabric.

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Book chapters on the topic "Configurable logic blocks"

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Baradaran, Nastaran, Joonseok Park, and Pedro C. Diniz. "Data Reuse in Configurable Architectures with RAM Blocks." In Field Programmable Logic and Application. Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30117-2_141.

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Kubica, Marcin, Adam Opara, and Dariusz Kania. "Ability of the Configuration of Configurable Logic Blocks." In Lecture Notes in Electrical Engineering. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-60488-2_10.

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Leong, Chee Hock, T. Nandha Kumar, and Haider A. F. Almurib. "Nonvolatile configurable logic block for FPGAs." In Low Power Designs in Nanodevices and Circuits for Emerging Applications. CRC Press, 2023. http://dx.doi.org/10.1201/9781003459231-10.

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Jayalakshmi, R., and M. Senthil Kumaran. "Modeling of Potentially Implementable Configurable Logic Block in Quantum Dot Cellular Automata for Nanoelectronic Device Architecture." In Springer Proceedings in Materials. Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-6267-9_69.

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Kularatna, Nihal. "Configurable Logic Blocks for Digital Systems Design." In Electronic Circuit Design. CRC Press, 2017. http://dx.doi.org/10.1201/9781420007909-6.

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Biglari-Abhari, Morteza. "Configurable Logic Blocks for Digital Systems Design." In Electronic Circuit Design. CRC Press, 2008. http://dx.doi.org/10.1201/9781420007909.ch6.

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Capmany, José, and Daniel Pérez. "Field Programmable Photonic Gate Arrays." In Programmable Integrated Photonics. Oxford University Press, 2020. http://dx.doi.org/10.1093/oso/9780198844402.003.0009.

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The field programmable photonic gate array (FPPGA) is an integrated photonic device/subsystem that operates similarly to a field programmable gate array in electronics. It is a set of programmable photonics analogue blocks (PPABs) and of reconfigurable photonic interconnects (RPIs) implemented over a photonic chip. The PPABs provide the building blocks for implementing basic optical analogue operations (reconfigurable/independent power splitting and phase shifting). Broadly they enable reconfigurable processing just like configurable logic elements (CLE) or programmable logic blocks (PLBs) carry digital operations in electronic FPGAs or configurable analogue blocks (CABs) carry analogue operations in electronic field programmable analogue arrays (FPAAs). Reconfigurable interconnections between PPABs are provided by the RPIs. This chapter presents basic principles of integrated FPPGAs. It describes their main building blocks and discusses alternatives for their high-level layouts, design flow, technology mapping and physical implementation. Finally, it shows that waveguide meshes lead naturally to a compact solution.

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Chandarana, Peyton, Mohammed Elbtity, Ronald F. DeMara, and Ramtin Zand. "MRAM-Based FPGAs: A Survey." In Computer Memory and Data Storage [Working Title]. IntechOpen, 2022. http://dx.doi.org/10.5772/intechopen.108212.

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Over the last decade, field programmable gate arrays (FPGAs) have embraced heterogeneity in a transformative way by leveraging emerging memory devices along with conventional CMOS-based devices to realize technology-specific benefits. Memristive device technologies exhibit desirable characteristics such as non-volatility, scalability, near-zero leakage, radiation hardness, and more, making them promising alternatives for SRAM cells found in conventional SRAM-based FPGAs. In recent years, a significant amount of research has been performed to take advantage of these emerging technologies to develop fundamental building blocks of FPGAs like hybrid CMOS-memristive look-up tables (LUTs) and configurable logic blocks (CLBs). In this chapter, we will provide a brief overview of the previous work on hybrid CMOS-memristive FPGAs and their corresponding opportunities and challenges.

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Hauptfeld, Leonhard, Andrea Rappelsberger, and Klaus-Peter Adlassnig. "Infection Control Through Clinical Pipelines Built with Arden Syntax MLM Building Blocks." In dHealth 2024. IOS Press, 2024. http://dx.doi.org/10.3233/shti240032.

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Healthcare-associated infections (HAIs) may have grave consequences for patients. In the case of sepsis, the 30-day mortality rate is about 25%. HAIs cost EU member states an estimated 7 billion Euros annually. Clinical decision support tools may be useful for infection monitoring, early warning, and alerts. MONI, a tool for monitoring nosocomial infections, is used at University Hospital Vienna, but needs to be clinically and technically revised and updated. A new, completely configurable pipeline-based system for defining and processing HAI definitions was developed and validated. A network of data access points, clinical rules, and explanatory output is arranged as an inference network, a clinical pipeline as it is called, and processed in a stepwise manner. Arden-Syntax-based medical logic modules were used to implement the respective rules. The system was validated by creating a pipeline for the ECDC PN5 pneumonia rule. It was tested on a set of patient data from intensive care medicine. The results were compared with previously obtained MONI output as a suitable reference, yielding a sensitivity of 93.8% and a specificity of 99.8%. Clinical pipelines show promise as an open and configurable approach to graphically-based, human-readable, machine-executable HAI definitions.

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Zhang Lin, Slaets Peter, and Bruyninckx Herman. "An FPGA Based Architecture for Concurrent System Design Applied to Human-robot Interaction Applications." In Advances in Transdisciplinary Engineering. IOS Press, 2014. https://doi.org/10.3233/978-1-61499-440-4-555.

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This paper presents a hardware and software architecture for vision-based human-robot interaction designed for field programmable gate array (FPGA) based embedded system. The configurable logic and memory blocks connected through programmable interconnects on the FPGA permit programmers to create complex systems running multiple processing cores in parallel, which motivated the authors to implement vision algorithms and robot controllers on a single system-on-chip (SoC) board, aiming at low cost, low power consumption and high performance in human-robot interaction for industrial and educational robots. The architecture is a product derived from a component based programming model together with a systematic methodology for concurrent system design proposed by the authors.

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Conference papers on the topic "Configurable logic blocks"

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Ghani, Arfan, Chan H. See, Hassan Migdadi, Rameez Asif, Raed A. A. Abd-Alhameed, and James M. Noras. "Reconfigurable neurons - making the most of configurable logic blocks (CLBs)." In 2015 Internet Technologies and Applications (ITA). IEEE, 2015. http://dx.doi.org/10.1109/itecha.2015.7317451.

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Cota, Érika, Luigi Carro, Felipe Pinto, Ricardo Reis, and Marcelo Lubaszewski. "Resource-and-time-aware test strategy for configurable quaternary logic blocks." In the 22nd Annual Symposium. ACM Press, 2009. http://dx.doi.org/10.1145/1601896.1601922.

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Dutton, Bradley F., and Charles E. Stroud. "Built-In Self-Test of configurable logic blocks in Virtex-5 FPGAs." In 2009 41st Southeastern Symposium on System Theory (SSST). IEEE, 2009. http://dx.doi.org/10.1109/ssst.2009.4806778.

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Fu, Wen-Hui, Jun Jiang, Xi Qin, Ting Yi, and Zhi-Liang Hong. "A Reconfigurable Analog Processor Based on FPAA with Coarse-Grained, Heterogeneous Configurable Analog Blocks." In 2010 International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2010. http://dx.doi.org/10.1109/fpl.2010.50.

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Lahrach, Farid, Abderrazek Abdaoui, Abderrahim Doumar, and Eric Chatelet. "A novel SRAM-based FPGA architecture for defect and fault tolerance of configurable logic blocks." In 2010 IEEE 13th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE, 2010. http://dx.doi.org/10.1109/ddecs.2010.5491763.

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Lakys, Yahya, Weisheng Zhao, Jacques-Olivier Klein, and Claude Chappert. "MRAM crossbar based configurable logic block." In 2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012. IEEE, 2012. http://dx.doi.org/10.1109/iscas.2012.6271934.

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Pandey, Neeta, Maneesha Gupta, and Kirti Gupta. "A PFSCL based configurable logic block." In 2015 Annual IEEE India Conference (INDICON). IEEE, 2015. http://dx.doi.org/10.1109/indicon.2015.7443260.

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Mane, Pravin S., Namita Paul, Nikhilesh Behera, Madankumar Sampath, and C. K. Ramesha. "Hybrid CMOS - Memristor based configurable logic block design." In 2014 International Conference on Electronics and Communication Systems (ICECS). IEEE, 2014. http://dx.doi.org/10.1109/ecs.2014.6892532.

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Basha, B. Chagun, Sebastien Pillement, and Stanislaw J. Piestrak. "Fault-aware configurable logic block for reliable reconfigurable FPGAs." In 2015 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2015. http://dx.doi.org/10.1109/iscas.2015.7169251.

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Gaillardon, Pierre-Emmanuel, Xifan Tang, and Giovanni De Micheli. "Novel configurable logic block architecture exploiting controllable-polarity transistors." In 2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC). IEEE, 2014. http://dx.doi.org/10.1109/recosoc.2014.6861338.

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