Relevant bibliographies by topics / Configurable Logic Blocks (CLB)

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Configurable Logic Blocks (CLB)'

Author: Grafiati
Published: 2 June 2025
Last updated: 19 July 2025

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Journal articles on the topic "Configurable Logic Blocks (CLB)"

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Zhang, Jun Bin, Jin Yan Cai, and Dan Yang Li. "A Novel Fault Orientation Technique of FPGA Configurable Logic Blocks Based on Improved Shift Register." Applied Mechanics and Materials 347-350 (August 2013): 1602–6. http://dx.doi.org/10.4028/www.scientific.net/amm.347-350.1602.

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With the development of digital integrate circuit system which is based on Field Programmable Gate Arrays (FPGA), the request on FPGA test technique is becoming higher and higher. The Boundary Scan Technique and Built-In Self-Test (BIST) technique appear in succession, however, these techniques dont implement Configurable Logic Block (CLB) fault diagnose and fault orientation. Arrays-based technique was advanced, which also have some problems about masking of faults and too many reconfiguration times. According to these problems, A Novel Shift Register-based technique for Fault Orientation of
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Zia, Razia, Muzaffar Rao, Arshad Aziz, and Pervez Akhtar. "Efficient Utilization of FPGA Using LUT-6 Architecture." Applied Mechanics and Materials 241-244 (December 2012): 2548–54. http://dx.doi.org/10.4028/www.scientific.net/amm.241-244.2548.

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Field Programmable gate array (FPGA) technology is continuously gaining market share and becoming essential part of the today’s modern embedded systems. The most common FPGA architecture consists of an array of logic blocks called Configurable Logic Block (CLB), I/O pads, and routing channels. In general, a logic block (CLB) consists of logical cells called Slices and other dedicated resources. A typical cell consists of LUTs (Look up table). In modern FPGAs, there are 6-input LUTs instead of 4-input LUTs. In this paper we present the use of 6-input LUT architecture for some Boolean functions
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GHOSH, BAHNIMAN, J. SIVA CHANDRA, and AKSHAYKUMAR SALIMATH. "DESIGN OF A MULTI-LAYERED QCA CONFIGURABLE LOGIC BLOCK FOR FPGAs." Journal of Circuits, Systems and Computers 23, no. 06 (2014): 1450089. http://dx.doi.org/10.1142/s0218126614500893.

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In this paper, a Multi-layered configurable logic block (CLB) unit for field programmable gate arrays (FPGAs) is proposed based on quantum-dot cellular automata (QCA) technology. The design is made in multiple layers which help to process information simultaneously, in different layers. Various components of CLB like (4 × 16) Decoder, Memory units, Multiplexers and RS-Flip flops are all designed in multiple layers using higher input majority gates to reduce the cell count and latency compared to previous designs. QCA Designer tool is used to design and simulate the model. The Coherence vector
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Rajesh, A., Basha SK Jameer, Xavier Francis, and Babu S. Hari. "A BIST Methodology to test CLB Resources on an SRAM-Based FPGA using Complementary Gates Configuration." International Journal of Innovative Technology and Exploring Engineering (IJITEE) 9, no. 12 (2020): 217–20. https://doi.org/10.35940/ijitee.L7985.1091220.

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This paper primarily focuses on designing a new Built in self test (BIST) methodology to test the configurable logic blocks (CLBs) which is the heart of field programmable gate array (FPGA). The proposed methodology targets stuck-at-0/1 faults on a RAM cell in an LUT which constitutes about 90% of the total faults in the CLBs. No extra area overhead is needed to accommodate the test pattern generators (TPGs) and output responses analyzers (ORAs) as they are realized by the already existing configurable resources on the FPGA.A group of CLBs chosen as block under test (BUT) are configured as com
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Kim, Kyungah, Duc M. Tran, and Joon-Young Choi. "Implementation of EnDat Interface Master Using Configurable Logic Block in MCU." Electronics 13, no. 6 (2024): 1101. http://dx.doi.org/10.3390/electronics13061101.

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In this study, we propose an implementation method of the Encoder Data (EnDat) interface master for slave encoders using only a configurable logic block (CLB) and a serial peripheral interface (SPI) integrated into microcontroller units. By programming the CLB device to execute logic functions and finite state machines designed for the EnDat interface master operation, we realize the EnDat and SPI clocks that are required for the EnDat interface master operation. This approach is cost-efficient because additional hardware components, such as a field-programmable gate array or a complex program
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Wang, Guo Hua, and Jing Lin Sun. "BIST-Based Method for Diagnosing Multiple Faulty CLBs in FPGAs." Applied Mechanics and Materials 643 (September 2014): 243–48. http://dx.doi.org/10.4028/www.scientific.net/amm.643.243.

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This paper presents a new built-in self-test (BIST) method to realize the fault detection and the fault diagnosis of configurable logic blocks (CLBs) in FPGAs. The proposed BIST adopts a circular comparison structure to overcome the phenomenon of fault masking in diagnosing multiple faulty CLBs and improve the diagnostic resolution. To test the memory block in every CLB, different TPG structures are proposed to obtain maximum stuck-at fault coverage. For the LUT mode of the memory block, the TPG based on the LFSR is designed to provide Pseudo-exhaustive testing patterns, and for the distribute
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Liu, Hanyu, and Ali Akoglu. "Timing-Driven Nonuniform Depopulation-Based Clustering." International Journal of Reconfigurable Computing 2010 (2010): 1–11. http://dx.doi.org/10.1155/2010/158602.

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Low-cost FPGAs have comparable number of Configurable Logic Blocks (CLBs) with respect to resource-rich FPGAs but have much less routing tracks. For CAD tools, this situation increases the difficulty of successfully mapping a circuit into the low-cost FPGAs. Instead of switching to resource-rich FPGAs, the designers could employ depopulation-based clustering techniques which underuse CLBs, hence improve routability by spreading the logic over the architecture. However, all depopulation-based clustering algorithms to this date increase critical path delay. In this paper, we present a timing-dri
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M., Siva Kumar, Sanjeeva Rayudu T.C., Rafi Vempalle, and Rajesh M. "A HW/SW Co-Verification Method for ASK using FPGA Test." Journal of VLSI Design and its Advancement 6, no. 2 (2023): 41–50. https://doi.org/10.5281/zenodo.8313916.

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<em>Field programmable gate arrays (FPGAs) may be used in a wide variety of settings. If weak points in an FPGA can be isolated, then the device&#39;s shortcomings may be endured with relative ease. The research provides a recommendation and unveils a hardware/software co-verification approach for testing FPGAs. Using the adaptability and visibility of software in combination with large-speed simulation of the hardware, this process can do comprehensive, automated testing of every input/output block (IOB) and custom configurable logic block (CLB) of an FPGA. The proposed technique may detect f
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Yang, Wu, Milad Tanavardi Nasab, and Himanshu Thapliyal. "Energy Efficient CLB Design Based on Adiabatic Logic for IoT Applications." Electronics 13, no. 7 (2024): 1309. http://dx.doi.org/10.3390/electronics13071309.

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Many IoT applications require high computational performance and flexibility, and FPGA is a promising candidate. However, increased computation power results in higher energy dissipation, and energy efficiency is one of the key concerns for IoT applications. In this paper, we explore adiabatic logic for designing an energy efficient configurable logic block (CLB) and compare it to the CMOS counterpart. The simulation results show that the proposed adiabatic-logic-based look-up table (LUT) has significant energy savings for the frequency range of 1 MHz to 40 MHz, and the least energy savings is
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Ran, Y., and M. Marek-Sadowska. "Designing via-configurable logic blocks for regular fabric." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14, no. 1 (2006): 1–14. http://dx.doi.org/10.1109/tvlsi.2005.863196.

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Dissertations / Theses on the topic "Configurable Logic Blocks (CLB)"

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Erxleben, Fredo. "Graphical Support for the Design and Evaluation of Configurable Logic Blocks." Thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2016. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-175486.

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Developing a tool supporting humans to design and evaluate CLB-based circuits requires a lot of know-how and research from different fields of computer science. In this work, the newly developed application q2d, especially its design and implementation will be introduced as a possible tool for approaching CLB circuit development with graphical UI support. Design decisions and implementation will be discussed and a workflow example will be given.
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Modi, Harmish Rajeshkumar. "In-System Testing of Configurable Logic Blocks in Xilinx 7-Series FPGAs." Thesis, Virginia Tech, 2015. http://hdl.handle.net/10919/55123.

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FPGA fault recovery techniques, such as bitstream scrubbing, are only limited to detecting and correcting soft errors that corrupt the configuration memory. Scrubbing and related techniques cannot detect permanent faults within the FPGA fabric, such as short circuits and open circuits in FPGA transistors that arise from electromigration effects. Several Built-In Self-Test (BIST) techniques have been proposed in the past to detect and isolate such faults. These techniques suffer from routing congestion problems in modern FPGAs that have a large number of logic blocks. This thesis presents an im
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Erxleben, Fredo. "Graphical Support for the Design and Evaluation of Configurable Logic Blocks." Thesis, 2015. https://tud.qucosa.de/id/qucosa%3A28833.

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Developing a tool supporting humans to design and evaluate CLB-based circuits requires a lot of know-how and research from different fields of computer science. In this work, the newly developed application q2d, especially its design and implementation will be introduced as a possible tool for approaching CLB circuit development with graphical UI support. Design decisions and implementation will be discussed and a workflow example will be given.:1 Introduction 1.1 Forethoughts 1.2 Theoretical Background 1.2.1 Definitions 1.2.2 Expressing Connections between Circuit Elements 1.2.3 Global Contex
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Ghani, A., Chan H. See, Hassan S. O. Migdadi, Rameez Asif, Raed A. Abd-Alhameed, and James M. Noras. "Reconfigurable neurons - making the most of configurable logic blocks (CLBs)." 2015. http://hdl.handle.net/10454/9152.

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No<br>An area-efficient hardware architecture is used to map fully parallel cortical columns on Field Programmable Gate Arrays (FPGA) is presented in this paper. To demonstrate the concept of this work, the proposed architecture is shown at the system level and benchmarked with image and speech recognition applications. Due to the spatio-temporal nature of spiking neurons, this has allowed such architectures to map on FPGAs in which communication can be performed through the use of spikes and signal can be represented in binary form. The process and viability of designing and implementing the
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Liang, Fang-jia, and 梁芳嘉. "Design and implementation of Configurable Self-timed Logic Blocks." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/40469447266170277626.

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碩士<br>大同大學<br>資訊工程研究所<br>91<br>System-on-a-chip (SOC) design with IP (Intellectual Property) reuse becomes a key factor of IA design, and enables system or chip designer to increase the performance of the chip and decrease the time to market. A CAD tool, called SOCAD, for SOC design and Hardware/Software co-design based on self-timed technology is proposed. SOCAD provides the specification tool with Java programming language to describe system behaviors, translation tools to compile the Java programs into graph-based specifications represented by UML activity diagrams and to transla
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Book chapters on the topic "Configurable Logic Blocks (CLB)"

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Baradaran, Nastaran, Joonseok Park, and Pedro C. Diniz. "Data Reuse in Configurable Architectures with RAM Blocks." In Field Programmable Logic and Application. Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30117-2_141.

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Kubica, Marcin, Adam Opara, and Dariusz Kania. "Ability of the Configuration of Configurable Logic Blocks." In Lecture Notes in Electrical Engineering. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-60488-2_10.

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Capmany, José, and Daniel Pérez. "Field Programmable Photonic Gate Arrays." In Programmable Integrated Photonics. Oxford University Press, 2020. http://dx.doi.org/10.1093/oso/9780198844402.003.0009.

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The field programmable photonic gate array (FPPGA) is an integrated photonic device/subsystem that operates similarly to a field programmable gate array in electronics. It is a set of programmable photonics analogue blocks (PPABs) and of reconfigurable photonic interconnects (RPIs) implemented over a photonic chip. The PPABs provide the building blocks for implementing basic optical analogue operations (reconfigurable/independent power splitting and phase shifting). Broadly they enable reconfigurable processing just like configurable logic elements (CLE) or programmable logic blocks (PLBs) carry digital operations in electronic FPGAs or configurable analogue blocks (CABs) carry analogue operations in electronic field programmable analogue arrays (FPAAs). Reconfigurable interconnections between PPABs are provided by the RPIs. This chapter presents basic principles of integrated FPPGAs. It describes their main building blocks and discusses alternatives for their high-level layouts, design flow, technology mapping and physical implementation. Finally, it shows that waveguide meshes lead naturally to a compact solution.
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Chandarana, Peyton, Mohammed Elbtity, Ronald F. DeMara, and Ramtin Zand. "MRAM-Based FPGAs: A Survey." In Computer Memory and Data Storage [Working Title]. IntechOpen, 2022. http://dx.doi.org/10.5772/intechopen.108212.

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Over the last decade, field programmable gate arrays (FPGAs) have embraced heterogeneity in a transformative way by leveraging emerging memory devices along with conventional CMOS-based devices to realize technology-specific benefits. Memristive device technologies exhibit desirable characteristics such as non-volatility, scalability, near-zero leakage, radiation hardness, and more, making them promising alternatives for SRAM cells found in conventional SRAM-based FPGAs. In recent years, a significant amount of research has been performed to take advantage of these emerging technologies to develop fundamental building blocks of FPGAs like hybrid CMOS-memristive look-up tables (LUTs) and configurable logic blocks (CLBs). In this chapter, we will provide a brief overview of the previous work on hybrid CMOS-memristive FPGAs and their corresponding opportunities and challenges.
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Kularatna, Nihal. "Configurable Logic Blocks for Digital Systems Design." In Electronic Circuit Design. CRC Press, 2017. http://dx.doi.org/10.1201/9781420007909-6.

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Biglari-Abhari, Morteza. "Configurable Logic Blocks for Digital Systems Design." In Electronic Circuit Design. CRC Press, 2008. http://dx.doi.org/10.1201/9781420007909.ch6.

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Hauptfeld, Leonhard, Andrea Rappelsberger, and Klaus-Peter Adlassnig. "Infection Control Through Clinical Pipelines Built with Arden Syntax MLM Building Blocks." In dHealth 2024. IOS Press, 2024. http://dx.doi.org/10.3233/shti240032.

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Healthcare-associated infections (HAIs) may have grave consequences for patients. In the case of sepsis, the 30-day mortality rate is about 25%. HAIs cost EU member states an estimated 7 billion Euros annually. Clinical decision support tools may be useful for infection monitoring, early warning, and alerts. MONI, a tool for monitoring nosocomial infections, is used at University Hospital Vienna, but needs to be clinically and technically revised and updated. A new, completely configurable pipeline-based system for defining and processing HAI definitions was developed and validated. A network of data access points, clinical rules, and explanatory output is arranged as an inference network, a clinical pipeline as it is called, and processed in a stepwise manner. Arden-Syntax-based medical logic modules were used to implement the respective rules. The system was validated by creating a pipeline for the ECDC PN5 pneumonia rule. It was tested on a set of patient data from intensive care medicine. The results were compared with previously obtained MONI output as a suitable reference, yielding a sensitivity of 93.8% and a specificity of 99.8%. Clinical pipelines show promise as an open and configurable approach to graphically-based, human-readable, machine-executable HAI definitions.
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Zhang Lin, Slaets Peter, and Bruyninckx Herman. "An FPGA Based Architecture for Concurrent System Design Applied to Human-robot Interaction Applications." In Advances in Transdisciplinary Engineering. IOS Press, 2014. https://doi.org/10.3233/978-1-61499-440-4-555.

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This paper presents a hardware and software architecture for vision-based human-robot interaction designed for field programmable gate array (FPGA) based embedded system. The configurable logic and memory blocks connected through programmable interconnects on the FPGA permit programmers to create complex systems running multiple processing cores in parallel, which motivated the authors to implement vision algorithms and robot controllers on a single system-on-chip (SoC) board, aiming at low cost, low power consumption and high performance in human-robot interaction for industrial and educational robots. The architecture is a product derived from a component based programming model together with a systematic methodology for concurrent system design proposed by the authors.
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Véstias, Mário Pereira. "Field-Programmable Gate Array." In Encyclopedia of Information Science and Technology, Fifth Edition. IGI Global, 2021. http://dx.doi.org/10.4018/978-1-7998-3479-3.ch020.

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Field-programmable gate arrays (FPGAs) are integrated circuits whose logic and their interconnections are configurable. These devices are field-programmable, that is, they can be configured by the hardware designer without any intervention of the manufacturer. Most FPGAs can be reprogrammed as many times as we want with a vast variety of digital circuits. Some recent FPGA families are system-on-chips (SoC) with one or more microprocessor cores, memory, cache, and reconfigurable logic allowing the implementation of complex hardware/software systems in a single programmable device. This article focuses on the architecture of FPGAs, including the so called SoC FPGA. It explains the main blocks of the FPGA, how they have evolved along the last decades and the perspectives of next generation FPGAs. It also describes some applicability areas and how its architecture have evolved to adapt to some of these target markets.
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Conference papers on the topic "Configurable Logic Blocks (CLB)"

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Wu, Jun, Yong-Bin Kim, and Minsu Choi. "Configurable logic block (CLB) design for Asynchronous Nanowire Crossbar system." In 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2012. http://dx.doi.org/10.1109/mwscas.2012.6291984.

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Sunny, Abann, S. Aiswariya, A. J. Rose, Jerrin Joseph, Mangal Jolly, and Vinod Pangracious. "Design & implementation of configurable logic block (CLB) using SET based QCA technology." In 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology (ICSICT). IEEE, 2012. http://dx.doi.org/10.1109/icsict.2012.6467735.

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Sunny, Abann, S. Aiswariya, A. J. Rose, Jerrin Joseph, Mangal Jolly, and Vinod Pangracious. "Design & implementation of configurable logic block (CLB) using SET based QCA technology." In 2012 Annual IEEE India Conference (INDICON). IEEE, 2012. http://dx.doi.org/10.1109/indcon.2012.6420603.

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Ghani, Arfan, Chan H. See, Hassan Migdadi, Rameez Asif, Raed A. A. Abd-Alhameed, and James M. Noras. "Reconfigurable neurons - making the most of configurable logic blocks (CLBs)." In 2015 Internet Technologies and Applications (ITA). IEEE, 2015. http://dx.doi.org/10.1109/itecha.2015.7317451.

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Ramana Kumari, J. L. V., V. Kranthi Kumar, M. Abhignya, and P. Shiva Rama Krishna. "Design and Performance Analysis of Configurable Logic Block (CLB) for FPGA using Various Circuit Topologies." In 2024 3rd International Conference for Innovation in Technology (INOCON). IEEE, 2024. http://dx.doi.org/10.1109/inocon60754.2024.10511683.

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Cota, Érika, Luigi Carro, Felipe Pinto, Ricardo Reis, and Marcelo Lubaszewski. "Resource-and-time-aware test strategy for configurable quaternary logic blocks." In the 22nd Annual Symposium. ACM Press, 2009. http://dx.doi.org/10.1145/1601896.1601922.

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Dutton, Bradley F., and Charles E. Stroud. "Built-In Self-Test of configurable logic blocks in Virtex-5 FPGAs." In 2009 41st Southeastern Symposium on System Theory (SSST). IEEE, 2009. http://dx.doi.org/10.1109/ssst.2009.4806778.

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Fu, Wen-Hui, Jun Jiang, Xi Qin, Ting Yi, and Zhi-Liang Hong. "A Reconfigurable Analog Processor Based on FPAA with Coarse-Grained, Heterogeneous Configurable Analog Blocks." In 2010 International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2010. http://dx.doi.org/10.1109/fpl.2010.50.

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Lahrach, Farid, Abderrazek Abdaoui, Abderrahim Doumar, and Eric Chatelet. "A novel SRAM-based FPGA architecture for defect and fault tolerance of configurable logic blocks." In 2010 IEEE 13th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE, 2010. http://dx.doi.org/10.1109/ddecs.2010.5491763.

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