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Journal articles on the topic 'Configurable logic blocks'

Author: Grafiati

Published: 4 June 2025

Last updated: 1 August 2025

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1

Zhang, Jun Bin, Jin Yan Cai, and Dan Yang Li. "A Novel Fault Orientation Technique of FPGA Configurable Logic Blocks Based on Improved Shift Register." Applied Mechanics and Materials 347-350 (August 2013): 1602–6. http://dx.doi.org/10.4028/www.scientific.net/amm.347-350.1602.

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With the development of digital integrate circuit system which is based on Field Programmable Gate Arrays (FPGA), the request on FPGA test technique is becoming higher and higher. The Boundary Scan Technique and Built-In Self-Test (BIST) technique appear in succession, however, these techniques dont implement Configurable Logic Block (CLB) fault diagnose and fault orientation. Arrays-based technique was advanced, which also have some problems about masking of faults and too many reconfiguration times. According to these problems, A Novel Shift Register-based technique for Fault Orientation of

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2

Melnyk, Oleksandr, Viktoriia Kozarevych, and Mykola Butok. "Micro- and Nanocircuits with Configurable Logic." Electronics and Control Systems 3, no. 77 (2023): 47–52. http://dx.doi.org/10.18372/1990-5548.77.18003.

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The work considers controversial problems with the introduction of specialized and at the same time universal large integrated circuits, which are clarified at the initial stages of automated hierarchical design. Universal micro- and nanocircuits with configurable logic are created in the article to increase the efficiency of automated design systems. The article provides effective methods of programming multiplexer micro- and nanocircuits with configured logic for implementing Boolean and majority logic functions. The obtained results are used to configure the multiplexer functional blocks. W

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Ran, Y., and M. Marek-Sadowska. "Designing via-configurable logic blocks for regular fabric." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14, no. 1 (2006): 1–14. http://dx.doi.org/10.1109/tvlsi.2005.863196.

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Gan, Victor M., Yibin Liang, Lianjun Li, Lingjia Liu, and Yang Yi. "A Cost-Efficient Digital ESN Architecture on FPGA for OFDM Symbol Detection." ACM Journal on Emerging Technologies in Computing Systems 17, no. 4 (2021): 1–15. http://dx.doi.org/10.1145/3440017.

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The echo state network (ESN) is a recently developed machine-learning paradigm whose processing capabilities rely on the dynamical behavior of recurrent neural networks. Its performance outperforms traditional recurrent neural networks in nonlinear system identification and temporal information processing applications. We design and implement a cost-efficient ESN architecture on field-programmable gate array (FPGA) that explores the full capacity of digital signal processor blocks on low-cost and low-power FPGA hardware. Specifically, our scalable ESN architecture on FPGA exploits Xilinx DSP48

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Raj, Marshal, Lakshminarayanan Gopalakrishnan, Seok-Bum Ko, Nagi Naganathan, and N. Ramasubramanian. "Configurable Logic Blocks and Memory Blocks for Beyond-CMOS FPGA-Based Embedded Systems." IEEE Embedded Systems Letters 12, no. 4 (2020): 113–16. http://dx.doi.org/10.1109/les.2020.2966791.

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K., V. B. V. Rayudu, Jahagirdar, and Srihari Rao P. "Modern design approach of faults (toggling faults,bridge faults and SAT) of reduced ordered binary decision diagram based on combo & sequential blocks." International Journal of Reconfigurable and Embedded Systems 9, no. 2 (2020): 158–68. https://doi.org/10.11591/ijres.v9.i2.pp158-168.

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In this Research we are going to develop ROBDD (Reduced Ordered Binary Decision Diagram) designs to detect toggling faults, bridge faults and SAT (Stuck at Fault), Here we are going to develop sequential blocks using ROBDD and applying to the mux to detect stuck at faults and also connecting the combo & Sequential blocks to find the toggling faults by connecting or using automatic test pattern generator. In this research we are going to develop the bridges between the blocks of ROBDD designs and converting them to and or logic to find the bridge faults of the design. Finding bridge and tog

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Kubica, Marcin, and Dariusz Kania. "Area–Oriented Technology Mapping for LUT–Based Logic Blocks." International Journal of Applied Mathematics and Computer Science 27, no. 1 (2017): 207–22. http://dx.doi.org/10.1515/amcs-2017-0015.

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Abstract One of the main aspects of logic synthesis dedicated to FPGA is the problem of technology mapping, which is directly associated with the logic decomposition technique. This paper focuses on using configurable properties of CLBs in the process of logic decomposition and technology mapping. A novel theory and a set of efficient techniques for logic decomposition based on a BDD are proposed. The paper shows that logic optimization can be efficiently carried out by using multiple decomposition. The essence of the proposed synthesis method is multiple cutting of a BDD. A new diagram form c

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Rajesh, A., Basha SK Jameer, Xavier Francis, and Babu S. Hari. "A BIST Methodology to test CLB Resources on an SRAM-Based FPGA using Complementary Gates Configuration." International Journal of Innovative Technology and Exploring Engineering (IJITEE) 9, no. 12 (2020): 217–20. https://doi.org/10.35940/ijitee.L7985.1091220.

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This paper primarily focuses on designing a new Built in self test (BIST) methodology to test the configurable logic blocks (CLBs) which is the heart of field programmable gate array (FPGA). The proposed methodology targets stuck-at-0/1 faults on a RAM cell in an LUT which constitutes about 90% of the total faults in the CLBs. No extra area overhead is needed to accommodate the test pattern generators (TPGs) and output responses analyzers (ORAs) as they are realized by the already existing configurable resources on the FPGA.A group of CLBs chosen as block under test (BUT) are configured as com

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Moškon, Miha, Žiga Pušnik, Nikolaj Zimic, and Miha Mraz. "Field-programmable biological circuits and configurable (bio)logic blocks for distributed biological computing." Computers in Biology and Medicine 128 (January 2021): 104109. http://dx.doi.org/10.1016/j.compbiomed.2020.104109.

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10

Zia, Razia, Muzaffar Rao, Arshad Aziz, and Pervez Akhtar. "Efficient Utilization of FPGA Using LUT-6 Architecture." Applied Mechanics and Materials 241-244 (December 2012): 2548–54. http://dx.doi.org/10.4028/www.scientific.net/amm.241-244.2548.

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Field Programmable gate array (FPGA) technology is continuously gaining market share and becoming essential part of the today’s modern embedded systems. The most common FPGA architecture consists of an array of logic blocks called Configurable Logic Block (CLB), I/O pads, and routing channels. In general, a logic block (CLB) consists of logical cells called Slices and other dedicated resources. A typical cell consists of LUTs (Look up table). In modern FPGAs, there are 6-input LUTs instead of 4-input LUTs. In this paper we present the use of 6-input LUT architecture for some Boolean functions

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11

Pfänder, O. A., R. Nopper, H. J. Pfleiderer, S. Zhou, and A. Bermak. "Comparison of reconfigurable structures for flexible word-length multiplication." Advances in Radio Science 6 (May 26, 2008): 113–18. http://dx.doi.org/10.5194/ars-6-113-2008.

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Abstract. Binary multiplication continues to be one of the essential arithmetic operations in digital circuits. Even though field-programmable gate arrays (FPGAs) are becoming more and more powerful these days, the vendors cannot avoid implementing multiplications with high word-lengths using embedded blocks instead of configurable logic. But on the other hand, the circuit's efficiency decreases if the provided word-length of the hard-wired multipliers exceeds the precision requirements of the algorithm mapped into the FPGA. Thus it is beneficial to use multiplier blocks with configurable word

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Hong, Sheng, Wen Hui Tao, Yun Ping Qi, et al. "Built-in Self-Test Design for Fault Detection of MUXFXs in SRAM-Based FPGAs." Applied Mechanics and Materials 39 (November 2010): 220–25. http://dx.doi.org/10.4028/www.scientific.net/amm.39.220.

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This paper proposes a built-in self-test (BIST) design for MUXFXs in SRAM-based FPGAs. This approach can test both the interconnect resources and MUXFXs in the configurable logic blocks (CLBs). Because the test pattern generator (TPG) and output response analyzer (ORA)are configured by existing CLBs in FPGAs, no extra area overhead is needed for the proposed BIST structure. Open/short , stuck on/off faults in PSs, and stuck-at-0/1 faults in MUXFXs will be detected through the target fault detection/diagnosis of the proposed BIST structure.

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Barkalov, Alexander, Larysa Titarenko, Oleksandr Golovin, and Oleksandr Matvienko. "Optimization of a Mealy Automaton Circuit in a Mixed Element Basis." Cybernetics and Computer Technologies, no. 3 (September 29, 2023): 88–100. http://dx.doi.org/10.34229/2707-451x.23.3.8.

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Introduction. The control device is one of the most important blocks of any digital system. The main function of the control device is to coordinate the interaction of the remaining units of the system. Therefore, the characteristics of the control device circuit have a significant impact on the quality of the overall system. To represent the law of functioning of the control device, the models of the microprogrammed automaton (MPA) by Moore and Mealy are used. When synthesizing MPA circuits, it is necessary to solve a number of optimization problems: reducing hardware costs, increasing perfor

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14

Gowda V, Dankan, Sampada Abhijit Dhole, KDV Prasad, et al. "Optimizing Configurable Logic Blocks with Advanced Error-Resilient Circuits for Low-Power FPGA Systems." International Journal of Electrical and Electronics Research 13, no. 2 (2025): 227–36. https://doi.org/10.37391/ijeer.130206.

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This paper aims at enhancing configurable logic blocks (CLBs) in FPGA systems through incorporating more complex error-tolerant circuits and power control strategies. The architecture of the Presented FPGA considered in this study has been designed using MATLAB simulation and is tailored for low power consumption and high reliability. Power management is another feature implemented in the system through Dynamic Voltage Scaling (DVS) to improve electrical power usage essentially by 20%-25% at low load”. The fault tolerance is implemented through incorporating ECC and TMR into CLBs to render the

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15

Pfänder, O. A., H. J. Pfleiderer, and S. W. Lachowicz. "Configurable multiplier modules for an adaptive computing system." Advances in Radio Science 4 (September 6, 2006): 231–36. http://dx.doi.org/10.5194/ars-4-231-2006.

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Abstract. The importance of reconfigurable hardware is increasing steadily. For example, the primary approach of using adaptive systems based on programmable gate arrays and configurable routing resources has gone mainstream and high-performance programmable logic devices are rivaling traditional application-specific hardwired integrated circuits. Also, the idea of moving from the 2-D domain into a 3-D design which stacks several active layers above each other is gaining momentum in research and industry, to cope with the demand for smaller devices with a higher scale of integration. However,

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16

Magyari, Alexander, and Yuhua Chen. "Hardware Optimized Modular Reduction." Electronics 14, no. 3 (2025): 550. https://doi.org/10.3390/electronics14030550.

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We introduce a modular reduction method that is optimized for hardware and outperforms conventional approaches. By leveraging calculated reduction cycles and combinatorial logic, we achieve a remarkable 30% reduction in power usage, 27% reduction in Configurable Logic Blocks (CLBs), and 42% fewer look-up tables (LUTs) than the conventional implementation. Our Hardware-Optimized Modular Reduction (HOM-R) system can condense a 256-bit input to a four-bit base within a single 250 MHz clock cycle. Further, our method stands out from prevalent techniques, such as Barrett and Montgomery reduction, b

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17

Liu, Hanyu, and Ali Akoglu. "Timing-Driven Nonuniform Depopulation-Based Clustering." International Journal of Reconfigurable Computing 2010 (2010): 1–11. http://dx.doi.org/10.1155/2010/158602.

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Low-cost FPGAs have comparable number of Configurable Logic Blocks (CLBs) with respect to resource-rich FPGAs but have much less routing tracks. For CAD tools, this situation increases the difficulty of successfully mapping a circuit into the low-cost FPGAs. Instead of switching to resource-rich FPGAs, the designers could employ depopulation-based clustering techniques which underuse CLBs, hence improve routability by spreading the logic over the architecture. However, all depopulation-based clustering algorithms to this date increase critical path delay. In this paper, we present a timing-dri

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Tung, Hui-Hsiang, Rung-Bin Lin, Mei-Chen Li, and Tsung-Han Heish. "Standard Cell Like Via-Configurable Logic Blocks for Structured ASIC in an Industrial Design Flow." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20, no. 12 (2012): 2184–97. http://dx.doi.org/10.1109/tvlsi.2011.2170712.

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19

Craven, J. M., E. Meeks, G. Delich, E. Ayars, H. K. Pechkis, and J. A. Pechkis. "A low-cost shutter driver and arbitrary waveform generator for optical switching using a programmable system-on-chip (PSoC) device." Review of Scientific Instruments 93, no. 11 (2022): 113002. http://dx.doi.org/10.1063/5.0105884.

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We have developed a low-cost mechanical shutter driver with integrated arbitrary waveform generation for optical switching and control using a programmable system-on-chip device. This microcontroller-based device with configurable digital and analog blocks is readily programmed using free software, allowing for easy customization for a variety of applications. Additional digital and analog outputs with arbitrary timings can be used to control a variety of devices, such as additional shutters, acousto-optical modulators, or camera trigger pulses, for complete control and imaging of laser light.

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Xiong, Xu, Xuecheng Du, Bo Zheng, et al. "Soft Error Sensitivity Analysis Based on 40 nm SRAM-Based FPGA." Electronics 11, no. 23 (2022): 3844. http://dx.doi.org/10.3390/electronics11233844.

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Soft errors induced by radiation are the major reliability threat for SRAM-based field-programmable gate arrays (FPGAs). A more detailed analysis of the soft error sensitivity of the 40 nm SRAM-based FPGA was performed. Experimental methods for the configurable logic module, configure memory cells, and block RAM have been introduced for measuring the single event effects (SEEs) induced by alpha particles using a 241Am radiation source. The single event upset (SEU) and single event functional interrupt (SEFI) cross sections of different functional blocks have been calculated to discuss the fail

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Bhagat Kumar, B. H. K., and S. Khadar Bhasha. "Reconfigurable Real Time Signal Capturing through FPGA." Asian Journal of Engineering and Applied Technology 6, no. 1 (2017): 34–39. http://dx.doi.org/10.51983/ajeat-2017.6.1.812.

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Today all communication systems are prototyped on FPGAs before sending them for ASIC backend and fabrication. On other side the FPGAs with million gate logic densities and embedded block RAMs allowed the high speed signal capturing and storage for real time analysis. Performing various functions on the captured data allows high speed spectrum analysis. These two allow the prototyping of complex communication system on FPGA and real time analysis of implemented blocks. There are several types of interface methods possible to communicate the FPGA with a computer.. In this paper novel techniques

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22

P., Indira. "DESIGN AND ANALYSIS OF A 32-BIT PIPELINED MIPS RISC PROCESSOR." International Journal of VLSI design & Communication Systems (VLSICS) 10, no. 5 (2019): 01–18. https://doi.org/10.5281/zenodo.3529340.

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Pipelining is a technique that exploits parallelism, among the instructions in a sequential instruction stream to get increased throughput, and it lessens the total time to complete the work. . The major objective of this architecture is to design a low power high performance structure which fulfils all the requirements of the design. The critical factors like power, frequency, area, propagation delay are analysed using Spartan 3E XC3E 1600e device with Xilinx tool. In this paper, the 32-bit MIPS RISC processor is used in 6-stage pipelining to optimize the critical performance factors. The fun

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Пирогов, А. А., Ю. А. Пирогова, С. А. Гвозденко, Д. В. Шардаков, and Б. И. Жилин. "DEVELOPMENT OF RECONFIGURABLE DEVICES BASED ON PROGRAMMABLE LOGIC INTEGRATED CIRCUITS." ВЕСТНИК ВОРОНЕЖСКОГО ГОСУДАРСТВЕННОГО ТЕХНИЧЕСКОГО УНИВЕРСИТЕТА, no. 6 (January 10, 2021): 90–97. http://dx.doi.org/10.36622/vstu.2020.16.6.013.

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Цифровая фильтрация распознаваемых сигналов является непременной процедурой при обнаружении и распознавании сообщений. Под фильтрацией понимают любое преобразование сигналов, при котором во входной последовательности обрабатываемых данных целенаправленно изменяются определенные соотношения между различными параметрами сигналов. Системы, избирательно меняющие форму сигналов, устраняющие или уменьшающие помехи, извлекающие из сигналов определенную информацию и т.п., называют фильтрами. Соответственно, фильтры с любым целевым назначением являются частным случаем систем преобразования сигналов. Пр

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Pradhan, Sambhu Nath, Abhishek Nag, and Vivek Kumar Singh. "Design and analysis of a low power strategy in finite state machines implemented in configurable logic blocks." International Journal of Embedded Systems 15, no. 4 (2022): 326. http://dx.doi.org/10.1504/ijes.2022.10050473.

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Singh, Vivek Kumar, Abhishek Nag, and Sambhu Nath Pradhan. "Design and analysis of a low power strategy in finite state machines implemented in configurable logic blocks." International Journal of Embedded Systems 15, no. 4 (2022): 326. http://dx.doi.org/10.1504/ijes.2022.125440.

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Zapletina, M. A., D. V. Zhukov, and S. V. Gavrilov. "Boolean Satisfiability Methods for Modern Computer-Aided Design Problems in Microelectronics." Proceedings of Universities. ELECTRONICS 25, no. 6 (2020): 525–38. http://dx.doi.org/10.24151/1561-5405-2020-25-6-525-538.

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Currently, the methods based on a Boolean satisfiability (SAT) problem are one of the efficient approaches to solving the problem of Boolean matching and the equivalence checking of digital circuits. In combination with classic routing algorithms and optimization techniques, the SAT methods demonstrate the results exceeding the classic routing algorithms by the operation speed and the quality of obtained results. In the paper, the analysis of the modern practice of using the SAT methods in the CAD systems for VLSI has been performed. The examples of modern SAT approaches to the problems of the

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L.S, Ravi, Naveen K B, Dankan Gowda V, and Nagesh R. "Simulation and Analysis of Reversible Fault-Tolerant Gate-Based Configurable Logic Blocks for Robust FPGA Architecture and Computational Efficiency." International Journal of Electronics and Communication Engineering 12, no. 3 (2025): 68–78. https://doi.org/10.14445/23488549/ijece-v12i3p106.

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Wang, Guo Hua, and Jing Lin Sun. "BIST-Based Method for Diagnosing Multiple Faulty CLBs in FPGAs." Applied Mechanics and Materials 643 (September 2014): 243–48. http://dx.doi.org/10.4028/www.scientific.net/amm.643.243.

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This paper presents a new built-in self-test (BIST) method to realize the fault detection and the fault diagnosis of configurable logic blocks (CLBs) in FPGAs. The proposed BIST adopts a circular comparison structure to overcome the phenomenon of fault masking in diagnosing multiple faulty CLBs and improve the diagnostic resolution. To test the memory block in every CLB, different TPG structures are proposed to obtain maximum stuck-at fault coverage. For the LUT mode of the memory block, the TPG based on the LFSR is designed to provide Pseudo-exhaustive testing patterns, and for the distribute

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Della Sala, Riccardo, Davide Bellizia, and Giuseppe Scotti. "A Novel Ultra-Compact FPGA PUF: The DD-PUF." Cryptography 5, no. 3 (2021): 23. http://dx.doi.org/10.3390/cryptography5030023.

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In this paper, we present a novel ultra-compact Physical Unclonable Function (PUF) architecture and its FPGA implementation. The proposed Delay Difference PUF (DD-PUF) is the most dense FPGA-compatible PUF ever reported in the literature, allowing the implementation of two PUF bits in a single slice and provides very good values for all the most important figures of merit. The architecture of the proposed PUF exploits the delay difference between two nominally identical signal paths and the metastability features of D-Latches with an asynchronous reset input. The DD-PUF has been implemented on

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Magdaleno, Eduardo, Manuel Rodríguez Valido, David Hernández, María Balaguer, Basilio Ruiz Cobo, and David Díaz. "FPGA Implementation of Image Ordering and Packing Algorithm for TuMag Camera." Electronics 10, no. 14 (2021): 1706. http://dx.doi.org/10.3390/electronics10141706.

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The TuMag instrument is a Tunable Magnetograph that has been designed to measure the magnetic field of the sun. This instrument and others will be connected to a telescope that will be sent into the stratosphere using a balloon for an uninterrupted observation of the sun for four days in the summer of 2022. The TuMag camera is a new development for implementing the image detector of the instrument. It is based on the GPIXEL GSENSE400-BSI scientific CMOS image sensor and an FPGA device in charge of controlling the image sensor, configuring it and grabbing images. FPGA device consists of an arra

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Sánchez-Solano, Santiago, Luis F. Rojas-Muñoz, Macarena C. Martínez-Rodríguez, and Piedad Brox. "Hardware-Efficient Configurable Ring-Oscillator-Based Physical Unclonable Function/True Random Number Generator Module for Secure Key Management." Sensors 24, no. 17 (2024): 5674. http://dx.doi.org/10.3390/s24175674.

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The use of physical unclonable functions (PUFs) linked to the manufacturing process of the electronic devices supporting applications that exchange critical data over the Internet has made these elements essential to guarantee the authenticity of said devices, as well as the confidentiality and integrity of the information they process or transmit. This paper describes the development of a configurable PUF/TRNG module based on ring oscillators (ROs) that takes full advantage of the structure of modern programmable devices offered by Xilinx 7 Series families. The proposed architecture improves

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Visconti, Paolo, Stefano Capoccia, Eugenio Venere, Ramiro Velázquez, and Roberto de Fazio. "10 Clock-Periods Pipelined Implementation of AES-128 Encryption-Decryption Algorithm up to 28 Gbit/s Real Throughput by Xilinx Zynq UltraScale+ MPSoC ZCU102 Platform." Electronics 9, no. 10 (2020): 1665. http://dx.doi.org/10.3390/electronics9101665.

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The security of communication and computer systems is an increasingly important issue, nowadays pervading all areas of human activity (e.g., credit cards, website encryption, medical data, etc.). Furthermore, the development of high-speed and light-weight implementations of the encryption algorithms is fundamental to improve and widespread their application in low-cost, low-power and portable systems. In this scientific article, a high-speed implementation of the AES-128 algorithm is reported, developed for a short-range and high-frequency communication system, called Wireless Connector; a Xil

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Nagma., P., S. Ramachandran., and E. Sathishkumar. "Fault Testing and Diagnosis of Sram based FBGA using Built In Self Test Architecture." International Journal of Trend in Scientific Research and Development 2, no. 2 (2018): 717–30. https://doi.org/10.31142/ijtsrd9415.

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A new low power LP scan based built in self test BIST technique is proposed based on weighted pseudorandom test pattern generation and reseeding. A new LP scan architecture is proposed, which supports both pseudorandom testing and deterministic BIST. During the pseudorandom testing phase, an LP weighted random test pattern generation scheme is proposed by disabling a part of scan chains. During the deterministic BIST phase, the design for testability architecture is modified slightly while short. Built in Self Test BIST is a design technique that allows a circuit to test itself .The proposed m

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34

Lala, P. K., and A. Walker. "A Fine Grain Configurable Logic Block for Self-checking FPGAs." VLSI Design 12, no. 4 (2001): 527–36. http://dx.doi.org/10.1155/2001/83474.

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This paper proposes a logic cell that can be used as a building block for Self-checking FPGAs. The proposed logic cell consists of two 2-to-1 multiplexers, three 4-to-1 multiplexers and a D flip-flop. The cell has been designed using Differential Cascode Voltage Switch Logic. It is self-checking for all single transistor stuck-on and stuck-off faults as well as stuck-at faults at the inputs of each multiplexers and the D flip-flop. The multiplexers and the D flip-flop provide either correct (complementary) output in the absence of above-mentioned faults; otherwise the outputs are identical.

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Ho, Patrick W. C., Haider Abbas F. Almurib, and T. Nandha Kumar. "Configurable memristive logic block for memristive-based FPGA architectures." Integration 56 (January 2017): 61–69. http://dx.doi.org/10.1016/j.vlsi.2016.09.003.

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Meerasha, M. A., and K. Pandiyan. "Photonic configurable logic block for digital photonic integrated circuits." Electronics Letters 56, no. 21 (2020): 1130–33. http://dx.doi.org/10.1049/el.2020.2014.

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Kim, Kyungah, Duc M. Tran, and Joon-Young Choi. "Implementation of EnDat Interface Master Using Configurable Logic Block in MCU." Electronics 13, no. 6 (2024): 1101. http://dx.doi.org/10.3390/electronics13061101.

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In this study, we propose an implementation method of the Encoder Data (EnDat) interface master for slave encoders using only a configurable logic block (CLB) and a serial peripheral interface (SPI) integrated into microcontroller units. By programming the CLB device to execute logic functions and finite state machines designed for the EnDat interface master operation, we realize the EnDat and SPI clocks that are required for the EnDat interface master operation. This approach is cost-efficient because additional hardware components, such as a field-programmable gate array or a complex program

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GHOSH, BAHNIMAN, J. SIVA CHANDRA, and AKSHAYKUMAR SALIMATH. "DESIGN OF A MULTI-LAYERED QCA CONFIGURABLE LOGIC BLOCK FOR FPGAs." Journal of Circuits, Systems and Computers 23, no. 06 (2014): 1450089. http://dx.doi.org/10.1142/s0218126614500893.

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In this paper, a Multi-layered configurable logic block (CLB) unit for field programmable gate arrays (FPGAs) is proposed based on quantum-dot cellular automata (QCA) technology. The design is made in multiple layers which help to process information simultaneously, in different layers. Various components of CLB like (4 × 16) Decoder, Memory units, Multiplexers and RS-Flip flops are all designed in multiple layers using higher input majority gates to reduce the cell count and latency compared to previous designs. QCA Designer tool is used to design and simulate the model. The Coherence vector

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You, Chao, Jong-Ru Guo, Russell P. Kraft, et al. "A 5–10GHz SiGe BiCMOS FPGA with new configurable logic block." Microprocessors and Microsystems 29, no. 2-3 (2005): 121–31. http://dx.doi.org/10.1016/j.micpro.2004.06.008.

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Shokuhi, Shoaib, and Ali Hosseini. "Power Optimization of Configurable Logic Block in FPGA via Controlling Logic State of Virtual Ground Voltage." International Journal of Image, Graphics and Signal Processing 8, no. 2 (2016): 45–52. http://dx.doi.org/10.5815/ijigsp.2016.02.06.

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Bonacini, Sandro, Federico Faccio, Kostas Kloukinas, and Alessandro Marchioro. "An SEU-Robust Configurable Logic Block for the Implementation of a Radiation-Tolerant FPGA." IEEE Transactions on Nuclear Science 53, no. 6 (2006): 3408–16. http://dx.doi.org/10.1109/tns.2006.884097.

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Yogayata, Shrivastava, Verma Tarun, and Jain Rita. "Design and Implementation of Low Power High Speed 32-Bit HCSA." International Journal of VLSI and Embedded Systems 5 (April 17, 2014): 893–98. https://doi.org/10.5281/zenodo.33236.

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In the design of carry select adder, the requirement of area, speed and power consumption is of prime importance. Power dissipation is one of the most important design objectives in integrated circuits, after speed. Carry select adder (CSLA) is one of the fast adder used to perform fast arithmetic operations as we select the carry beforehand and calculate the sum output for both the carry conditions i.e. for Cin=1 or Cin=0. The most fundamental arithmetic operations in any ALU is addition. It has been ranked the most extensively used operation among a set of real-time digital signal processing

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Seif Kashani, Sayed Ali, Hossein Karimiyan Alidash, and Sandeep Miryala. "Schottky‐barrier graphene nanoribbon field‐effect transistors‐based field‐programmable gate array's configurable logic block and routing switch." IET Circuits, Devices & Systems 11, no. 6 (2017): 549–58. http://dx.doi.org/10.1049/iet-cds.2016.0349.

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M., Siva Kumar, Sanjeeva Rayudu T.C., Rafi Vempalle, and Rajesh M. "A HW/SW Co-Verification Method for ASK using FPGA Test." Journal of VLSI Design and its Advancement 6, no. 2 (2023): 41–50. https://doi.org/10.5281/zenodo.8313916.

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<em>Field programmable gate arrays (FPGAs) may be used in a wide variety of settings. If weak points in an FPGA can be isolated, then the device's shortcomings may be endured with relative ease. The research provides a recommendation and unveils a hardware/software co-verification approach for testing FPGAs. Using the adaptability and visibility of software in combination with large-speed simulation of the hardware, this process can do comprehensive, automated testing of every input/output block (IOB) and custom configurable logic block (CLB) of an FPGA. The proposed technique may detect f

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Chhetri, Sujit Rokka, Bikash Poudel, Sandesh Ghimire, Shaswot Shresthamali, and Dinesh Kumar Sharma. "Implementation of Audio Effect Generator in FPGA." Nepal Journal of Science and Technology 15, no. 1 (2015): 89–98. http://dx.doi.org/10.3126/njst.v15i1.12022.

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This paper describes the theory and implementation of audio effects such as echo, distortion and pitch-shift in Field Programmable Gate Array (FPGA). At first the mathematical formulation for generation of such effects is explained and then the algorithm is described for its implementation in FPGA using Very high speed integrated circuit hardware descriptive language (VHDL). The digital system being designed, which is synthesizable and reconfigurable, offers a great flexibility and scalability in designing and prototyping in FPGAs. The system is divided into three HDL blocks, each for echo, di

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Liu, Yizhou, Yuxuan Zhai, Hao Hu, et al. "Erasable and Field Programmable DNA Circuits Based on Configurable Logic Blocks." Advanced Science, May 2, 2024. http://dx.doi.org/10.1002/advs.202400011.

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AbstractDNA is commonly employed as a substrate for the building of artificial logic networks due to its excellent biocompatibility and programmability. Till now, DNA logic circuits are rapidly evolving to accomplish advanced operations. Nonetheless, nowadays, most DNA circuits remain to be disposable and lack of field programmability and thereby limits their practicability. Herein, inspired by the Configurable Logic Block (CLB), the CLB‐based erasable field‐programmable DNA circuit that uses clip strands as its operation‐controlling signals is presented. It enables users to realize diverse fu

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"Technique to Dynamically Reconfigure FPGAs using Control Registers." International Journal of Engineering and Advanced Technology 9, no. 1S3 (2019): 117–21. http://dx.doi.org/10.35940/ijeat.a1024.1291s319.

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Due to increased use of FPGAs computation intensive applications, the need for embedded processing system integrated with programmable logic device has also increased. Configuration of programmable logic device by the processing system through its interface improves the efficiency of the device. In order to operate as a stand-alone device and to have a better efficiency, the programmable logic device must be capable of dynamically programming its own configuration memory. In this paper, we propose a configurable logic block with a control register to improve performance of the programmable log

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"A BIST Methodology to test CLB Resources on an SRAM-Based FPGA using Complementary Gates Configuration." Regular 9, no. 12 (2020): 217–20. http://dx.doi.org/10.35940/ijitee.l7985.1091220.

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This paper primarily focuses on designing a new Built in self test (BIST) methodology to test the configurable logic blocks (CLBs) which is the heart of field programmable gate array (FPGA). The proposed methodology targets stuck-at-0/1 faults on a RAM cell in an LUT which constitutes about 90% of the total faults in the CLBs. No extra area overhead is needed to accommodate the test pattern generators (TPGs) and output responses analyzers (ORAs) as they are realized by the already existing configurable resources on the FPGA.A group of CLBs chosen as block under test (BUT) are configured as com

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M., Shiva Priya, Venkata Shesha Giridhar Akula Dr., and P. Sammulal Dr. "Deep Learning-Driven FPGA Function Block Detection Using Bit streamto-Image Transformation." June 7, 2024. https://doi.org/10.5281/zenodo.14293160.

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To enhance the security of Field Programmable Gate Arrays (FPGAs) across variousapplication scenarios, it is essential to analyse the system functions of FPGA designs. Thiscan be achieved by partitioning the FPGA bitstream into functional blocks and identifyingtheir functionalities. In this study, we present a novel deep learning-based method for FPGAfunction block detection, which involves three key steps.First, we analyze the bitstreamformat to establish the mapping between configuration bits and configurable logic blocks,addressing the discontinuity of configuration bits for individual elem

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P., Indira1 M. Kamaraju2 and Ved Vyas Dwivedi3. "DESIGN AND ANALYSIS OF A 32-BIT PIPELINED MIPS RISC PROCESSOR." April 19, 2023. https://doi.org/10.5281/zenodo.7844407.

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Pipelining is a technique that exploits parallelism, among the instructions in a sequential instruction stream to get increased throughput, and it lessens the total time to complete the work. . The major objective of this architecture is to design a low power high performance structure which fulfils all the requirements of the design. The critical factors like power, frequency, area, propagation delay are analysed using Spartan 3E XC3E 1600e device with Xilinx tool. In this paper, the 32-bit MIPS RISC processor is used in 6-stage pipelining to optimize the critical performance factors. The fun

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