Relevant bibliographies by topics / Continuous-time bandpass delta-sigma modulators

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Continuous-time bandpass delta-sigma modulators'

Author: Grafiati
Published: 3 June 2025
Last updated: 23 June 2025

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Journal articles on the topic "Continuous-time bandpass delta-sigma modulators"

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Lima, Evelyn Cristina de Oliveira, Antonio Wallace Antunes Soares, and Diomadson Rodrigues Belfort. "4th Order LC-Based Sigma Delta Modulators." Sensors 22, no. 22 (2022): 8915. http://dx.doi.org/10.3390/s22228915.

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Due to the characteristic of narrow band conversion around a central radio frequency, the Sigma Delta Modulator (ΣΔM) based on LC resonators is a suitable option for use in Software-Defined Radio (SDR). However, some aspects of the topologies described in the state-of-the-art, such as noise and nonlinear sources, affect the performance of ΣΔM. This paper presents the design methodology of three high-order LC-Based single-block Sigma Delta Modulators. The method is based on the equivalence between continuous time and discrete time loop gain using a Finite Impulse Response Digital-to-Analog Converter (FIRDAC) through a numerical approach to defining the coefficients. The continuous bandpass LC ΣΔM simulations are performed at a center frequency of 432 MHz and a sampling frequency of 1.72 GHz. To the proposed modulators a maximum Signal-to-Noise Ratio (SNR) of 51.39 dB, 48.48 dB, and 46.50 dB in a 4 MHz bandwidth was achieved to respectively 4th Order Gm-LC ΣΔM, 4th Order Magnetically Coupled ΣΔM and 4th Order Capacitively Coupled ΣΔM.
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Javidan, Mohammad, Jerome Juillard, and Philippe Benabes. "High‐loop‐delay sixth‐order bandpass continuous‐time sigma–delta modulators." IET Circuits, Devices & Systems 7, no. 6 (2013): 305–12. http://dx.doi.org/10.1049/iet-cds.2011.0313.

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Song-Bok Kim, M. Robens, S. Joeres, R. Wunderlich, and S. Heinen. "A Polyphase Filter Design for Continuous-Time Quadrature Bandpass Sigma–Delta Modulators." IEEE Transactions on Circuits and Systems I: Regular Papers 55, no. 11 (2008): 3457–68. http://dx.doi.org/10.1109/tcsi.2008.925352.

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Sobot, R., S. Stapleton, and M. Syrzycki. "Tunable continuous-time bandpass /spl Sigma//spl Delta/ modulators with fractional delays." IEEE Transactions on Circuits and Systems I: Regular Papers 53, no. 2 (2006): 264–73. http://dx.doi.org/10.1109/tcsi.2005.857085.

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Molina-Salgado, Gerardo, Alonso Morgado, Gordana Jovanovic Dolecek, and Jose M. de la Rosa. "LC-Based Bandpass Continuous-Time Sigma-Delta Modulators With Widely Tunable Notch Frequency." IEEE Transactions on Circuits and Systems I: Regular Papers 61, no. 5 (2014): 1442–55. http://dx.doi.org/10.1109/tcsi.2013.2289412.

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Raghavan, G., J. F. Jensen, J. Laskowski, et al. "Architecture, design, and test of continuous-time tunable intermediate-frequency bandpass delta-sigma modulators." IEEE Journal of Solid-State Circuits 36, no. 1 (2001): 5–13. http://dx.doi.org/10.1109/4.896223.

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Pulincherry, A., M. Hufford, E. Naviasky, and Un-Ku Moon. "A time-delay jitter-insensitive continuous-time bandpass /spl Delta//spl Sigma/ modulator architecture." IEEE Transactions on Circuits and Systems II: Express Briefs 52, no. 10 (2005): 680–84. http://dx.doi.org/10.1109/tcsii.2005.850746.

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Van Engelen, J. A. E. P., R. J. Van De Plassche, E. Stikvoort, and A. G. Venes. "A sixth-order continuous-time bandpass sigma-delta modulator for digital radio IF." IEEE Journal of Solid-State Circuits 34, no. 12 (1999): 1753–64. http://dx.doi.org/10.1109/4.808900.

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Naderi, A., M. Sawan, and Y. Savaria. "On the Design of Undersampling Continuous-Time Bandpass Delta–Sigma Modulators for Gigahertz Frequency A/D Conversion." IEEE Transactions on Circuits and Systems I: Regular Papers 55, no. 11 (2008): 3488–99. http://dx.doi.org/10.1109/tcsi.2008.925364.

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Afifi, M., Y. Manoli, and M. Keller. "A study of excess loop delay in tunable continuous-time bandpass delta–sigma modulators using RC-resonators." Analog Integrated Circuits and Signal Processing 79, no. 3 (2014): 555–68. http://dx.doi.org/10.1007/s10470-014-0294-0.

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Dissertations / Theses on the topic "Continuous-time bandpass delta-sigma modulators"

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Yang, Xi S. M. Massachusetts Institute of Technology. "Design of a continuous-time bandpass delta-sigma modulator." Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/87939.

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Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (pages 103-105).<br>An 8th-order continuous-time (CT) bandpass delta-sigma modulator has been designed and simulated in a 65 nm CMOS process. This modulator achieves in simulation 25 MHz signal bandwidth at 250 MHz center frequency with a signal-to- noise ratio (SNR) of 75.5 dB. The modulator samples at 1 GS/s while consuming 319 mW. On the system level, the feedback topology secures stability for the 8th-order system, achieving a maximum stable input range of -1.9 dBFS. A 2.5-V/1.2-V dual-supply loop filter with a feed-forward coupling path has been proposed to suppress noise and distortion. On the transistor level, a 5th -order dual-supply feed-forward operational amplifier (op amp) and a 4th-order single-supply feed-forward op amp have been designed to enable high modulator linearity and coefficient accuracy.<br>by Xi Yang.<br>S.M.
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Liu, Xuemei. "Design of a 125 mhz tunable continuous-time bandpass modulator for wireless IF applications." Texas A&M University, 2004. http://hdl.handle.net/1969.1/3257.

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Bandpass sigma-delta modulators combine oversampling and noise shaping to get very high resolution in a limited bandwidth. They are widely used in applications that require narrowband high-resolution conversion at high frequencies. In recent years interests have been seen in wireless system and software radio using sigma-delta modulators to digitize signals near the front end of radio receivers. Such applications necessitate clocking the modulators at a high frequency (MHz or above). Therefore a loop filter is required in continuous-time circuits (e.g., using transconductors and integrators) rather than discretetime circuits (e.g., using switched capacitors) where the maximum clocking rate is limited by the bandwidth of Opamp, switch’s speed and settling-time of the circuitry. In this work, the design of a CMOS fourth-order bandpass sigma-delta modulator clocking at 500 MHz for direct conversion of narrowband signals at 125 MHz is presented. A new calibration scheme is proposed for the best signal-to-noise-distortion-ratio (SNDR) of the modulator. The continuous-time loop filter is based on Gm-C resonators. A novel transconductance amplifier has been developed with high linearity at high frequency. Qfactor of filter is enhanced by tunable negative impedance which cancels the finite output impendence of OTA. The fourth-order modulator is implemented using 0.35 mm triplemetal standard analog CMOS technology. Postlayout simulation in CADENCE demonstrates that the modulator achieves a SNDR of 50 dB (~8 bit) performance over a 1 MHz bandwidth. The modulator’s power consumption is 302 mW from supply power of ± 1.65V.
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Mariano, André Augusto. "Mixed Simulations and Design of a Wideband Continuous-Time Bandpass Delta-Sigma Converter Dedicated to Software Dfined Radio Applications." Thesis, Bordeaux 1, 2008. http://www.theses.fr/2008BOR13644/document.

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La chaîne de réception des téléphones mobiles de dernière génération utilisent au moins deux étages de transposition en fréquence avant d'effectuer la démodulation en quadrature. La transposition en fréquence augmente la complexité du système et engendre de nombreux problèmes tels que la limitation de l'échelle dynamique et l'introduction de bruit issu de l'oscillateur local. Il est alors nécessaire d'envisager une numérisation du signal le plus près possible de l'antenne. Cette dernière permet la conversion directe d'un signal analogique en un signal numérique à des fréquences intermédiaires. Elle simplifie ainsi la conception globale du système et limite les problèmes liés aux mélangeurs. Pour cela, des architectures moins conventionnelles doivent être développées, comme la conversion analogique-numérique utilisant la modulation Sigma-Delta à temps continu. La modélisation comportementale de ce convertisseur analogique-numérique, ainsi que la conception des principaux blocs ont donc été l'objet de cette thèse. L'application d'une méthodologie de conception avancée, permettant la simulation mixte des blocs fonctionnels à différents niveaux d'abstraction, a permis de valider aussi bien la conception des circuits que le système global de conversion. En utilisant une architecture à multiples boucles de retour avec un quantificateur multi-bit, le convertisseur Sigma-Delta passe bande à temps continu atteint un rapport signal sur bruit (SNR) d'environ 76 dB dans une large bande de 20MHz<br>Wireless front-end receivers of last generation mobile devices operate at least two frequency translations before I/Q demodulation. Frequency translation increases the system complexity, introducing several problems associated with the mixers (dynamic range limitation, noise injection from the local oscillator, etc.). Herein, the position of the analog-to-digital interface in the receiver chain can play an important role. Moving the analog-to-digital converter (ADC) as near as possible to the antenna, permits to simplify the overall system design and to alleviate requirements associated with analog functions (filters, mixers). These currently requirements have led to a great effort in designing improved architectures as Continuous-Time Delta-Sigma ADCs. The behavioural modeling this converter, although the circuit design of the main blocks has been the subject of this thesis. The use of an advanced design methodology, allowing the mixed simulation at different levels of abstraction, allows to validate both the circuit design and the overall system conversion. Using a multi-feedback architecture associated with a multi-bit quantizer, the continuous-time Bandpass Delta-Sigma converter achieves a SNR of about 76 dB in a wide band of 20MHz
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Mahmoud, Doaa. "Convertisseur analogique-numérique de type Sigma-Delta Passe-Bande avec résonateurs à un et deux amplificateurs." Electronic Thesis or Diss., Sorbonne université, 2021. http://www.theses.fr/2021SORUS288.

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Le récepteur radio logicielle (SDR) est une technique prometteuse pour les futurs récepteurs adaptés à une variété de protocoles. Il numérise le signal RF directement en basse fréquence. Nous proposons un récepteur SDR basé sur un modulateur sigma-delta à temps continu passe-bande (CT BP ). Nous nous concentrons sur les résonateurs RC actifs pour diminuer la surface du circuit. Nous ciblons les applications au voisinage de 400 MHz, à savoir Advanced Research and Global Observation Satellite (ARGOS), Medical Implant Communication Service (MICS), Automobile Keyless system et Industrial, Scientific and Medical (ISM). Nous présentons une nouvelle comparaison détaillée entre le modulateur CT BP à résonateur à deux amplificateurs et le modulateur CT BP à résonateur à un amplificateur. Les deux modulateurs sont conçus à l'aide de transistors MOS en technologie FDSOI-28nm, où nous utilisons la polarisation du caisson pour compenser les variations de processus, de tension et de température<br>Software defined radio receiver is a promising technique for future receivers which provides a variety of protocols. It digitizes the RF signal directly to low-frequency. We propose an SDR receiver based on a bandpass sigma delta modulator. The most essential element is the loop filter, there are two main configurations, an LC tank resonator and an active RC resonator. We focus on the active RC resonators for a low chip area. We target applications in the vicinity of 400 MHz, namely Advanced Research and Global Observation Satellite, Medical Implant Communication Service. We introduce a new comparison between the two-op-amp resonator CT BP sigma delta modulator and the one-op-amp resonator CT BP sigma delta modulator. We study the sensitivity of the quality factor and the signal to noise ratio to the DC-gain op-amps in two-op-amp resonator sigma delta modulator. It also shows how, in one-op-amp resonator sigma delta modulator, the quality factor and the signal to noise ratio, are very sensitive to any variations in the capacitors values for limited DC-gain op-amps. We establish a mathematical model of the thermal-noise behaviour for two-op-amp resonator CT BP sigma delta modulator. This model matches the circuit simulator results with a good accuracy. Furthermore, we demonstrate that a high quality factor (&gt;100) of the two-op-amp resonators can be achieved by selecting the proper value of the integrator gain at a moderate DC-gain op-amp (35dB). Both sigma delta modulators are designed using flipped-well devices on fully depleted silicon on insulator technology, where we use body biasing to compensate the process, voltage and temperature variations
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Ali, Furrookh. "Noise-shaping enhancement in continuous-time delta-sigma modulators." Thesis, McGill University, 2009. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=66679.

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A technique is presented for designing high-order continuous-time (CT) delta-sigma modulators with noise-transfer-function (NTF) enhancement. This enhancement is achieved by injecting the quantization noise into the forward path of the CT delta-sigma modulator, through a passive CT filter. This passive filter introduces a real pole-zero pair into the NTF. Thus, the order of the NTF is increased, without affecting the signal transfer function (STF). The proposed NTF-enhancement technique is applied to a CT delta-sigma modulator with a capacitive-feedforward architecture, where all feedforward paths are summed within the last integrator of the delta-sigma loop filter. This eliminates the need for an analog summation amplifier at the output of the delta-sigma loop filter. Behavioral and circuit-level simulation results confirm that the proposed feedforward CT delta-sigma modulator with NTF enhancement has improved noise-shaping and stability characteristics, as compared to classical CT delta-sigma modulators.<br>Une technique est présentée pour la conception du modulateur delta-sigma en temps continu (CT) ordre-haut avec amélioration de la fonction de transfert du bruit (NTF). Cette amélioration est obtenue par injection du bruit de quantification dans la chemin feedforward du modulateur delta-sigma CT, via un filtre passif CT. Ce filtre passif introduit une paire de pôle-zéro réel dans la NTF. Donc, l'ordre de la NTF est augmenté, sans affecter la fonction de transfert du signal (STF). La technique proposé pour l'amélioration de la NTF est appliquée à un modulateur delta-sigma CT avec une architecture feedforward-capacitive, où tous les chemins feedforward sont ajoutée dans le dernier intégrateur du filtre de boucle delta-sigma . Ceci élimine la nécessité d'un amplificateur de sommation analogique à la sortie du filtre de boucle delta-sigma. Les résultats de simulation du comportement et niveau circuit confirment que la proposition du modulateur delta-sigma CT feedforward avec amélioration de la NTF a permis d'améliorer le bruit-façonnement et les caractéristiques de stabilité, par rapport aux modulateurs delta-sigma CT classiques.
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Zare-Hoseini, Hashem. "Continuous-Time Delta-Sigma Modulators with Immunity to Clock-Jitter." Thesis, University of Westminster, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.500545.

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Jiang, Yang. "Clock-jitter insensitive circuit techniques in continuous-time sigma-delta modulators." Thesis, University of Macau, 2012. http://umaclib3.umac.mo/record=b2590641.

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Lee, Hyunjoo Jenny. "The effects of excess loop delay in continuous-time sigma-delta modulators." Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/36787.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.<br>Includes bibliographical references (p. 79-80).<br>Continuous-time sigma-delta (CT-Sigma Delta) modulators have recently received great attention in the academia as well as in the industry. Despite the improved understanding of the operation of CT-Sigma Delta modulators, the problem due to excess loop delay that arises from timing mismatch and parasitic delay still remains unsolved. Thus, the thesis investigates the effects of the excess loop delay. In specific, the sensitivity of various CT-Sigma Delta topologies to the excess loop delay is explored by converting the CT modulators to its DT equivalents and realizing loop filters in state-space representations in MATLAB ©.<br>by Hyunjoo Jenny Lee.<br>M.Eng.
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Thandri, Bharath Kumar. "Design of RF/IF analog to digital converters for software radio communication receivers." Texas A&M University, 2003. http://hdl.handle.net/1969.1/5774.

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Software radio architecture can support multiple standards by performing analogto- digital (A/D) conversion of the radio frequency (RF) signals and running reconfigurable software programs on the backend digital signal processor (DSP). A slight variation of this architecture is the software defined radio architecture in which the A/D conversion is performed on intermediate frequency (IF) signals after a single down conversion. The first part of this research deals with the design and implementation of a fourth order continuous time bandpass sigma-delta (CT BP) C based on LC filters for direct RF digitization at 950 MHz with a clock frequency of 3.8 GHz. A new ADC architecture is proposed which uses only non-return to zero feedback digital to analog converter pulses to mitigate problems associated with clock jitter. The architecture also has full control over tuning of the coefficients of the noise transfer function for obtaining the best signal to noise ratio (SNR) performance. The operation of the architecture is examined in detail and extra design parameters are introduced to ensure robust operation of the ADC. Measurement results of the ADC, implemented in IBM 0.25 µm SiGe BiCMOS technology, show SNR of 63 dB and 59 dB in signal bandwidths of 200 kHz and 1 MHz, respectively, around 950 MHz while consuming 75 mW of power from ± 1.25 V supply. The second part of this research deals with the design of a fourth order CT BP ADC based on gm-C integrators with an automatic digital tuning scheme for IF digitization at 125 MHz and a clock frequency of 500 MHz. A linearized CMOS OTA architecture combines both cross coupling and source degeneration in order to obtain good IM3 performance. A system level digital tuning scheme is proposed to tune the ADC performance over process, voltage and temperature variations. The output bit stream of the ADC is captured using an external DSP, where a software tuning algorithm tunes the ADC parameters for best SNR performance. The IF ADC was designed in TSMC 0.35 µm CMOS technology and it consumes 152 mW of power from ± 1.65 V supply.
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Cherry, James A. "Theory, practice, and fundamental performance limits of high-speed data conversion using continuous-time delta-sigma modulators." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp02/NQ37061.pdf.

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Books on the topic "Continuous-time bandpass delta-sigma modulators"

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Liu, Qiyuan, Alexander Edward, Carlos Briseno-Vidrios, and Jose Silva-Martinez. Design Techniques for Mash Continuous-Time Delta-Sigma Modulators. Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-77225-7.

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Cherry, James A. Continuous-time delta-sigma modulators for high-speed A/D conversion: Theory, practice and fundamental performance limits. Kluwer Academic, 2002.

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Cherry, James A. Continuous-time delta-sigma modulators for high-speed A/D/ conversion: Theory, practice, and fundamental performance limits. Kluwer Academic Pub., 2000.

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Caldwell, Trevor C. Time-interleaved continuous-time delta-sigma modulators. 2004.

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Silva-Martinez, Jose, Qiyuan Liu, Alexander Edward, and Carlos Briseno-Vidrios. Design Techniques for Mash Continuous-Time Delta-Sigma Modulators. Springer, 2018.

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Silva-Martinez, Jose, Qiyuan Liu, Alexander Edward, and Carlos Briseno-Vidrios. Design Techniques for Mash Continuous-Time Delta-Sigma Modulators. Springer, 2018.

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Continuous-Time Delta-Sigma Modulators for High-Speed A/D Conversion. Kluwer Academic Publishers, 2002. http://dx.doi.org/10.1007/b117617.

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Zhang, Bo. Delta-sigma modulators employing continuous-time circuits and mismatch-shaped DACs. 1996.

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Zhang, Bo. Delta-sigma modulators employing continuous-time circuits and mismatch-shaped DACs. 1996.

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Breems, Lucien, and Johan Huijsing. Continuous-Time Sigma-Delta Modulation for a/d Conversion in Radio Receivers. Springer London, Limited, 2006.

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Book chapters on the topic "Continuous-time bandpass delta-sigma modulators"

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van Engelen, Jurgen, and Rudy van de Plassche. "Design of Continuous Time Bandpass SDMS." In Bandpass Sigma Delta Modulators. Springer US, 1999. http://dx.doi.org/10.1007/978-1-4757-4586-3_6.

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Liu, Qiyuan, Alexander Edward, Carlos Briseno-Vidrios, and Jose Silva-Martinez. "Delta-Sigma Modulators." In Design Techniques for Mash Continuous-Time Delta-Sigma Modulators. Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-77225-7_3.

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Arnaldi, Isacco. "Continuous Time Sigma-Delta Modulators." In Design of Sigma-Delta Converters in MATLAB®/Simulink®. Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-91539-5_7.

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Xing, Xinpeng, Peng Zhu, and Georges Gielen. "Continuous-Time Delta-Sigma Modulators." In Design of Power-Efficient Highly Digital Analog-to-Digital Converters for Next-Generation Wireless Communication Systems. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-66565-8_3.

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Liu, Qiyuan, Alexander Edward, Carlos Briseno-Vidrios, and Jose Silva-Martinez. "Design of Continuous-Time Delta-Sigma Modulators." In Design Techniques for Mash Continuous-Time Delta-Sigma Modulators. Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-77225-7_4.

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Kang, Kyung, and Peter Stubberud. "Stability Analysis of Continuous Time Sigma Delta Modulators." In Progress in Systems Engineering. Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-08422-0_71.

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Liu, Qiyuan, Alexander Edward, Carlos Briseno-Vidrios, and Jose Silva-Martinez. "Design of MASH Continuous-Time Delta-Sigma Modulators." In Design Techniques for Mash Continuous-Time Delta-Sigma Modulators. Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-77225-7_5.

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Bolatkale, Muhammed, Lucien J. Breems, and Kofi A. A. Makinwa. "Continuous-Time Delta-Sigma Modulators at High Sampling Rates." In Analog Circuits and Signal Processing. Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-05840-5_3.

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Liu, Qiyuan, Alexander Edward, Carlos Briseno-Vidrios, and Jose Silva-Martinez. "Introduction." In Design Techniques for Mash Continuous-Time Delta-Sigma Modulators. Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-77225-7_1.

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Liu, Qiyuan, Alexander Edward, Carlos Briseno-Vidrios, and Jose Silva-Martinez. "Analog-to-Digital and Digital-to-Analog Converters." In Design Techniques for Mash Continuous-Time Delta-Sigma Modulators. Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-77225-7_2.

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Conference papers on the topic "Continuous-time bandpass delta-sigma modulators"

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Honarparvar, Mohammad, Rene Landry, Frederic Nabki, and Mohamad Sawan. "Advanced modeling technique for bandpass continuous-time delta-sigma modulators." In 2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS). IEEE, 2014. http://dx.doi.org/10.1109/newcas.2014.6934052.

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Sakr, Khaled, Mohamed Dessouky, and Abd-El Halim Zekry. "Design of tunable continuous-time quadrature bandpass delta-sigma modulators." In 2011 IEEE 6th International Design and Test Workshop (IDT). IEEE, 2011. http://dx.doi.org/10.1109/idt.2011.6123110.

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Flynn, Michael P., Jaehun Jeong, Sunmin Jang, et al. "Continuous-Time Bandpass Delta-Sigma Modulators and Bitstream Processing: (Invited)." In 2020 IEEE Custom Integrated Circuits Conference (CICC). IEEE, 2020. http://dx.doi.org/10.1109/cicc48029.2020.9075928.

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Lieu, Don T., and Thomas P. Weldon. "A 10MHz continuous time bandpass delta sigma modulator." In SOUTHEASTCON 2012. IEEE, 2012. http://dx.doi.org/10.1109/secon.2012.6196890.

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Yuan, Xiaolong, Xiaobo Wu, and Svante Signell. "Continuous-Time Quadrature Bandpass Sigma Delta Modulators with Different Feedback DAC." In 2008 4th IEEE International Conference on Circuits and Systems for Communications (ICCSC 2008). IEEE, 2008. http://dx.doi.org/10.1109/iccsc.2008.129.

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Saalfeld, Tobias, Markus Scholl, Christoph Beyerstedt, Ralf Wunderlich, and Stefan Heinen. "A Tracking Quantizer for Continuous Time Quadrature Bandpass Sigma-Delta Modulators." In 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS). IEEE, 2018. http://dx.doi.org/10.1109/icecs.2018.8618055.

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Afifi, Mohamed, Ahmed Shahein, Michael Maurer, Matthias Keller, and Yiannos Manoli. "A self calibration technique for tunable continuous-time bandpass delta-sigma modulators." In 2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012. IEEE, 2012. http://dx.doi.org/10.1109/iscas.2012.6271943.

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Song-Bok Kim, Markus Robens, Ralf Wunderlich, and Stefan Heinen. "Performance limitation by finite gbw in continuous-time quadrature bandpass sigma-delta modulators." In 2009 International Symposium on Signals, Circuits and Systems - ISSCS 2009. IEEE, 2009. http://dx.doi.org/10.1109/isscs.2009.5206192.

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Mariano, A., D. Dallet, Y. Deval, and J.-B. Begueret. "High-speed multi-bit continuous-time bandpass delta-sigma modulator." In 2007 Ph.D Research in Microelectronics and Electronics Conference. IEEE, 2007. http://dx.doi.org/10.1109/rme.2007.4401814.

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10

Lai, Wen-Cheng, and Wen Liu. "Bandpass Continuous-time Sigma-delta Modulators for PLL Chip Design in Wireless Charging Module." In 2021 IEEE International Future Energy Electronics Conference (IFEEC). IEEE, 2021. http://dx.doi.org/10.1109/ifeec53238.2021.9661796.

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